NEC UPA1740TP

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1740TP
SWITCHING
N-CHANNEL POWER MOS FET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The µPA1740TP is N-channel MOS FET device that features a
low on-state resistance and excellent swiching characteristics, and
designed for high voltage applications such as DC/DC converter.
8
5
1, 2, 3
: Source
4
: Gate
5, 6, 7, 8, 9 : Drain
1
0.8 ±0.2
4.4 ±0.15
0.05 ±0.05
0.15
S
0.10 S
1.27 TYP.
+0.10
–0.05
0.12 M
4
2.9 MAX.
2.0 ±0.2
PACKAGE
Power HSOP8
8
1.1 ±0.2
0.40
1
ORDERING INFORMATION
PART NUMBER
µPA1740TP
6.0 ±0.3
4
5.2 +0.17
–0.2
+0.10
–0.05
1.49 ±0.21
1.44 TYP.
FEATURES
• High voltage: VDSS = 200 V
• Gate voltage rating: ±30 V
• Low on-state resistance
RDS(on) = 0.44 Ω MAX. (VGS = 10 V, ID = 3.5 A)
• Low input capacitance
Ciss = 420 pF TYP. (VDS = 10 V, VGS = 0 V)
• Built-in gate protection diode
• Small and surface mount package (Power HSOP8)
• Avalanche capability rated
9
4.1 MAX.
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
200
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±30
V
Drain Current (DC) (TC = 25°C)
Drain Current (pulse)
Note1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
Note2
ID(DC)
±7.0
A
ID(pulse)
±21
A
PT1
22
W
PT2
1.0
W
Tch
150
°C
Tstg
–55 to + 150
°C
IAS
7.0
A
EAS
4.9
mJ
Repetitive Avalanche Current
Note4
IAR
7.0
A
Repetitive Avalanche Energy
Note4
EAR
2.2
mJ
Notes 1.
2.
3.
4.
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
PW ≤ 10 µs, Duty Cycle ≤ 1%
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
Starting Tch = 25°C, VDD = 100 V, RG = 25 Ω, L = 100 µH, VGS = 20 → 0 V
Tch ≤ 125°C, VDD = 100 V, RG = 25 Ω
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15937EJ1V0DS00 (1st edition)
Date Published May 2002 NS CP(K)
Printed in Japan
©
2001
µPA1740TP
ELECTRICAL CHARACTERISTICS (TA = 25°C, Unless otherwise noted, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 200 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±30 V, VDS = 0 V
±10
µA
VGS(off)
VDS = 10 V, ID = 1.0 mA
4.5
V
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
2.5
3.5
3
4.5
| yfs |
VDS = 10 V, ID = 3.5 A
RDS(on)
VGS = 10 V, ID = 3.5 A
0.35
S
Ω
0.44
Input Capacitance
Ciss
VDS = 10 V
420
pF
Output Capacitance
Coss
VGS = 0 V
100
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
45
pF
Turn-on Delay Time
td(on)
VDD = 100 V, ID = 3.5 A
5
ns
Rise Time
Turn-off Delay Time
tr
VGS = 10 V
7.5
ns
td(off)
RG = 10 Ω
21
ns
7
ns
Fall Time
tf
Total Gate Charge
QG
VDD = 160 V
12
nC
Gate to Source Charge
QGS
VGS = 10 V
2
nC
Gate to Drain Charge
QGD
ID = 7.0 A
6.5
nC
VF(S-D)
IF = 7.0 A, VGS = 0 V
1.0
Reverse Recovery Time
trr
IF = 7.0 A, VGS = 0 V
110
ns
Reverse Recovery Charge
Qrr
di/dt = 50 A/µs
360
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
1.5
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
BVDSS
IAS
VDS
VDS
ID
Starting Tch
τ
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
PG.
2
50 Ω
10%
0
10%
Wave Form
VDD
D.U.T.
IG = 2 mA
90%
VDS
VGS
0
RL
VDD
Data Sheet G15937EJ1V0DS
td(on)
tr
ton
td(off)
tf
toff
µPA1740TP
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
25
100
80
60
40
20
0
20
15
10
5
0
0
25
50
75
100
125
150
175
0
25
TC - Case Temperature - °C
50
75
100
125
150
175
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
RDS(on) Limited
(VGS = 10 V)
10
PW = 100 µs
DC
1 ms
1
10 ms
0.1
Power Dissipation Limited
T C = 25°C
Single Pulse
0.01
0.1
1
10
100
1000
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(ch-A)(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
ID(DC) = 7.0 A
Rth(j-A) = 125°C/W
100
10
Rth(j-C) = 5.68°C/W
1
0.1
100 µ
1m
10 m
100 m
1
PW - Pulse Width - s
Data Sheet G15937EJ1V0DS
10
100
1000
3
µPA1740TP
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
30
100
V DS = 10 V
Pulsed
Pulsed
10
20
ID - Drain Current - A
ID - Drain Current - A
25
VGS = 10 V
15
10
5
1
T ch = 125°C
75°C
25°C
−25°C
0.1
0.01
0.001
0
0.0001
0
5
10
15
20
25
30
0
5
VDS - Drain to Source Voltage - V
VGS(off) - Gate Cut-off Voltage - V
VDS = 10 V
ID = 1 mA
4.0
3.5
3.0
2.5
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
5.0
0
25
50
75
100 125 150
1
TA = 125°C
75°C
25°C
−25°C
0.1
0.1
1
10
100
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
Pulsed
1.5
1
0.5
VGS = 10 V
0.1
1
10
100
ID - Drain Current - A
4
10
ID - Drain Current - A
2
0
0.01
VDS = 10 V
Pulsed
Tch - Channel Temperature - °C
RDS(on) - Drain to Source On-state Resistance - Ω
RDS(on) - Drain to Source On-state Resistance - Ω
-25
100
0.01
0.01
2.0
-50
15
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
4.5
10
1
Pulsed
0.9
0.8
0.7
ID = 7.0 A
3.5 A
1.4 A
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10 12 14 16 18 20
VGS - Gate to Source Voltage - V
Data Sheet G15937EJ1V0DS
µPA1740TP
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
1000
1.4
VGS = 10 V
Pulsed
1.2
1
ID = 7.0 A
0.8
Ciss
Ciss, Coss, Crss - Capacitance - pF
0.6
3.5 A
0.4
100
Coss
Crss
10
0.2
VGS = 0 V
f = 1 MHz
0
1
-50
-25
0
25
50
75
100
125
0.1
150
Tch - Channel Temperature - °C
10
100
1000
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
12
240
100
VDD = 100 V
VGS = 10 V
RG = 0 Ω
VDS - Drain to Source Voltage - V
td(on), tr, td(off), tf - Switching Time - ns
1
td(off)
10
tr
tf
td(on)
ID = 7.0 A
V DD = 160 V
100 V
40 V
220
200
180
10
160
8
140
120
6
V GS
100
80
4
60
40
2
V DS
20
0
1
0.1
1
10
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - Ω
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
100
QG - Gate Charge - nC
ID - Drain Current - A
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
100
trr - Reverse Recovery Diode - ns
IF - Diode Forward Current - A
Pulsed
10
1
VGS = 0 V
0.1
100
10
VGS = 0 V
di/dt = 100 A/ µs
1
0.01
0
0.25
0.5
0.75
1
1.25
1.5
VSD - Source to Drain Voltage - V
Data Sheet G15937EJ1V0DS
0.1
1
10
100
IF - Diode Forward Current - A
5
µPA1740TP
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
100
10
IAS = 7.0 A
EAS = 4.9 mJ
1
VDD = 100 V
RG = 25 Ω
VGS = 20 → 0 V
Starting Tch = 25°C
0.1
0.01
60
40
20
0
0.1
1
10
L - Inductive Load - mH
6
VDD = 100 V
RG = 25 Ω
VGS = 20 → 0 V
IAS ≤ 7.0 A
80
Energy Derating Factor - %
IAS - Single Avalanche Current - A
100
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - °C
Data Sheet G15937EJ1V0DS
µPA1740TP
[MEMO]
Data Sheet G15937EJ1V0DS
7
µPA1740TP
• The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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M8E 00. 4