DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA2752GR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA2752GR is Dual N-Channel MOS Field Effect Transistor designed for DC/DC converters and power management applications of notebook computers. 8 5 1 : Source 1 2 : Gate 1 7, 8 : Drain 1 FEATURES 3 : Source 2 4 : Gate 2 5, 6 : Drain 2 • Dual chip type • Low on-state resistance RDS(on)1 = 23.0 mΩ MAX. (VGS = 10 V, ID = 4.0 A) RDS(on)2 = 35.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A) RDS(on)3 = 41.0 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A) • Low Ciss: Ciss = 480 pF TYP. • Built-in G-S protection diode • Small and surface mount package (Power SOP8) 4.4 5.37 MAX. 0.8 0.15 +0.10 –0.05 1.44 6.0 ±0.3 4 0.05 MIN. 1.8 MAX. 1 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ORDERING INFORMATION PART NUMBER PACKAGE µPA2752GR Power SOP8 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V EQUIVALENT CIRCUIT Drain Current (DC) (TC = 25°C) ID(DC) ±8.0 A (1/2 Circuit) Note1 ID(pulse) ±32 A Total Power Dissipation (1 unit) Note2 PT 1.7 W Total Power Dissipation (2 unit) Note2 PT 2.0 W Drain Current (pulse) Channel Temperature Storage Temperature Tch 150 °C Tstg –55 to +150 °C Single Avalanche Current Note3 IAS 8 A Single Avalanche Energy Note3 EAS 6.4 mJ Drain Body Diode Gate Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1% 2 2. TA = 25°C, Mounted on ceramic substrate of 2000 mm x 2.2 mm 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G15716EJ1V0DS00 (1st edition) Date Published February 2002 NS CP(K) Printed in Japan © 2002 µPA2752GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±18 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.0 2.5 V | yfs | VDS = 10 V, ID = 4.0 A 3.5 7.0 RDS(on)1 VGS = 10 V, ID = 4.0 A 18.0 23.0 mΩ RDS(on)2 VGS = 4.5 V, ID = 4.0 A 25.0 35.0 mΩ RDS(on)3 VGS = 4.0 V, ID = 4.0 A 28.5 41.0 mΩ Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance S Input Capacitance Ciss VDS = 10 V 480 pF Output Capacitance Coss VGS = 0 V 190 pF Reverse Transfer Capacitance Crss f = 1 MHz 70 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 4.0 A 9.9 ns tr VGS = 10 V 6.2 ns td(off) RG = 10 Ω 25 ns 5.8 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 24 V 10 nC Gate to Source Charge QGS VGS = 10 V 1.9 nC Gate to Drain Charge QGD ID = 8.0 A 2.6 nC VF(S-D) IF = 8.0 A, VGS = 0 V 0.81 V Reverse Recovery Time trr IF = 8.0 A, VGS = 0 V 28 ns Reverse Recovery Charge Qrr di/dt = 100 A/ µs 23 nC Body Diode Forward Voltage TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% BVDSS IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE PG. 2 50 Ω 10% 0 10% Wave Form VDD D.U.T. IG = 2 mA 90% VDS VGS 0 RL VDD Data Sheet G15716EJ1V0DS td(on) tr ton td(off) tf toff µPA2752GR TYPICAL CHARACTERISTICS (TA = 25°C) DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 40 35 10 1 ID - Drain Current - A ID - Drain Current - A Pulsed VDS = 10 V TA = −25˚C 25˚C 75˚C 150˚C 0.1 30 VGS = 10 V 4.5 V 25 20 4.0 V 15 10 5 0.01 0 1 2 3 4 Pulsed 0 5 0 | yfs | - Forward Transfer Admittance - S FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 VDS = 10 V Pulsed 10 TA = 150˚C 75˚C 25˚C −25˚C 1 0.1 0.01 0.1 1 10 100 0.2 0.4 0.6 0.8 1.0 1.2 VDS - Drain to Source Voltage - V 1.4 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 80 Pulsed 60 ID = 8.0 A 40 4.0 A 20 0 0 5 10 15 20 VGS - Gate to Source Voltage - V DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 100 3.0 Pulsed VGS(off) - Gate Cut-off Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ ID - Drain Current - A RDS(on) - Drain to Source On-state Resistance - mΩ VGS - Gate to Source Voltage - V 80 VGS = 4.0 V 60 40 4.5 V 20 10 V 0 0.1 1 10 VDS = 10 V ID = 1 mA 2.5 2.0 1.5 1.0 0.5 100 ID - Drain Current - A 0 −75 −50 −25 0 25 50 75 100 125 150 175 Tch - Channel Temperature - ˚C Data Sheet G15716EJ1V0DS 3 µPA2752GR SOURCE TO DRAIN DIODE FORWARD VOLTAGE 50 Pulsed ID = 4.0 A ISD - Diode Forward Current - A 100 40 VGS = 4 V 4.5 V 30 10 V 20 10 0 −50 −25 Pulsed 4V 10 0.1 0.01 0 25 50 75 0 100 125 150 175 1.5 SWITCHING CHARACTERISTICS 1000 td(on), tr, td(off), tf - Switching Time - ns 10000 Ciss, Coss, Crss - Capacitance - pF 1.0 0.5 VSD - Source to Drain Voltage - V Tch - Channel Temperature - ˚C 1000 Ciss Coss 100 Crss VGS = 0 V f = 1 MHz 10 0.1 1 10 100 tf td(off) td(on) 10 tr 1 VDD = 15 V VGS = 10 V RG = 10 Ω 0.1 0.1 100 1 VDS - Drain to Source Voltage - V DYNAMIC INPUT/OUTPUT CHARACTERISTICS di/dt = 100 A/ µ s VGS = 0 V 100 10 1 0.1 1 10 100 14 35 VDS - Drain to Source Voltage - V 1000 10 ID - Drain Current - A REVERSE RECOVERY TIME vs. DRAIN CURRENT trr - Reverse Recovery Time - ns 0V 1 CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 12 30 VDD = 24 V 15 V 6V 25 10 VGS 20 8 15 6 10 4 100 IF - Drain Current - A 4 VGS = 10 V 5 2 VDS ID = 8.0 A 0 0 2 4 6 8 QG - Gate Charge - nC Data Sheet G15716EJ1V0DS 10 0 12 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE µPA2752GR DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE PT - Total Power Dissipation - W/package dT - Percentage of Rated Power - % 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 160 2.8 Mounted on ceramic substrate of 2000 mm2 × 2.2 mm 2.4 2 unit 2.0 1 unit 1.6 1.2 0.8 0.4 0 0 20 TA - Ambient Temperature - ˚C 40 60 80 100 120 140 160 TA - Ambient Temperature - ˚C FORWARD BIAS SAFE OPERATING AREA 100 10 (V ID(pulse) PW 1m ID(DC) 10 Po we r 10 0m ati 1 s =1 00 µs ms s Dis sip on Lim ite d 0.1 Mounted on2ceramic substrate of 2000 mm x 2.2 mm Single Pulse, 1 unit TA = 25˚C Single Pulse 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 Mounted on ceramic substrate 2 rth(t) - Transient Thermal Resistance - ˚C/W ID - Drain Current - A d ite Lim0 V) 1 ) on S( RD GS = of 2000 mm x 2.2 mm Single Pulse, 1 unit TA = 25˚C Rth(ch-A) = 73.5˚C/W 100 10 1 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 PW - Pulse Width - s Data Sheet G15716EJ1V0DS 5 µPA2752GR SINGLE AVALANCHE ENERGY DERATING FACTOR SINGLE AVALANCHE ENERGY vs. INDUCTIVE LOAD 10 RG = 25 Ω VDD = 15 V VGS = 20 0V Starting Tch = 25˚C IAS = 8 A EAS = 6.4 mJ 1 10 µ 100 µ 1m 100 80 60 40 20 100 m 0 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - ˚C L - Inductive Load - H 6 RG = 25 W VDD = 15 V 0V VGS = 20 IAS 8 A 120 Energy Derating Factor - % IAS - Single Avalanche Energy - A 100 Data Sheet G15716EJ1V0DS µPA2752GR [MEMO] Data Sheet G15716EJ1V0DS 7 µPA2752GR • The information in this document is current as of February, 2002. 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