NEC 2SK3479

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3479
SWITCHING
N-CHANNEL POWER MOS FET
ORDERING INFORMATION
DESCRIPTION
The 2SK3479 is N-channel MOS Field Effect Transistor
PART NUMBER
PACKAGE
2SK3479
TO-220AB
2SK3479-S
TO-262
2SK3479-ZJ
TO-263
2SK3479-Z
TO-220SMDNote
designed for high current switching applications.
FEATURES
• Super low on-state resistance:
RDS(on)1 = 11 mΩ MAX. (VGS = 10 V, ID = 42 A)
Note TO-220SMD package is produced only
RDS(on)2 = 13 mΩ MAX. (VGS = 4.5 V, ID = 42 A)
in Japan.
• Low Ciss: Ciss = 11000 pF TYP.
(TO-220AB)
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
100
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
V
Drain Current (DC) (TC = 25°C)
ID(DC)
±83
A
ID(pulse)
±332
A
Total Power Dissipation (TC = 25°C)
PT1
125
W
Total Power Dissipation (TA = 25°C)
PT2
1.5
W
Channel Temperature
Tch
150
°C
Drain Current (pulse)
Note1
Tstg
–55 to +150
°C
Single Avalanche Current
Note2
IAS
65
A
Single Avalanche Energy
Note2
EAS
422
mJ
Storage Temperature
(TO-262)
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, RG = 25 Ω, VGS = 20 → 0 V
(TO-263, TO-220SMD)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D15077EJ1V0DS00 (1st edition)
Date Published July 2001 NS CP(K)
Printed in Japan
©
2000, 2001
2SK3479
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = 100 V, VGS = 0 V
10
µA
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
±10
µA
2.5
V
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
| yfs |
VDS = 10 V, ID = 42 A
37
RDS(on)1
VGS = 10 V, ID = 42 A
8.8
11
mΩ
RDS(on)2
VGS = 4.5 V, ID = 42 A
10
13
mΩ
74
S
Input Capacitance
Ciss
VDS = 10 V
11000
pF
Output Capacitance
Coss
VGS = 0 V
1100
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
540
pF
Turn-on Delay Time
td(on)
VDD = 50 V, ID = 42 A
27
ns
VGS = 10 V
18
ns
RG = 0 Ω
140
ns
13
ns
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = 80 V
210
nC
Gate to Source Charge
QGS
VGS = 10 V
26
nC
Gate to Drain Charge
QGD
ID = 83 A
60
nC
VF(S-D)
IF = 83 A, VGS = 0 V
1.0
V
Reverse Recovery Time
trr
IF = 83 A, VGS = 0 V
85
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
280
nC
Body Diode Forward Voltage
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = 20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VGS
RL
Wave Form
RG
PG.
VDD
VGS
0
VGS
10%
90%
VDD
VDS
90%
IAS
VDS
VDS
ID
Starting Tch
τ
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
PG.
2
50 Ω
10%
0
10%
Wave Form
VDD
D.U.T.
IG = 2 mA
90%
VDS
VGS
0
BVDSS
RL
VDD
Data Sheet D15077EJ1V0DS
td(on)
tr
ton
td(off)
tf
toff
2SK3479
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
150
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
120
100
80
60
40
20
0
20
40
60
80
100
125
100
75
50
25
0
120 140 160
20
40
60
80
100 120 140 160
TC - Case Temperature - ˚C
TC - Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
1000
ID(pulse)
100
0
d
µs
ite V)
1
m
im 10 ID(DC)
L
s
10
=
n)
P
o
o
m
S( GS
Li we DC
s
m r
RDat V
ite Di
(
d ss
ip
at
10
PW
=
10
µs
io
n
1
TC = 25˚C
Single Pulse
0.1
0.1
1
10
100
1000
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(t) - Transient Thermal Resistance - ˚C/W
ID - Drain Current - A
10
100
Rth(ch-A) = 83.3˚C/W
10
1
Rth(ch-C) = 1˚C/W
0.1
Single Pulse
0.01
10 µ
100 µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet D15077EJ1V0DS
3
2SK3479
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
300
1000 Pulsed
ID - Drain Current - A
ID - Drain Current - A
250
100
TA = −40˚C
25˚C
75˚C
150˚C
10
1
VGS =10 V
200
4.5 V
150
100
50
0.1
1
2
3
VDS = 10 V
5
6
4
Pulsed
0
1
100 VDS = 10 V
Pulsed
10
TA = 150˚C
75˚C
25˚C
−40˚C
0.1
0.1
10
1
100
4
50
20
Pulsed
16
12
ID = 83 A
8
42 A
4
0
5
30
20
VGS = 4.5 V
10 V
20
VGS - Gate to Source Voltage - V
10
100
VDS = 10 V
ID = 1 mA
2.5
2.0
1.5
1.0
0.5
0
1
15
3.0
40
0
10
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
Pulsed
10
5
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
VGS(off) - Gate Cut-off Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
ID - Drain Current - A
RDS(on) - Drain to Source On-state Resistance - mΩ
| yfs | - Forward Transfer Admittance - S
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
0.01
0.01
4
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
1
3
2
1000
ID - Drain Current - A
−50
0
50
100
150
Tch - Channel Temperature - ˚C
Data Sheet D15077EJ1V0DS
1000
25
ISD - Diode Forward Current - A
Pulsed
20
VGS = 4.5 V
10 V
10
5
0
ID = 42 A
−50
50
0
100
VGS = 10 V
0V
10
1
0.1
0
150
VSD - Source to Drain Voltage - V
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
1000
VGS = 0 V
f = 1 MHz
Ciss
1000
Coss
Crss
1
10
100
tf
td(off)
100
td(on)
tr
10
VDD = 50 V
VGS = 10 V
RG = 0 Ω
1
0.1
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
di/dt = 100 A/µs
VGS = 0 V
100
10
160
16
120
12
80
10
VDD = 80 V
50 V
20 V
8
VGS
40
4
VDS
0
1.0
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns
1000
10
1
ID - Drain Current - A
VDS - Drain to Source Voltage - V
1
0.1
1.5
1.0
0.5
Tch - Channel Temperature - ˚C
10000
100
0.1
100
Pulsed
100
50
ID = 83 A
100
150
200
VGS - Gate to Source Voltage - V
15
100000
Ciss, Coss, Crss - Capacitance - pF
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
td(on), tr, td(off), tf - Switching Time - ns
RDS(on) - Drain to Source On-state Resistance - mΩ
2SK3479
0
250
QG - Gate Charge - nC
IF - Drain Current - A
Data Sheet D15077EJ1V0DS
5
2SK3479
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
160
100
IAS = 65 A
EAS
=4
22 m
J
10
VDD = 50 V
RG = 25 Ω
VGS = 20 → 0 V
1
10 µ
100 µ
120
100
80
60
40
20
1m
10 m
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
L - Inductive Load - H
6
VDD = 50 V
RG = 25 Ω
VGS = 20 → 0 V
IAS ≤ 65 A
140
Energy Derating Factor - %
IAS - Single Avalanche Current - A
1000
Data Sheet D15077EJ1V0DS
2SK3479
PACKAGE DRAWINGS (Unit: mm)
TO-220AB(MP-25)
2) TO-262(MP-25 Fin Cut)
φ 3.6±0.2
1.0±0.5
4.8 MAX.
10.6 MAX.
3.0±0.3
10 TYP.
1.3±0.2
4
4
1
1 2 3
12.7 MIN.
0.5±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.75±0.1
2.54 TYP.
3
1.3±0.2
6.0 MAX.
1.3±0.2
2
1.3±0.2
8.5±0.2
15.5 MAX.
5.9 MIN.
10.0 TYP.
4.8 MAX.
12.7 MIN.
1)
2.8±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
3)
Note
TO-263 (MP-25ZJ)
4) TO-220SMD(MP-25Z)
4.8 MAX.
10 TYP.
4.8 MAX.
10 TYP.
1.3±0.2
1.3±0.2
4
0
2.54 TYP.
2.8±0.2
TY
.
YP
R
0.8
T
1.4±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
8.5±0.2
3
3.0±0.5
0.7±0.2
2.54 TYP.
P.
.5R
2
0
.5R
P.
P.
TY
TY
R
.8
2.54 TYP. 0
2.8±0.2
1.4±0.2
1
1.1±0.4
8.5±0.2
3
5.7±0.4
2
1.0±0.5
4
1.0±0.5
1
2.8±0.2
2.54 TYP.
0.5±0.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
Note This package is produced only in Japan.
EQUIVALENT CIRCUIT
Drain
Remark
The diode connected between the gate and source of the transistor
serves as a protector against ESD. When this device actually used,
Body
Diode
Gate
Gate
Protection
Diode
an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Source
Data Sheet D15077EJ1V0DS
7
2SK3479
• The information in this document is current as of July, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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M8E 00. 4