HUF75321D3ST
Data Sheet
20A, 55V, 0.036 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
November 2010
Features
• 20A, 55V
• Simulation Models
- Temperature Compensating PSPICE® and SABER™
Models
- Thermal Impedance SPICE and SABER Models
Available on the web at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA75321.
Symbol
Packaging
D
JEDEC TO-252AA
G
DRAIN
(FLANGE)
S
GATE
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2010 Fairchild Semiconductor Corporation
HUF75321D3ST Rev. C
HUF75321D3ST
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
V
V
V
55
55
±20
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
20
Figure 4
Figures 6, 14, 15
93
0.625
-55 to 175
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
55
-
-
V
VDS = 50V, VGS = 0V
-
-
1
µA
VDS = 45V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figure 9)
-
0.030
0.036
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
1.6
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-251, TO-252
-
-
100
oC/W
VDD = 30V, ID ≅ 20A,
RL = 1.5Ω, VGS = 10V,
RGS = 25Ω
-
-
100
ns
-
11
-
ns
tr
-
55
-
ns
td(OFF)
-
47
-
ns
tf
-
66
-
ns
tOFF
-
-
170
ns
-
36
44
nC
-
21
26
nC
-
1.3
1.6
nC
-
3
-
nC
-
9
-
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
Gate to Source Gate Charge
Qgs
Reverse Transfer Capacitance
Qgd
©2010 Fairchild Semiconductor Corporation
VDD = 30V,
ID ≅ 20A,
RL = 1.5Ω
Ig(REF) = 1.0mA
(Figure 13)
HUF75321D3ST Rev. C
HUF75321D3ST
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
680
-
pF
-
270
-
pF
-
60
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.25
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
59
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
82
nC
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
Typical Performance Curves
25
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
20
15
10
5
0
175
25
50
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01 -5
10
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2010 Fairchild Semiconductor Corporation
HUF75321D3ST Rev. C
HUF75321D3ST
Typical Performance Curves
(Continued)
IDM, PEAK CURRENT (A)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
100
150
VGS = 20V
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
ID, DRAIN CURRENT (A)
T J = MAX RATED
T C = 25 oC
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
IAS, AVALANCHE CURRENT (A)
300
300
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV DSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
10ms
VDSS(MAX) = 55V
1
0.01
1
1
10
100
200
10
1
0.1
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
75
VGS = 20V
VGS = 10V
VGS = 8V
VGS = 7V
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
75
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
VGS = 6V
45
30
VGS = 5V
15
0
1.5
3.0
4.5
6.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
©2010 Fairchild Semiconductor Corporation
60
175 oC
45
30
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0
-55oC
25oC
7.5
0
0
VDD = 15V
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
7.5
FIGURE 8. TRANSFER CHARACTERISTICS
HUF75321D3ST Rev. C
HUF75321D3ST
Typical Performance Curves
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
(Continued)
2.0
1.5
1.0
0.5
-80
-40
0
40
80
120
160
VGS = VDS, ID = 250µA
1.0
0.8
0.6
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
40
80
120
160
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1000
1.2
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
ID = 250µA
800
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
0
TJ, JUNCTION TEMPERATURE (oC)
1.1
1.0
CISS
600
400
COSS
200
CRSS
0.9
-80
-40
0
40
80
120
160
0
200
0
10
TJ , JUNCTION TEMPERATURE (oC)
20
30
40
50
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
8
6
4
2
VDD = 30V
0
0
5
10
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
ID = 5A
15
20
25
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2010 Fairchild Semiconductor Corporation
HUF75321D3ST Rev. C
HUF75321D3ST
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2010 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
HUF75321D3ST Rev. C
HUF75321D3ST
PSPICE Electrical Model
.SUBCKT HUF75321D 2 1 3 ;
rev 4/29/98
CA 12 8 9.96e-10
CB 15 14 9.83e-10
CIN 6 8 6.18e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
ESLC
11
-
EBREAK 11 7 17 18 59.54
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
+
50
-
LDRAIN 2 5 1e-9
LGATE 1 9 3.57e-9
LSOURCE 3 7 4.25e-9
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.50e-3
RGATE 9 20 2.25
RLDRAIN 2 5 10
RLGATE 1 9 35.7
RLSOURCE 3 7 42.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 16.30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
5
51
IT 8 17 1
RLDRAIN
RSLC1
51
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*101),2.5))}
.MODEL DBODYMOD D (IS = 7.47e-13 RS = 6.45e-3 TRS1 = 2.01e-3 TRS2 = 1.21e-6 CJO = 1.02e-9 TT = 3.21e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 2.01e- 1TRS1 = 3.62e- 3TRS2 = 6.01e-7)
.MODEL DPLCAPMOD D (CJO = 9.0e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.25)
.MODEL MSTROMOD NMOS (VTO = 3.65 KP = 32.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.21e-7)
.MODEL RDRAINMOD RES (TC1 = 2.40e-2 TC2 = 1.02e-6)
.MODEL RSLCMOD RES (TC1 = 2.07e-4 TC2 = 4.67e-5)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 =0)
.MODEL RVTHRESMOD RES (TC = -3.01e-3 TC2 = -8.85e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.96e- 3TC2 = 1.39e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.85 VOFF= -4.85)
VON = -4.85 VOFF= -7.85)
VON = 0.00 VOFF= 3.00)
VON = 3.00 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2010 Fairchild Semiconductor Corporation
HUF75321D3ST Rev. C
HUF75321D3ST
SABER Electrical Model
REV April 1998
template huf75321d n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 7.47e-13, cjo = 1.02e-9, tt = 3.21e-8, m = 0.5)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 9e-10, is = 1e-30, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 1.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.65, kp = 32, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.07, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.85, voff = -4.85)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.85, voff = -7.85)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 3.0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 3.0, voff = 0)
10
RSLC1
51
i.it n8 n17 = 1
RDRAIN
6
8
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
71
11
16
6
-
8
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 =3.57e-9
l.lsource n3 n7 = 4.25e-9
RDBODY
DBREAK
50
RLGATE
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.21e-7
res.rdbody n71 n5 = 6.45e-3, tc1 = 2.01e-3, tc2 = 1.21e-6
res.rdbreak n72 n5 = 2.01e-1, tc1 = 3.62e-3, tc2 = 6.01e-7
res.rdrain n50 n16 = 5.5e-3, tc1 = 2.4e-2, tc2 = 1.02e-6
res.rgate n9 n20 = 2.25
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 35.7
res.rlsource n3 n7 = 42.5
res.rslc1 n5 n51 = 1e-6, tc1 = 2.07e-4, tc2 = 4.67e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 16.3e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.96e-3, tc2 = 1.39e-6
res.rvthres n22 n8 = 1, tc1 = -3.01e-3, tc2 = -8.85e-6
72
ISCL
+
GATE
1
RLDRAIN
RDBREAK
RSLC2
ESG
LGATE
DRAIN
2
5
-
c.ca n12 n8 = 9.96e-10
c.cb n15 n14 = 9.83e-10
c.cin n6 n8 = 6.18e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
LDRAIN
DPLCAP
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 59.54
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/101))** 2.5))
}
}
©2010 Fairchild Semiconductor Corporation
HUF75321D3ST Rev. C
HUF75321D3ST
SPICE Thermal Model
th
REV 24 February 1999
JUNCTION
HUF75321D
CTHERM1 th 6 2.7e-3
CTHERM2 6 5 3.7e-3
CTHERM3 5 4 1.2e-2
CTHERM4 4 3 3.8e-3
CTHERM5 3 2 1.4e-2
CTHERM6 2 tl 10.55
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 2.72e-2
RTHERM3 5 4 7.67e-2
RTHERM4 4 3 4.30e-1
RTHERM5 3 2 6.49e-1
RTHERM6 2 tl 8.61e-2
SABER Thermal Model
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER thermal model HUF75321D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.7e-3
ctherm.ctherm2 6 5 = 3.7e-3
ctherm.ctherm3 5 4 = 1.2e-2
ctherm.ctherm4 4 3 = 3.8-3
ctherm.ctherm5 3 2 = 1.4e-2
ctherm.ctherm6 2 tl = 10.55
rtherm.rtherm1 th 6 = 1.10e-3
rtherm.rtherm2 6 5 = 2.72e-2
rtherm.rtherm3 5 4 = 7.67e-2
rtherm.rtherm4 4 3 = 4.30e-1
rtherm.rtherm5 3 2 = 6.49e-1
rtherm.rtherm6 2 tl = 8.61e-2
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2010 Fairchild Semiconductor Corporation
CASE
HUF75321D3ST Rev. C
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