HUFA75429D3S
N-Channel UltraFET® MOSFETs
60V, 20A, 25mΩ
General Description
Applications
These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves very low on-resistance per silicon
area, resulting in outstanding performance. This device is
capable of withstanding high energy in the avalanche mode
and the diode exhibits very low reverse recovery time and
stored charge. It was designed for use in applications where
power efficiency is important, such as switching regulators,
switching convertors, motor drivers, relay drivers, low-voltage bus switches.
• Motor & Load Control
• Powertrain Management
Features
• 175°C Maximum Junction Temperature
• UIS Capability (Single Pulse and Repetitive Pulse)
• Ultra-Low On-Resistance rDS(ON) = 0.025Ω, VGS = 10V
DRAIN (FLANGE)
GATE
D
G
SOURCE
S
TO-252
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
60
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V)
20
A
Continuous (TC = 125oC, VGS = 10V, RθJA = 52oC/W)
4
A
Drain Current
ID
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Figure 4
A
312
mJ
Power dissipation
125
W
Derate above 25oC
0.83
W/oC
-55 to 175
oC
Operating and Storage Temperature
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-252
1.2
o
C/W
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-252
100
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
52
oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75429D3S
March 2002
HUFA75429D3S
Package Marking and Ordering Information
Device Marking
75429D3
Device
HUFA75429D3ST
Package
TO-252
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
75429D3
HUFA75429D3S
TO-252
Tube
N/A
75 units
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250µA, VGS = 0V
60
-
-
VDS = 55V, VGS = 0V
-
-
1
-
-
250
-
±100
nA
V
IDSS
Zero Gate Voltage Drain Current
VDS = 45V
VGS = 0V
IGSS
Gate to Source Leakage Current
VGS = ±20V
-
TC= 150oC
µA
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 20A, VGS = 10V
-
0.021
0.025
ID = 20A, VGS = 10V,
TJ = 175oC
-
0.043
0.054
-
1090
-
pF
-
376
-
pF
-
102
-
pF
65
85
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 20V
VGS = 0V to 20V
VGS = 0V to 10V V = 30V
DD
VGS = 0V to 2V ID = 20A
Ig = 1.0mA
Qg(10)
Total Gate Charge at 10V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDS = 25V, VGS = 0V,
f = 1MHz
-
36
47
nC
-
2
2.6
nC
-
4
-
nC
-
14
-
nC
(VGS = 10V)
tON
Turn-On Time
-
-
74
ns
td(ON)
Turn-On Delay Time
-
10
-
ns
tr
Rise Time
-
39
-
ns
td(OFF)
Turn-Off Delay Time
-
52
-
ns
tf
Fall Time
-
33
-
ns
tOFF
Turn-Off Time
-
-
128
ns
ISD = 20A
-
-
1.25
V
ISD = 10A
-
-
1.0
V
VDD = 30V, ID = 20A
VGS = 10V, RGS = 11Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 20A, dISD/dt = 100A/µs
-
-
55
ns
QRR
Reverse Recovered Charge
ISD = 20A, dISD/dt = 100A/µs
-
-
83
nC
Notes:
1: Starting TJ = 25°C, L = 1.56mH, IAS = 20A
©2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75429D3S
Typical Characteristics TA = 25°C unless otherwise noted
1.2
25
POWER DISSIPATION MULTIPLIER
1.0
ID, DRAIN CURRENT (A)
20
0.8
0.6
0.4
15
10
0.2
0
0
25
50
75
100
150
125
5
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
TC, CASE TEMPERATURE
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
150
175
(oC)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
600
TC = 25oC
FOR TEMPERATURES
IDM, PEAK CURRENT (A)
ABOVE 25oC DERATE PEAK
VGS = 10V
CURRENT AS FOLLOWS:
175 - TC
I = I25
100
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75429D3S
Typical Characteristics TA = 25°C unless otherwise noted
500
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
500
100µs
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515.
100
Figure 5. Forward Bias Safe Operating Area
50
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
VGS = 6V
40
ID, DRAIN CURRENT (A)
40
ID , DRAIN CURRENT (A)
Figure 6. Unclamped Inductive Switching
Capability
30
TJ = 175oC
20
TJ = 25oC
10
VGS = 7V
VGS = 5V
30
20
VGS = 4.5V
TC = 25oC
10
TJ = -55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
3
4
5
VGS , GATE TO SOURCE VOLTAGE (V)
6
0
Figure 7. Transfer Characteristics
0.5
1.0
1.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Saturation Characteristics
1.2
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.0
1.5
1.0
1.0
0.8
0.6
VGS = 10V, ID = 20A
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
200
0.4
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
Rev. A
HUFA75429D3S
Typical Characteristics TA = 25°C unless otherwise noted
3000
1.2
CISS = CGS + CGD
1000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
1.1
1.0
CRSS = CGD
COSS ≅ CDS + CGD
100
VGS = 0V, f = 1MHz
50
0.9
-80
-40
0
40
80
120
160
200
0.1
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
60
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (oC)
Figure 12. Capacitance vs Drain to Source
Voltage
10
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 4A
2
0
0
10
20
Qg, GATE CHARGE (nC)
30
40
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0.01Ω
0
tAV
Figure 14. Unclamped Energy Test Circuit
©2002 Fairchild Semiconductor Corporation
Figure 15. Unclamped Energy Waveforms
Rev. A
HUFA75429D3S
Test Circuits and Waveforms (Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS =10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tf
tr
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 18. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 19. Switching Time Waveforms
Rev. A
HUFA75429D3S
Thermal Resistance vs. Mounting Pad Area
( T JM – T A )
P DM = ----------------------------RθJA
125
RθJA = 33.32 + 23.84/(0.268+Area)
100
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
75
(EQ. 1)
50
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 20. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
23.84
( 0.268 + Area )
R θ JA = 33.32 + -------------------------------------
©2002 Fairchild Semiconductor Corporation
(EQ. 2)
Rev. A
HUFA75429D3S
PSPICE Electrical Model
.SUBCKT HUFA75429D3S 2 1 3 rev February 2002
CA 12 8 1.9e-9
CB 15 14 1.9e-9
CIN 6 8 9.7e-10
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
+
EBREAK
16
17
18
-
DBODY
MWEAK
6
MMED
MSTRO
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLGATE 1 9 35.4
RLDRAIN 2 5 10
RLSOURCE 3 7 22.1
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
VBAT
5
8
EDS
-
IT
14
+
+
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 6.5e-3
RGATE 9 20 2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
11
50
21
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
ESLC
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
5
51
LGATE 1 9 3.54e-9
LDRAIN 2 5 1e-9
LSOURCE 3 7 2.21e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 65
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
-
+
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),5))}
.MODEL DBODYMOD D (IS = 1.6e-12 N=1.02 RS = 8.1e-3 TRS1 = 3e-3 TRS2 = 2e-6 CJO = 1.43e-9 TT = 3e-8 M = 0.53 XTI=5.5)
.MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.4e-9 IS = 1e-30 N = 10 M = 0.79)
.MODEL MmedMOD NMOS (VTO=3 KP=4.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2)
.MODEL MstroMOD NMOS (VTO=3.6 KP=40 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.66 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2e1 RS=0.1)
.MODEL RBREAKMOD RES (TC1 =1.2e-3 TC2 = 1e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 2.3e-5)
.MODEL RSLCMOD RES (TC1 = 8e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 8e-6)
.MODEL RVTEMPMOD RES (TC1 = -3e-3 TC2 = -2e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1e-5)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75429D3S
SABER Electrical Model
REV February 2002
template HUFA75429D3S n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.6e-12,nl=1.02,rs=8.1e-3,trs1=3e-3,trs2=2e-6,cjo=1.43e-9,tt=3e-8,m=0.53,xti=5.5)
dp..model dbreakmod = (rs=2e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.4e-9,isl=10e-30,nl=10,m=0.79)
m..model mmedmod = (type=_n,vto=3,kp=4.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.6,kp=40,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.66,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-8)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.1,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.1)
c.ca n12 n8 = 1.9e-9
c.cb n15 n14 = 1.9e-9
DPLCAP 5
c.cin n6 n8 = 9.7e-10
LDRAIN
DRAIN
2
10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RLDRAIN
RSLC1
51
RSLC2
ISCL
spe.ebreak n11 n7 n17 n18 = 65
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
RDRAIN
6
8
ESG
GATE
1
EVTEMP
RGATE + 18 22
9
20
6
EBREAK
+
17
18
-
MMED
RLGATE
CA
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBODY
MWEAK
MSTRO
l.lgate n1 n9 = 3.54e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 2.21e-9
res.rlgate n1 n9 = 35.4
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.1
11
EVTHRES
16
21
+ 19 8
+
LGATE
DBREAK
50
-
CIN
8
LSOURCE
7
RSOURCE
S1A
12
13
8
S2A
14
13
S1B
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
-
SOURCE
3
19
IT
14
VBAT
5
8
EDS
-
res.rbreak n17 n18 = 1, tc1=1.2e-3,tc2=1e-7
res.rdrain n50 n16 = 6.5e-3, tc1=1.2e-2,tc2=2.3e-5
res.rgate n9 n20 = 2
res.rslc1 n5 n51 = 1e-6, tc1=8e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.1e-2, tc1=1e-3,tc2=8e-6
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=-2e-6
+
8
22
RVTHRES
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 5))}
}
©2002 Fairchild Semiconductor Corporation
Rev. A
th
HUFA75429D3S
SPICE Thermal Model
JUNCTION
REV 23 February 2002
HUFA75429D3S
CTHERM1 TH 6 2.49e-3
CTHERM2 6 5 7.6e-3
CTHERM3 5 4 7.8e-3
CTHERM4 4 3 8e-3
CTHERM5 3 2 1.3e-2
CTHERM6 2 TL 7.52e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 6e-3
RTHERM2 6 5 1.4e-2
RTHERM3 5 4 9e-2
RTHERM4 4 3 1.8e-1
RTHERM5 3 2 3.1e-1
RTHERM6 2 TL 3.35e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model HUFA75429D3S
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =2.49e-3
ctherm.ctherm2 6 5 =7.6e-3
ctherm.ctherm3 5 4 =7.8e-3
ctherm.ctherm4 4 3 =8e-3
ctherm.ctherm5 3 2 =1.3e-2
ctherm.ctherm6 2 tl =7.52e-2
rtherm.rtherm1 th 6 =6e-3
rtherm.rtherm2 6 5 =1.4e-2
rtherm.rtherm3 5 4 =9e-2
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =3.1e-1
rtherm.rtherm6 2 tl =3.35e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
CTHERM6
RTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
Rev. A
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