19-2384; Rev 0; 4/02 Differential PECL/ECL/LVPECL/LVECL Receiver/Driver Features ♦ Improved Second Source of the MC10EP16D ♦ +3.0V to +5.5V Differential PECL/LVPECL Operation ♦ -3.0V to -5.5V Differential ECL/LVECL Operation ♦ Low 17mA Supply Current ♦ 20ps Part-to-Part Skew ♦ 172ps Propagation Delay ♦ Minimum 300mV Output at 3GHz ♦ Output Low for Open Input ♦ ESD Protection >2kV (Human Body Model) ♦ On-Chip Reference for Single-Ended Input Applications Precision Clock Buffer Ordering Information PART Low-Jitter Data Repeater TEMP RANGE PIN-PACKAGE MAX9321BESA -40°C to +85°C 8 SO MAX9321BEUA* -40°C to +85°C 8 TSSOP *Future product—contact factory for availability. Pin Configuration D VCC VIH VBB D VIL MAX9321B N.C. 1 (CONNECTED TO D) 50kΩ D 2 VOH Q VOH - VOL VOL Q 8 VCC 80kΩ 7 Q 60kΩ 6 Q D 3 100kΩ 5 VEE VBB 4 TSSOP/SO Figure 1. Switching with Single-Ended Inputs ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9321B General Description The MAX9321B low-skew differential receiver/driver is designed for clock and data distribution. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to an input as a reference voltage. The MAX9321B features ultra-low propagation delay (172ps) and part-to-part skew (20ps) with 24mA maximum supply current, making this device ideal for clock buffering or repeating. For interfacing to differential PECL and LVPECL signals, these devices operate over a +3.0V to +5.5V supply range, allowing high-performance clock and data distribution in systems with a nominal 3.3V or 5.0V supply. For differential ECL and LVECL operation, this device operates from a -3.0V to -5.5V supply. The MAX9321B is offered in industry-standard 8-pin SO and TSSOP packages. MAX9321B Differential PECL/ECL/LVPECL/LVECL Receiver/Driver ABSOLUTE MAXIMUM RATINGS VCC to VEE .............................................................................6.0V D or D ...................................................VEE - 0.3V to VCC + 0.3V D or D with the Other Input Floating ....VCC - 5.0V to VCC + 0.3V D to D .................................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current .................................................±0.6mA Continuous Power Dissipation (TA +70°C) 8-Pin TSSOP (derate 4.5mW/°C above +70°C) ...........362mW 8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW Junction-to-Ambient Thermal Resistance in Still Air 8-Pin TSSOP ............................................................+221°C/W 8-Pin SO...................................................................+170°C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin TSSOP ............................................................+155°C/W 8-Pin SO.....................................................................+99°C/W Junction-to-Case Thermal Resistance 8-Pin TSSOP ..............................................................+39°C/W 8-Pin SO.....................................................................+40°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (D, D, Q_, Q_) .................................>2kV Soldering Temperature (10s) ...........................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL -40°C CONDITIONS MIN TYP +25°C MAX MIN VCC VCC 1.145 TYP +85°C MAX MIN VCC VCC 1.085 TYP MAX UNITS DIFFERENTIAL INPUT (D, D) Single-Ended Input High Voltage VIH VBB connected to D (VIL for VBB connected to D), Figure 1 VCC 1.21 Single-Ended Input Low Voltage VIL VBB connected to D (VIH for VBB connected to D), Figure 1 (Note 4) VEE VCC 1.61 VEE VCC 1.545 VEE VCC V VCC 1.485 V VCC V High Voltage of Differential Input VIHD VEE + 1.2 Low Voltage of Differential Input VILD VEE VCC 0.1 VEE VCC 0.1 VEE VCC 0.1 V VIHD VILD 0.1 3.0 0.1 3.0 0.1 3.0 V 150 µA Differential Input Voltage Input High Current IIH D Input Low Current IILD D Input Low Current IILD 2 VCC VEE + 1.2 150 VCC VEE + 1.2 150 VCC - VEE ≤ 3.8V -100 +100 -100 +100 -100 +100 VCC - VEE ≥ 3.8V -140 +140 -140 +140 -140 +140 VCC - VEE ≤ 3.8V -150 +150 -150 +150 -150 +150 VCC - VEE ≥ 3.8V -175 +175 -175 +175 -175 +175 _______________________________________________________________________________________ µA µA Differential PECL/ECL/LVPECL/LVECL Receiver/Driver (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2.0V. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL -40°C CONDITIONS MIN TYP +25°C MAX MIN TYP +85°C MAX MIN TYP MAX UNITS DIFFERENTIAL OUTPUT (Q, Q) Single-Ended Output High Voltage VOH Figure 1 VCC 1.135 VCC 0.885 VCC 1.07 VCC 0.82 VCC 1.01 VCC 0.76 V Single-Ended Output Low Voltage VOL Figure 1 VCC 1.935 VCC 1.68 VCC 1.87 VCC 1.62 VCC 1.81 VCC 1.56 V VOH VOL Figure 1 550 VCC 1.51 Differential Output Voltage 820 550 820 550 820 mV REFERENCE (VBB) Reference Voltage Output VBB IBB = ±0.5mA (Note 5) POWER SUPPLY Supply Current IEE (Note 6) VCC 1.31 16 VCC 1.445 24 VCC 1.245 17 VCC 1.385 24 18 VCC 1.185 V 24 mA AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 7) PARAMETER SYMBOL -40°C CONDITIONS +25°C +85°C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 145 184 235 145 172 245 130 167 230 ps ps Differential Input-toOutput Delay tPLHD, tPHLD Figure 2 Part-to-Part Skew tSKPP (Note 8) 25 90 20 100 20 100 fIN = 1.5GHz, clock pattern (Note 9) 1.7 2.8 1.7 2.8 1.7 2.8 fIN = 3.0GHz, clock pattern (Note 9) 0.6 Added Random Jitter ps (RMS) tRJ 1.5 0.6 1.5 0.6 1.5 _______________________________________________________________________________________ 3 MAX9321B DC ELECTRICAL CHARACTERISTICS (continued) MAX9321B Differential PECL/ECL/LVPECL/LVECL Receiver/Driver AC ELECTRICAL CHARACTERISTICS (continued) (VCC - VEE = 3.0V to 5.5V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3.0V. Typical values are at VCC - VEE = 5V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 7) PARAMETER SYMBOL -40°C CONDITIONS MIN Added Deterministic Jitter Switching Frequency Output Rise/ Fall Time (20% to 80%) tDJ 3.0Gpbs 223 - 1 PRBS pattern (Note 9) VOH - VOL ≥ 300mV, clock pattern, Figure 2 +25°C TYP MAX 57 80 3.0 MIN +85°C TYP MAX 57 80 3.0 MIN UNITS TYP MAX 57 80 3.0 fMAX tR, tF ps (P-P) GHz VOH - VOL ≥ 550mV, clock pattern, Figure 2 2.0 Figure 2 65 2.0 112 135 65 2.0 118 135 65 121 135 ps Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temperature range. Note 4: Maximum differential input voltage limit of ±3V also applies to single-ended use. Note 5: Use VBB as a reference for inputs on the same device only. Note 6: All pins open except VCC and VEE. Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 9: Device jitter added to the input signal. 4 _______________________________________________________________________________________ Differential PECL/ECL/LVPECL/LVECL Receiver/Driver OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY 16 15 0.7 125 TRANSITION TIME (ps) 17 TRANSITION TIME vs. TEMPERATURE 130 MAX9321B toc02 0.8 OUTPUT AMPLITUDE (V) 18 0.6 0.5 0.4 0.3 13 115 110 0.2 100 0.1 95 35 60 85 90 0 TEMPERATURE (°C) 500 1000 1500 2000 2500 3000 3500 PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD VIHD - VILD = 0.5V tPLHD 180 175 170 165 -15 160 35 60 85 PROPAGATION DELAY vs. TEMPERATURE 200 tPLHD 190 180 170 tPHLD 160 tPHLD 10 TEMPERATURE (°C) 210 PROPAGATION DELAY (ps) 190 185 -40 FREQUENCY (MHz) MAX9321B toc05 10 MAX9321B toc04 -15 tF 105 0 -40 tR 120 14 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 0.9 MAX9321B toc01 19 MAX9321B toc03 SUPPLY CURRENT, IEE vs. TEMPERATURE 150 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 VIHD (V) -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9321B Typical Operating Characteristics (VCC = 5V, VEE = 0V, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) Differential PECL/ECL/LVPECL/LVECL Receiver/Driver MAX9321B Pin Description FUNCTION PIN NAME 1 N.C. 2 D Noninverting Differential Input. 80kΩ pullup to VCC, 60kΩ pulldown to VEE. 3 D Inverting Differential Input. 50kΩ pullup to VCC and 100kΩ pulldown to VEE. 4 VBB 5 VEE 6 Q Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V. 7 Q Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V. 8 VCC No Connection Reference Output Voltage. Connect to the inverting or noninverting input to provide a reference for singleended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise leave open. Negative Supply Voltage Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Detailed Description The MAX9321B low-skew differential receiver/driver is designed for clock and data distribution. For interfacing to differential PECL/LVPECL signals, this device operates over a +3.0V to +5.5V supply range, allowing highperformance clock and data distribution in systems with a nominal 3.3V or 5V supply. For differential ECL/ LVECL operation, this device operates from a -3.0V to -5.5V supply. Inputs The differential input can be configured to accept a single-ended input. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a reference. For example, the differential input is converted to a noninverting, single-ended input by connecting VBB to D and connecting the single-ended input to D. An inverting input is obtained by connecting VBB to D and connecting the single-ended input to D. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. The VBB reference can source or sink 0.5mA. Use VBB only for an input on the same device as the VBB reference. The maximum magnitude of the differential input from D to D is 3.0V. This limit also applies to the difference between any reference voltage input and a singleended input. The differential input has bias resistors that drive the output to a differential low when the inputs are open. The inverting input is biased with a 50kΩ pullup to VCC and a 100kΩ pulldown to VEE. The noninverting input is biased with an 80kΩ pullup to VCC and a 60kΩ pulldown to VEE. 6 Specifications for the high and low voltage of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Outputs Output levels are referenced to VCC and are considered PECL/LVPECL or ECL/LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the output is PECL/LVPECL. The output is ECL/LVECL when VCC is connected to GND and VEE is connected to a negative supply. A single-ended input of at least VBB ±100mV or a differential input of at least ±100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. Applications Information Supply Bypassing Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel ground vias for low inductance. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC (if the VBB reference is not used, it can be left open). Traces Input and output trace characteristics affect the performance of the MAX9321B. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and _______________________________________________________________________________________ Differential PECL/ECL/LVPECL/LVECL Receiver/Driver MAX9321B D VIHD VIHD - VILD VILD D tPLHD tPHLD Q VOH VOH - VOL VOL Q 80% 80% 0V (DIFFERENTIAL) (Q) - (Q) 0V (DIFFERENTIAL) 20% 20% tR tF Figure 2. Differential Transition Time and Propagation Delay Timing Diagram across cables. Reduce skew within a differential pair by matching the electrical length of the traces. Chip Information TRANSISTOR COUNT: 162 Output Termination Terminate outputs through 50Ω to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from the differential output, terminate both outputs. For example, when Q is used as a singleended output, terminate both Q and Q. Package Information For the latest package outline information, go to www.maximic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.