SAMSUNG S3C7044

S3C7044/C7048/P7048
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to S3C7044/C7048.
With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications.
Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide
operating voltage range.
1-1
PRODUCT OVERVIEW
S3C7044/C7048/P7048
FEATURES SUMMARY
Memory
Bit Sequential Carrier
•
512 × 4-bit RAM
•
•
4096 × 8-bit ROM: S3C7044
•
8192 × 8-bit ROM: S3C7048
36 I/O Pins
•
Input only: 4 pins
•
I/O: 24 pins
•
N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
•
Data memory bank 15
8-Bit Basic Timer
•
4 interval timer functions
Two 8-Bit Timer/Counters
•
Programmable interval timer
•
External event counter function
•
Timer/counters clock outputs to TCLO0 and
TCLO1 pins
Supports 16-bit serial data transfer in arbitrary
format
Interrupts
•
3 external interrupt vectors
•
4 internal interrupt vectors
•
2 quasi-interrupts
Power-Down Modes
•
Idle: Only CPU clock stops
•
Stop: System clock stops
Oscillation Sources
•
Crystal or Ceramic for system clock
•
Oscillation frequency : 0.4 – 6.0MHz
•
CPU clock divider circuit (by 4. 8, or 64)
Instruction Execution Times
•
0.95, 1.91, 15.3 µs at 4.19 MHz
•
0.67, 1.33, 10.7 µs at 6.0 MHz
Watch Timer
Operating Temperature
•
Time interval generation: 0.5 s, 3.9 ms at
4.19 MHz
•
•
4 frequency outputs to the BUZ pin
Operating Voltage Range
8-Bit Serial I/O Interface
- 40 °C to 85 °C
•
1.8 V to 5.5 V (Main)
•
2.0 V to 5.5 V (OTP)
•
8-bit transmit/receive mode
•
8-bit receive mode
Package Types
•
LSB-first or MSB-first transmission selectable
•
1-2
42-pin SDIP, 44-pin QFP
S3C7044/C7048/P7048
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and
shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles.
CPU REGISTERS
program counter
A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instruction stored in a look-up table in the ROM.
Whenever a reset operation or an interrupt occurs, bits PC12 though PC0 are set to the vector address.
Stack pointer
An 8-bit stack pointer (SP) stores addresses for stack operation. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero.
During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.
The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 4096 x 8-bit (S3C7404), 8192 x 8-bit (S3C7408) ROM is divided into four areas:
 16-byte area for vector addresses
 96-byte instruction reference area
 16-byte general-purpose area (0010 – 001FH)
 3968-byte area for general-purpose program memory (S3C7404)
 8064-byte area for general-purpose program memory (S3C7408)
The vector address area is used mostly during reset operation and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.
The REF instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020H – 007FH.
REF can also reference three-byte instruction such as JP or CALL. So that a REF instruction can reference these
instruction, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to
the reference area with the format TJP or TCALL instead of the normal instruction name. Unused location in the
REF instruction look-up area can be allocated to general-purpose use.
1-3
PRODUCT OVERVIEW
S3C7044/C7048/P7048
DATA MEMORY
Overview
The 512 x 4bit data memory has five areas:
 32 x 4-bit working register area
 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area
 256 x 4-bit general-purpose area in bank 1
 128 x 4-bit area in bank 15 for memory-mapped I/O addresses
The data memory area is also organized as three memory banks  bank0, bank1, and bank15. You use the
select memory bank instruction (SMB) to select one of the banks as working data memory.
Data stored in RAM location are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.
Data Memory addressing modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the
EMB flag is logic zero, only location 00H–7FH of bank 0 and bank 15 can be accessed. When the EMB flag is
set to logic one, all three data memory banks can be accessed based on the current SMB value.
Working registers
The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.
Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL, and HL are used as address pointers for indirect addressing.
To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.
Bit sequential carrier
The bit sequential carrier (BSC) mapped in data memory bank 15 is a 16-bit general register that you can
manipulate using 1-, 4-, and 8-bit RAM control instructions.
Using the BSC register, addresses and bit location can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.
1-4
S3C7044/C7048/P7048
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C
SC2
SC1
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
S3C7044/C7048 using an external clock source, the external clock signal should be input to Xin, and its inverted
signal to Xout.
A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies  fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
of 3.91 milliseconds at 4.19MHz. The following components support interrupt processing:
 Interrupt enable flags
 Interrupt request flags
 Interrupt priority registers
 Power-down termination circuit
1-5
PRODUCT OVERVIEW
S3C7044/C7048/P7048
POWER-DOWN
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode and the STOP instruction initiates stop mode.
In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.
Stop mode effects only the system clock. In stop mode system clock oscillation stops completely, halting all
operations except for a few basic peripheral functions. RESET or an interrupt (with the exception of INT0) can be
used to terminate either idle or stop mode.
RESET
When a RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode
when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)
has elapsed, normal CPU operation resumes.
I/O PORTS
The S3C7044/C7048 has 9 I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FFCH in
bank 15 of the RAM.
There are 4 input pins, 24 configurable I/O pins, and 8 software n-channel open-drain I/O pins, for a total of 36
I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using
bit manipulation instructions.
TIMERS AND TIMER/COUNTERS
The timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch
timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected CPU clock
frequency.
The programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock
frequencies for output, and dividing external clock signals. The 8-bit timer/counter 0 generates a clock signal
(SCK) for the serial I/O interface.
The watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its
functions include real-time and watch-time measurement, and frequency outputs for buzzer sound.
SERIAL I/O INTERFACE
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
 8-bit mode register
 Clock selector circuit
 8-bit buffer register
 3-bit serial clock counter
The serial I/O circuit can be set either to transmit-and-receive or to receive-only mode. MSB-first or LSB-first
transmission is also selectable. The serial interface operates with an internal or an external clock source, or using
the clock signal generated by the 8-bit timer/counter 0. To modify transmission frequency, the appropriate bits in
the serial I/O mode register (SMOD) must be manipulated.
1-6
S3C7044/C7048/P7048
PRODUCT OVERVIEW
BLOCK DIAGRAM
BASIC
TIMER
INT0, INT1,
INT2,INT4
8-BIT
TIMER/
COUNTER 0
RESET
INTERRUPT
CONTROL
BLOCK
Xin
Xout
CLOCK
8-BIT
TIMER/
COUNTER 1
INTERNAL
INTERRUPTS
P4.0–P4.3
I/O PORT 4
P5.0–P5.3
I/O PORT 5
INSTRUCTION DECODER
P6.0–P6.3 /
KS0–KS3
I/O PORT 6
P7.0–P7.3 /
KS4–KS7
I/O PORT 7
P8.0–P8.3
I/O PORT 8
ARITHMETIC
AND
LOGIC UNIT
WATCH
TIMER
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PROGRAM
STATUS WORD
I/O PORT 0
SERIAL
I/O
INPUT
PORT 1
I/O PORT 2
STACK
POINTER
I/O PORT 3
512 x 4-BIT
DATA
MEMORY
P0.0 /SCK
P0.1 / SO
P0.2 / SI
P0.3 / BTCO
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
P3.2
P3.3
PROGRAM MEMORY
4 KBYTE: S3C7404
8 KBYTE: S3C7408
Figure 1-1. S3C7044/C7048/P0408 Block Diagram
1-7
PRODUCT OVERVIEW
S3C7044/C7048/P7048
PIN ASSIGNMENTS
S3C7044/C7048
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP-600)
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P0.3/BTCO
P0.2/SI
P0.1/SO
P0.0/SCK
P8.3
P8.2
P8.1
P8.0
P3.3
P3.2
P3.1/TCL1
P3.0/TCL0
VDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XIN
XOUT
RESET
P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
TEST
Figure 1-2. S3C7044/C7048 Pin Assignment Diagrams (42-SDIP Pakage)
1-8
S3C7044/C7048/P7048
PRODUCT OVERVIEW
44
43
42
41
40
39
38
37
36
35
34
NC
P3.3
P3.2
P3.1/TCL1
P3.0/TCL0
VDD
TEST
P4.3
P4.2
P4.1
P4.0
1
2
3
4
5
6
7
8
9
10
11
S3C7044/C7048
(44-QFP-1010B)
33
32
31
30
29
28
27
26
25
24
23
NC
P8.0
P8.1
P8.2
P8.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BTCO
P2.0/TCLO0
P2.1/TCLO1
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
VSS
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P2.3/BUZ
P2.2/CLO
12
13
14
15
16
17
18
19
20
21
22
P5.3
P5.2
P5.1
P5.0
RESET
XOUT
XIN
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
Figure 1-3. S3C7044/C7048 Pin Assignment Diagrams (44-QFP Pakage)
1-9
PRODUCT OVERVIEW
S3C7044/C7048/P7048
PIN DESCRIPTIONS
Table 1-1. S3C7044/C7048/P0408 Pin Description
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
12 (28)
11 (27)
10 (26)
9 (25)
SCK
SO
SI
BTCO
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are assignable by software to
pins P1.0, P1.1, and P1.2.
4 (20)
3 (19)
2 (18)
1 (17)
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
P2.3
I/O
Same as port 0.
8 (24)
7 (23)
6 (22)
5 (21)
TCLO0
TCLO1
CLO
BUZ
P3.0
P3.1
P3.2
P3.3
I/O
Same as port 0.
20 (38)
19 (37)
18 (36)
17 (35)
TCL0
TCL1
P4.0–P4.3
I/O
4-bit I/O ports.
N-channel open-drain output up to 9 volts.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to support 8-bit data
transfer.
8-bit unit pull-up resistors are assignable by mask
option.
26–23
(44–41)
30–27
(4–1)
–
I/O
4-bit I/O ports.
1-bit or 4-bit read/write and test is possible.
Port 6 pins are individually software configurable as
input or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins
(port 6 only).
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
37–34
(11–8)
41–38
(15–12)
KS0–KS3
4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Pins are individually software configurable as input or
output.
4-bit pull-down resistors are software assignable;
pull-down resistors are automatically disabled for
output pins.
16–13
(32–29)
–
P5.0–P5.3
P6.0–P6.3
P7.0–P7.3
P8.0–P8.3
I/O
NOTE: Parentheses indicate pin number for 44 QFP package.
1-10
KS4–KS7
S3C7044/C7048/P7048
PRODUCT OVERVIEW
Table 1-1. S3C7044/C7048 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share
Pin
SCK
I/O
Serial I/O interface clock signal
12 (28)
P0.0
SO
I/O
Serial data output
11 (27)
P0.1
SI
I/O
Serial data input
10 (26)
P0.2
BTCO
I/O
Basic timer clock output (2 Hz, 16 Hz, 64 Hz, or 256
Hz at 4.19 MHz)
9 (25)
P0.3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. INT0 is synchronized to system
clock.
4, 3
(20, 19)
P1.0, P1.1
INT2
I
Quasi-interrupt with detection of rising edges
2 (18)
P1.2
INT4
I
External interrupt with detection of rising and falling
edges.
1 (17)
P1.3
TCLO0
I/O
Timer/counter 0 clock output
8 (24)
P2.0
TCLO1
I/O
Timer/counter 1 clock output
7 (23)
P2.1
CLO
I/O
Clock output
6 (22)
P2.2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
4.19 MHz for buzzer sound
5 (21)
P2.3
TCL0
I/O
External clock input for timer/counter 0
20 (38)
P3.0
TCL1
I/O
External clock input for timer/counter 1
19 (37)
P3.1
KS0–KS3
I/O
Quasi-interrupt inputs with falling edge detection
37–34
(11–8)
41–38
(15–12)
P6.0–P6.3
KS4–KS7
P7.0–P7.3
VDD
–
Power supply
21 (39)
–
VSS
–
Ground
42 (16)
–
RESET
I
Reset signal
31 (5)
–
Xin, Xout
–
Crystal, ceramic, or RC oscillator signal for system
clock (For external clock input, use Xin and input
Xin's reverse phase to Xout)
33, 32
(7, 6)
–
TEST
–
Test signal input (must be connected to VSS)
22 (40)
–
NC
–
No connection (must be connected to VSS)
(33, 34)
–
NOTE: Parentheses indicate pin number for 44 QFP package.
1-11
PRODUCT OVERVIEW
S3C7044/C7048/P7048
Table 1-2. Overview of S3C7044/C7048 Pin Data
Pin Names
Share Pins
I/O Type
Reset Value
Circuit Type
I/O
Input
D-1
P0.0–P0.3
SCK, SO, SI, BTCO
P1.0–P1.2
INT0, INT1, INT2
I
Input
A-3
P1.3
INT4
I
Input
B-4
P2.0–P2.3
TCLO0, TCLO1, CLO,
BUZ
I/O
Input
D
P3.0–P3.1
TCL0, TCL1
I/O
Input
D-1
P3.2–P3.3
–
I/O
Input
D
P4.0–P4.3
P5.0–P5.3
–
I/O
(NOTE)
E-2
I/O
Input
D-1
P6.0–P6.3
P7.0–P7.3
KS0–KS3
KS4–KS7
P8.0–P8.3
–
I/O
Input
D-2
Xin, Xout
–
–
–
–
RESET
–
I
–
B
TEST
–
I
–
–
NC
–
–
–
–
VDD, VSS
–
–
–
–
NOTE: When pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to
high impedance.
1-12
S3C7044/C7048/P7048
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL
PULL-UP
RESISTOR
IN
IN
N-CHANNEL
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B
VDD
PULL-UP
RESISTOR
PULL-UP RESISTOR
ENABLE
P-CHANNEL
IN
SCHMITT TRIGGER
IN
SCHMITT TRIGGER
Figure 1-5. Pin Circuit Type A-3
Figure 1-7. Pin Circuit Type B-4
1-13
PRODUCT OVERVIEW
S3C7044/C7048/P7048
VDD
PULL-UP
RESISTOR
VDD
P-CHANNEL
DATA
OUT
N-CHANNEL
OUTPUT
DISABLE
RESISTOR
ENABLE
P-CHANNEL
DATA
CIRCUIT
TYPE C
OUTPUT
DISABLE
I/O
SCHMITT TRIGGER
Figure 1-8. Pin Circuit Type C
DATA
VDD
PULL-UP
RESISTOR
OUTPUT
DISABLE
OUTPUT
DISABLE
CIRCUIT
TYPE C
I/O
CIRCUIT TYPE A
RESISTOR
ENABLE
DATA
Figure 1-10. Pin Circuit Type D-1
P-CHANNEL
CIRCUIT
TYPE C
RESISTOR
ENABLE
N-CHANNEL
I/O
PULL-DOWN
RESISTOR
CIRCUIT TYPE A
Figure 1-9. Pin Circuit Type D
1-14
Figure 1-11. Pin Circuit Type D-2
S3C7044/C7048/P7048
PRODUCT OVERVIEW
VDD
I/O
DATA
OUTPUT
DISABLE
N-CHANNEL
Figure 1-12. Pin Circuit Type E-2
1-15
S3C7044/C7048/P7048
13
ELECTRICAL DATA
ELECTRICAL DATA
In this section, information on S3C7044/C7048 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN and XOUT
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
S3C7044/C7048/P7048
Table 13-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Supply Voltage
VDD
–
Input Voltage
VI1
Output Voltage
VO
–
Output Current High
I OH
One I/O port active
– 15
All I/O ports active
– 30
One I/O port active
+ 30 (Peak value)
Output Current Low
I OL
All I/O ports except 4 and 5
Rating
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
mA
mA
+ 15 (note)
All I/O ports, total
+ 100 (Peak value)
+ 60 (note)
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
NOTE: The values for output current low ( IOL ) are calculated as peak value ×
13-2
Duty .
S3C7044/C7048/P7048
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input High
Voltage
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
–
0.3 VDD
V
VIH1
All input pins except those
specified below for VIH2 – VIH4
0.7 VDD
VIH2
Ports 0, 1, 3, 6, 7, and RESET
0.8 VDD
VIH3
Ports 4 and 5 with pull-up
resistors assigned
0.7 VDD
Ports 4 and 5 are open-drain
VIH4
XIN and XOUT
VIL1
All input pins except those
specified below for VIL2–VIL3
VIL2
Ports 0, 1, 3, 6, 7, and RESET
VIL3
Xin and Xout
Output High
Voltage
VOH
IOH = – 1 mA
Ports except 1, 4, and 5
Output Low
Voltage
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 4, 5 only
Input Low
Voltage
VDD – 0.1
–
0.2 VDD
0.1
VDD – 1.0
–
–
V
–
–
2
V
VDD = 1.8 to 5.5 V
IOL = 1.6mA
VOL2
0.4
VDD = 4.5 V to 5.5 V
IOL= 4 mA
All output ports except ports 4,5
2
VDD = 1.8 to 5.5 V
IOL = 1.6mA
Input High
Leakage
Current
Input Low
Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN and XOUT
ILIL1
VI = 0 V
All input pins except below and
0.4
–
–
3
µA
20
–
–
–3
µA
RESET
ILIL2
VI = 0 V
XIN and XOUT only
– 20
13-3
ELECTRICAL DATA
S3C7044/C7048/P7048
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Output High
Leakage Current
ILOH
Output Low
Leakage Current
Pull-Up
Resistor
Min
Typ
Max
Units
VO = VDD, All output pins
–
–
3
µA
ILOL
VO = 0 V, All output pins
–
–
–3
µA
RL1
VI = 0 V; VDD = 5 V
Ports 0, 1 (not P1.3), 2, 3, 6, 7
25
47
100
kΩ
VDD = 3 V
50
95
200
VO = VDD – 2V; VDD = 5V
Ports 4 and 5 only
15
47
70
VDD = 3 V
10
45
60
VDD = 5 V; VI = 0V; RESET
100
220
400
VDD = 3 V
200
450
800
VDD = 5 V; VI = VDD; Port 8
25
47
100
VDD = 3 V
50
95
200
–
3.9
8.0
4.19 MHz
2.9
5.5
6.0 MHz
1.8
4.0
4.19 MHz
1.3
3.0
1.3
2.5
4.19 MHz
1.2
1.8
6.0 MHz
0.5
1.5
4.19 MHz
0.44
1.0
0.2
3
0.1
2
RL2
RL3
Pull-Down
Resistor
RL4
Supply
IDD1
Current (1)
Conditions
Run mode; VDD = 5 V ± 10%
Crystal oscillator; C1 = C2 = 22 pF
VDD = 3 V ± 10%
IDD2
Run mode; VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF
VDD = 3 V ± 10%
IDD3
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
6.0 MHz
6.0 MHz
–
–
kΩ
mA
mA
µA
NOTES
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors.
2. The supply current assumes a CPU clock of fx/4.
13-4
S3C7044/C7048/P7048
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Crystal
Oscillator
Xin
External
Clock
Xin
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
–
4
ms
MHz
C2
Xout
C1
Parameter
Stabilization time (2)
VDD = 3 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
–
10
ms
MHz
C2
Xout
Stabilization time (2)
VDD = 3 V
XIN input frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
VDD = 1.8 V to 5.5 V
0.4
–
4.2
–
83.3
–
1250
XIN input high and low
level width (tXH, tXL)
ns
NOTES
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
13-5
ELECTRICAL DATA
S3C7044/C7048/P7048
Table 13-4. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Input Capacitance
Output Capacitance
I/O Capacitance
Symbol
CIN
Condition
Min
Typ
Max
Units
–
–
15
pF
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
0.95
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
f = 1 MHz; Unmeasured
pins are returned to VSS
COUT
CIO
Table 13-5. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Time
TCL0, TCL1 Input
Frequency
Symbol
tCY
f TI0, f TI1
Conditions
VDD = 1.8 V to 5.5V
TCL0, TCL1 Input
High, Low Width
SCK Cycle Time
tTIH0, tTIL0
tTIH1, tTIL1
tKCY
1
VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
–
–
µs
–
–
µs
–
–
µs
External SCK source
Internal SCK source
670
VDD = 1.8 V to 5.5 V
3200
External SCK source
SCK High, Low
Width
tKH, tKL
Internal SCK source
3800
VDD = 2.7 V to 5.5 V
335
External SCK source
Internal SCK source
tKCY/
2 – 50
VDD = 1.8 V to 5.5 V
1600
External SCK source
Internal SCK source
13-6
tKCY/
2 – 150
S3C7044/C7048/P7048
ELECTRICAL DATA
Table 13-5. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
SI Setup Time to
SCK High
Symbol
tSIK
Conditions
VDD = 2.7 V to 5.5 V
Min
Typ
Max
Units
100
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
150
VDD = 1.8 V to 5.5 V
150
External SCK source
SI Hold Time to
SCK High
tKSI
Internal SCK source
500
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
400
VDD = 1.8 V to 5.5 V
600
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V
500
–
External SCK source
Internal SCK source
250
VDD = 1.8 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input Low
Width
tINTH, tINTL
tRSL
1000
INT0
(2)
INT1, INT2, INT4, KS0 - KS7
10
Input
10
–
–
µs
–
–
µs
NOTES
1. R(1Kohm) and C(100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
13-7
ELECTRICAL DATA
S3C7044/C7048/P7048
CPU CLOCK
Main Osc. Freq. ( Divided by 4 )
1.5 MHz
6 MHz
1.05 kHz
4.2 MHz
15.625 kHz
400 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-6. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.5
–
5.5
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
0
–
–
µs
Oscillator stabilization wait
tWAIT
Released by RESET
–
217/fx
–
ms
Released by interrupt
–
(2)
–
ms
time
(1)
VDDDR = 1.5 V
–
NOTES
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-8
S3C7044/C7048/P7048
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
EXECUTION OF
STOP INSTRUCTION
VDDDR
RESET
tWAIT
t SREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
13-9
ELECTRICAL DATA
S3C7044/C7048/P7048
Timing Waveforms (continued)
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 13-4. A.C. Timing Measurement Points (Except for XIN)
1 / fx
tXL
tXH
Xin
VDD – 0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at XIN
1 / fTI
tTIL
tTIH
0.8 VDD
TCL
0.2 VDD
Figure 13-6. TCL Timing
13-10
S3C7044/C7048/P7048
ELECTRICAL DATA
tRSL
RESET
0.2 VDD
Figure 13-7. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
KS0 to KS7
tINTH
0.8 VDD
0.2 VDD
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
13-11
ELECTRICAL DATA
S3C7044/C7048/P7048
tKCY
tKL
tKH
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
0.8 VDD
INPUT DATA
SI
0.2 VDD
tKSO
SO
OUTPUT DATA
Figure 13-9. Serial Data Transfer Timing
13-12
S3C7044/C7048/P7048
14
ECHANICAL DATA
MECHANICAL DATA
This section contains the following information about the device package:
— 42-SDIP-600 package dimensions in millimeters
— 44-QFP-1010B package dimensions in millimeters
0 ~ 15 °
#22
15.24
42-SDIP-600
0.50 ± 0.1
1.00 ± 0.1
1.778
5.08 MAX
(1.77)
3.30 ± 0.3
39.10 ± 0.2
3.50 ± 0.2
#21
0.51 MIN
#1
0.25 +0. 1
– 0.05
14.00 ± 0.2
#42
NOTE: Dimensions are in millimeters.
Figure 14-1. 42-SDIP-600 Package Dimensions
14-1
MECHANICAL DATA
S3C7044/C7048/P7048
0~8°
13.20 ± 0.30
0.15 + 0.1
– 0.05
0.1 MAX
10.00 ± 0.2
44-QFP-1010B
0.80 ± 0.20
13.20 ± 0.30
10.00 ± 0.2
#44
#1
1.00
+ 0.10
0.35 - 0.05
0.80
0.0 MIN
2.05 ± 0.1
2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 14-2. 44-QFP-1010B Package Dimensions
14-2
S3C7044/C7048/P7048
15
S3P7048 OTP
S3P7048 OTP
OVERVIEW
The S3P7048 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7044/C7048 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P7048 is fully compatible with the S3C7044/C7048, both in function and in pin configuration. Because of
its simple programming requirements, the S3P7048 is ideal for use as an evaluation chip for the
S3C7044/C7048.
NOTE:
S3P7048
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP-600)
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P0.3/BTCO
P0.2/SI
P0.1/SO
P0.0/SCK
P8.3
P8.2
P8.1
P8.0
P3.3
P3.2
SDAT/P3.1/TCL1
SCLK/P3.0/TCL0
VDD/VDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS/VSS
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XIN
XOUT
RESET/RESET
RESET
P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
TEST/TEST
The bolds indicate an OTP pin name.
Figure 15-1. S3P7048 Pin Assignments (42-SDIP Package)
15-1
S3P7048 OTP
S3C7044/C7048/P7048
44
43
42
41
40
39
38
37
36
35
34
NC
P3.3
P3.2
SDAT/P3.1/TCL1
SCLK/P3.0/TCL0
VDD/VDD
TEST/TEST
P4.3
P4.2
P4.1
P4.0
1
2
3
4
5
6
7
8
9
10
11
S3P7048
(44-QFP-1010B)
33
32
31
30
29
28
27
26
25
24
23
NC
P8.0
P8.1
P8.2
P8.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BTCO
P2.0/TCLO0
P2.1/TCLO1
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
VSS/VSS
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P2.3/BUZ
P2.2/CLO
12
13
14
15
16
17
18
19
20
21
22
P5.3
P5.2
P5.1
P5.0
RESET/RESET
RESET
XOUT
XIN
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
NOTE:
The bolds indicate an OTP pin name.
Figure 15-2. S3P7048 Pin Assignments (44-QFP Package)
15-2
S3C7044/C7048/P7048
S3P7048 OTP
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.1
SDAT
19 (37)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P3.0
SCLK
20 (38)
I/O
Serial clock pin. Input only pin.
TEST
VPP(TEST)
22 (40)
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in writing
mode and when 5 V is applied, OTP is in reading
mode. (Option)
RESET
RESET
31 (5)
I
Chip initialization
VDD/VSS
VDD/VSS
21/42(39/16)
I
Logic power supply pin. VDD should be tied to
+5 V during programming.
NOTE: ( ) means the 44-QFP OTP pin number.
Table 15-2. Comparison of S3P7048 and S3C7044/C7048 Features
Characteristic
S3P7048
S3C7044/C7048
Program Memory
8 K-byte EPROM
4 K-byte mask ROM: S3C7044
8 K-byte mask ROM: S3C7048
Operating Voltage (VDD)
2.0 V to 5.5 V
1.8 V to 5.5V
OTP Programming Mode
VDD = 5 V, VPP(TEST)=12.5V
Pin Configuration
42SDIP, 44QFP
42SDIP, 44QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7048, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-3. Operating Mode Selection Criteria
VDD
5V
Vpp
REG/
Address
R/W
Mode
(TEST)
MEM
(A15-A0)
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15-3
S3P7048 OTP
S3C7044/C7048/P7048
Table 15-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Input High
Voltage
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
–
0.3 VDD
V
VIH1
All input pins except those
specified below for VIH2 – VIH4
0.7 VDD
VIH2
Ports 0, 1, 3, 6, 7, and RESET
0.8 VDD
VIH3
Ports 4 and 5 with pull-up
resistors assigned
0.7 VDD
Ports 4 and 5 are open-drain
VIH4
XIN and XOUT
VIL1
All input pins except those
specified below for VIL2–VIL3
VIL2
Ports 0, 1, 3, 6, 7, and RESET
VIL3
XIN and XOUT
Output High
Voltage
VOH
IOH = – 1 mA
Ports except 1, 4, and 5
Output Low
Voltage
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 4, 5 only
Input Low
Voltage
VDD – 0.1
–
0.2 VDD
0.1
VDD – 1.0
–
–
V
–
–
2
V
VDD = 2.0 to 5.5 V
IOL = 1.6mA
VOL2
0.4
VDD = 4.5 V to 5.5 V
IOL= 4 mA
All output ports except ports 4,5
2
VDD = 2.0 to 5.5 V
IOL = 1.6mA
Input High
Leakage
Current
Input Low
Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN and XOUT
ILIL1
VI = 0 V
All input pins except below and
–
–
3
VI = 0 V
XIN and XOUT only
µA
20
–
–
–3
RESET
ILIL2
15-4
0.4
– 20
µA
S3C7044/C7048/P7048
S3P7048 OTP
Table 15-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Output High
Leakage Current
ILOH
Output Low
Leakage Current
Pull-Up
Resistor
Min
Typ
Max
Units
VO = VDD, All output pins
–
–
3
µA
ILOL
VO = 0 V, All output pins
–
–
–3
µA
RL1
VI = 0 V; VDD = 5 V
Ports 0, 1 (not P1.3), 2, 3, 6, 7
25
47
100
kΩ
VDD = 3 V
50
95
200
VO = VDD – 2V; VDD = 5V
Ports 4 and 5 only
15
47
70
VDD = 3 V
10
45
60
VDD = 5 V; VI = 0V; RESET
100
220
400
VDD = 3 V
200
450
800
VDD = 5 V; VI = VDD; Port 8
25
47
100
VDD = 3 V
50
95
200
–
3.9
8.0
4.19 MHz
2.9
5.5
6.0 MHz
1.8
4.0
4.19 MHz
1.3
3.0
1.3
2.5
4.19 MHz
1.2
1.8
6.0 MHz
0.5
1.5
4.19 MHz
0.44
1.0
0.2
3
0.1
2
RL2
RL3
Pull-Down
Resistor
RL4
Supply
IDD1
Current (1)
Conditions
Run mode; VDD = 5 V ± 10%
Crystal oscillator; C1 = C2 = 22 pF
VDD = 3 V ± 10%
IDD2
Run mode; VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF
VDD = 3 V ± 10%
IDD3
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
6.0 MHz
6.0 MHz
–
–
kΩ
mA
mA
µA
NOTES
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors.
2. The supply current assumes a CPU clock of fx/4.
15-5
S3P7048 OTP
S3C7044/C7048/P7048
Table 15-5. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Instruction Cycle
Time
TCL0, TCL1 Input
Frequency
Symbol
tCY
f TI0, f TI1
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 2.0 V to 5.5 V
0.95
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
VDD = 2.0 V to 5.5V
TCL0, TCL1 Input
High, Low Width
SCK Cycle Time
tTIH0, tTIL0
tTIH1, tTIL1
tKCY
1
VDD = 2.7 V to 5.5 V
0.48
VDD = 2.0 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
–
–
µs
–
–
µs
–
–
µs
External SCK source
Internal SCK source
670
VDD = 2.0 V to 5.5 V
3200
External SCK source
SCK High, Low
Width
tKH, tKL
Internal SCK source
3800
VDD = 2.7 V to 5.5 V
335
External SCK source
Internal SCK source
tKCY/
2 – 50
VDD = 2.0 V to 5.5 V
1600
External SCK source
Internal SCK source
15-6
tKCY/
2 – 150
S3C7044/C7048/P7048
S3P7048 OTP
Table 15-5. A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
SI Setup Time to
SCK High
Symbol
tSIK
Conditions
VDD = 2.7 V to 5.5 V
Min
Typ
Max
Units
100
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
150
VDD = 2.0 V to 5.5 V
150
External SCK source
SI Hold Time to
SCK High
tKSI
Internal SCK source
500
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
400
VDD = 2.0 V to 5.5 V
600
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V
500
–
External SCK source
Internal SCK source
250
VDD = 2.0 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input Low
Width
tINTH, tINTL
tRSL
1000
INT0
(2)
INT1, INT2, INT4, KS0 - KS7
10
Input
10
–
–
µs
–
–
µs
NOTES
1. R (1KΩ) and C (100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
15-7
S3P7048 OTP
S3C7044/C7048/P7048
CPU CLOCK
Main Osc. Freq. ( Divided by 4 )
1.5 MHz
6 MHz
1.05 kHz
4.2 MHz
15.625 kHz
400 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 15-3. Standard Operating Voltage Range
15-8
S3C7044/C7048/P7048
S3P7048 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 15-4. OTP Programming Algorithm
15-9