× SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 D D D D D DW OR N PACKAGE (TOP VIEW) Asynchronous Operation Organized as 64 Words by 4 Bits Data Rates From 0 to 30 MHz 3-State Outputs Package Options Include Plastic Small-Outline Packages (DW), Plastic J-Leaded Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N) OE IR SI D0 D1 D2 D3 GND description The SN74ALS234 is a 256-bit memory utilizing advanced low-power Schottky IMPACT technology. It features high speed with fast fall-through times and is organized as 64 words by 4 bits. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SO OR Q0 Q1 Q2 Q3 RST IR OE NC VCC SO FN PACKAGE (TOP VIEW) A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS234 is designed to process data at rates from 0 to 30 MHz in a bit-parallel format, word by word. SI D0 NC D1 D2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 OR Q0 NC Q1 Q2 D3 GND NC RST Q3 Data is written into memory on the rising edge of the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words NC − No internal connection stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low. Status of the SN74ALS234 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full. When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high during this time, the OR flag pulses high indicating valid data at the outputs (see Figure 3). When the FIFO is full, data can be shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR will go high. If SI is still high when IR goes high, data at the inputs are automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output (see Figure 4). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 description (continued) The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data will not be shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is high. OE does not affect the IR or OR. The SN74ALS234 is characterized for operation from 0°C to 70°C. logic symbol† FIFO 64 × 4 SI CTR 3 5 + /C1 G2 SO 15 14 3CT > 0 OR (CT > 0) G4 4− 2 2CT < 64 G3 IR (CT < 64) G5 CT = 0 9 RST OE D0 D1 D2 D3 R 1 EN6 4 1D 5 13 6 12 6 11 7 10 Q0 Q1 Q2 Q3 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. functional block diagram D0 D1 D2 D3 IR SI RST 4 5 6 7 2 3 FIFO Input Stage 62 × 4 Bit Register FIFO Output Stage InputControl Logic RegisterControl Logic OutputControl Logic 9 Pin numbers shown are for the DW and N packages. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 13 12 11 10 15 14 Q0 Q1 Q2 Q3 SO OR × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 SI RST D1 D2 D3 D0 OE Word 64 Data Inputs logic diagram (positive logic) Word 63 Words 4 − 6 Same as 3 or 63 Word 3 Word 2 Word 1 Q1 Q2 Q3 SO OR IR Q0 Data Outputs • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 timing diagram RST SI D3 −D0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1 Don’t Care W2 W1 W2 W63 W64 W1 SO Word 1 Q3 −Q0 Invalid† Word 2 Word 1‡ Word 2 Word 3 IR OR Clear Shift In W1 Full Shift Out W2 Empty † The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO. ‡ While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written into the FIFO will stack up behind the first word and will not appear at the output until SO is taken low. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 RST tsu SI ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ th tsu D3 −D0 tPLH IR tPHL tPLH Full tPHL tPLH Empty OR tpd tpd Q3 −Q0 NOTE: SO is low. Figure 1. Master Reset and Data-In Waveforms SO tPLH OR tPHL tPLH IR Full td(SOL-QX) Q3 −Q0 tdis ten tpd OE NOTE: SI is low. Figure 2. Data-Out Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 ÎÎÎ ÎÎÎ D3 −D0 tsu th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SI SO tPLH OR tw Empty td(QV-ORH) Q3 −Q0 Invalid Figure 3. Data Fall-Through Waveforms SO SI IR tPLH tw Full Full ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ D3 −D0 Figure 4. Automatic Data-In Waveforms absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70° Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current fclock Clock frequency tw Pulse duration tsu Setup time before SI↑ th TA Hold time, data after SI↑ High-level input voltage MIN NOM MAX 4.5 5 5.5 2 Q outputs − 2.6 IR and OR − 0.4 Q outputs 24 IR and OR 8 0 SI or SO High or low 15 RST Low 15 Data V V 0.8 SI or SO UNIT 30 V mA mA MHz ns 0 High (inactive) RST ns 15 17 Operating free-air temperature ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, MIN TYP† II = − 18 mA IOH = − 1 mA MAX UNIT −1.2 V Any Q VCC = 4.5 V IR, OR VCC = 4.5 V, 0.4 VCC = 4.5 V IOL = 12 mA IOL = 24 mA 0.25 Any Q 0.35 0.5 0.25 0.4 VCC = 4.5 V IOL = 4 mA IOL = 8 mA 0.35 0.5 IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH VOL IR, OR ICC VCC = 5.5 V IOH = − 2.6 mA IOH = − 0.4 mA 2.4 3.2 2.7 3.4 V 20 −30 V µA −20 µA 0.1 mA 20 µA −0.1 mA −112 mA Low 100 145 High 97 142 mA Disabled 103 148 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 switching characteristics (see Figure 5) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C MIN fmax tw‡ tw§ TYP SO 35 30 IR high 15 8 ns OR high 19 8 ns 6 Q valid after SO↓ 13 SI↓ SI↓ tpd tPHL SO↓ tPLH tPLH¶ SO↓ Q 9 −5 12 4 ns ns 800 350 1000 20 26 8 30 16 21 6 25 OR 600 800 350 1000 ns Q 13 17 4 22 ns 23 27 7 33 20 24 6 30 IR SO↑ OR ns ns ns IR 600 800 350 1000 OR 22 26 10 34 IR 17 21 6 27 RST↓ Q 14 17 5 19 ns OE↑ Q 7 13 2 15 ns 13 ns tPHL tPLH RST↓ tPHL tdis ten OE↓ Q 6 12 2 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4). § The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3). ¶ Data throughput or fall-through times 8 MHz 600 SI↑ SO↓ MAX 30 Q valid before OR↑ tPLH tPLH¶ MIN 35 td(SOL-QX) SI↓ MAX UNIT SI td(QV-ORH) tpd tPHL VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns ns × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 PARAMETER MEASUREMENT INFORMATION 7V SWITCH POSITION TABLE Open S1 R1 = 500 Ω From Output Under Test CL = 50 pF (see Note A) Test Point R2 = 500 Ω TEST S1 tPLH tPHL Open Open tPZH tPZL Open Closed tPHZ Open tPLZ Closed LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V 0.3 V tw 3.5 V Timing Input 1.3 V Data Input 3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATION 1.3 V 1.3 V 3.5 V Low-Level Pulse 0.3 V th tsu 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 1.3 V tPZL 1.3 V tPLZ 0.3 V In-Phase Output Waveform 1 S1 Closed (see Note C) VOH 1.3 V VOL 1.3 V VOL 0.3 V tPZH Waveform 2 S1 Open (see Note C) VOH 1.3 V 1.3 V tPHZ tPLH tPHL Out-of-Phase Output 3.5 V tPHL tPLH 1.3 V 0.3 V 3.5 V Input (see Note B) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 5. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 × SDAS106B − OCTOBER 1986 − REVISED SEPTEMBER 1993 APPLICATION INFORMATION IR SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST IR RST SI RST IR SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST RST SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST OR RST IR RST SO RST RST Figure 6. 192-Word by 12-Bit Expansion 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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