STMICROELECTRONICS STM32F101T8U6TR

STM32F101x8
STM32F101xB
Medium-density access line, ARM-based 32-bit MCU with 64 or
128 KB Flash, 6 timers, ADC and 7 communication interfaces
Features
■
Core: ARM 32-bit Cortex™-M3 CPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
LQFP48
7 x 7 mm
■
Memories
– 64 to 128 Kbytes of Flash memory
– 10 to 16 Kbytes of SRAM
■
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■
■
■
LQFP100
14 x 14 mm
LQFP64
10 x 10 mm
VFQFPN48
7 × 7 mm
VFQFPN36
6 × 6 mm
■
Six timers
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
■
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
Up to 7 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
■
CRC calculation unit, 96-bit unique ID
■
ECOPACK® packages
Debug mode
– Serial wire debug (SWD) and JTAG
interfaces
Table 1.
Reference
DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
■
1 × 12-bit, 1 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■
Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
May 2010
Device summary
Part number
STM32F101x8
STM32F101C8,
STM32F101R8
STM32F101V8,
STM32F101T8
STM32F101xB
STM32F101RB,
STM32F101VB,
STM32F101CB
STM32F101TB
Doc ID 13586 Rev 13
1/85
www.st.com
1
Contents
STM32F101x8, STM32F101xB
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
2/85
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
2.3.6
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.18
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.19
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20
Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.21
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.22
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.23
ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.24
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.25
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Contents
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
6
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 33
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52
5.3.12
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.13
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.14
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.15
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.16
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.17
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.2
Evaluating the maximum junction temperature for an application . . . . . 77
Doc ID 13586 Rev 13
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Contents
STM32F101x8, STM32F101xB
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features and peripheral counts (STM32F101xx medium-density
access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Medium-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Maximum current consumption in Sleep mode, code running from Flash
or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 42
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Doc ID 13586 Rev 13
5/85
List of tables
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
6/85
STM32F101x8, STM32F101xB
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 71
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 72
LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data. . . . . . . . 73
LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 74
LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 75
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
STM32F101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F101xx medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 21
STM32F101xx medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F101xx medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F101xx medium-density access line VFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . 23
STM32F101xx medium-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . 23
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 37
Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 37
Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 68
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 69
VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 73
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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List of figures
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
8/85
STM32F101x8, STM32F101xB
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 74
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For
more details on the whole STMicroelectronics STM32F101xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F101xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 13586 Rev 13
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Description
2
STM32F101x8, STM32F101xB
Description
The STM32F101xB and STM32F101x8 medium-density access line family incorporates the
high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16
Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB
buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, and up to
three USARTs), one 12-bit ADC and three general-purpose 16-bit timers.
The STM32F101xx medium-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx medium-density access line family includes devices in four different
packages ranging from 36 pins to 100 pins. Depending on the device chosen, different sets
of peripherals are included, the description below gives an overview of the complete range
of peripherals proposed in this family.
These features make the STM32F101xx medium-density access line microcontroller family
suitable for a wide range of applications:
●
Application control and user interface
●
Medical and handheld equipment
●
PC peripherals, gaming and GPS platforms
●
Industrial applications: PLC, inverters, printers, and scanners
●
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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STM32F101x8, STM32F101xB
Device overview
Table 2.
Device features and peripheral counts (STM32F101xx medium-density
access line)
Peripheral
STM32F101Tx STM32F101Cx
STM32F101Rx
STM32F101Vx
Flash - Kbytes
64
128
64
128
64
128
64
128
SRAM - Kbytes
10
16
10
16
10
16
10
16
Communication Timers
2.1
Description
General -purpose
3
3
3
3
SPI
1
2
2
2
2C
1
2
2
2
2
3
3
3
1
10 channels
1
10 channels
1
16 channels
1
16 channels
26
37
51
80
I
USART
12-bit synchronized ADC
number of channels
GPIOs
CPU frequency
36 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 8)
Junction temperature: –40 to +105 °C (see Table 8)
VFQFPN36
LQFP48,
VFQFPN48
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LQFP64
LQFP100
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Description
STM32F101x8, STM32F101xB
STM32F101xx medium-density access line block diagram
TPIU
SW/JTAG
Trace/trig
SWD
Ibus
Cortex M3 CPU
Fmax : 36 MHz
NVIC
Trace
Cont rol ler
pbus
Dbus
NVIC
Syst em
AHB: Fmax =36 MHz
7 channels
SUPPLY
SUPERVISION
NRST
VDDA
VSSA
POR / PDR
Rst
PVD
Int
PCLK1
PCLK 2
HCLK
FCLK
@VDD
PLL &
CLOCK
MANAGT
XTAL OSC
4-16 MHz
PB[ 15:0]
GPIOB
PC[15:0]
GPIOC
PD[15:0]
GPIOD
PE[15:0]
GPIOE
MOSI,MISO,
SCK,NSS as AF
OSC_IN
OSC_OUT
RC 8 MHz
IWDG
RC 42 kHz
Stand by
in terface
@VDDA
VBAT
@VBAT
RTC
AWU
AHB2
APB 1
Back up
reg
OSC32_IN
OSC32_OUT
TAMPER-RTC
Backu p i nterf ace
APB2 : Fmax = 36 MHz
GPIOA
VDD = 2 to 3.6V
VSS
@VDD
64 bit
EXTI
WAKEUP
PA[ 15:0]
RX,TX, CTS, RTS,
Smart Card as AF
Flash 128 KB
XTAL 32 kHz
AHB2
APB2
80AF
VOLT. REG.
3.3V TO 1.8V
SRAM
16 KB
GP DMA
@VDDA
POWER
SPI1
APB 1 : Fmax =24 / 36 MHz
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
Flash obl
Interfac e
TRACECLK
TRACED[0:3]
as AS
BusM atrix
Figure 1.
TIM2
4 Chann els
TIM3
4 Chann els
TIM4
4 Channels
USART2
USART3
2x(8x16bit)SPI2
RX,TX, CTS, RTS,
CK, SmartCard as AF
RX,TX, CTS, RTS,
CK, SmartCard as AF
MOSI,MISO,SCK,NSS
as AF
I2C1
SCL,SDA,SMBA L
as AF
I2C2
SCL,SDA
as AF
USART1
@VDDA
16AF
VREF+
12bit ADC1 IF
WWDG
VREFTemp sen so r
ai14385B
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
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STM32F101x8, STM32F101xB
Figure 2.
Description
Clock tree
8 MHz
HSI RC
HSI
/2
36 MHz max
PLLSRC
/8
SW
PLLMUL
HSI
..., x16
x2, x3, x4
PLL
SYSCLK
PLLCLK
AHB
Prescaler
36 MHz
/1, 2..512
max
Clock
Enable (3 bits)
APB1
Prescaler
/1, 2, 4, 8, 16
HCLK
to AHB bus, core,
memory and DMA
to Cortex System timer
FCLK Cortex
free running clock
36 MHz max
PCLK1
to APB1
peripherals
Peripheral Clock
HSE
Enable (13 bits)
to TIM2, 3
TIM2,3, 4
and 4
If (APB1 prescaler =1) x1
TIMXCLK
else
x2 Peripheral Clock
CSS
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
OSC_OUT
OSC_IN
4-16 MHz
36 MHz max
HSE OSC
/2
ADC
Prescaler
/2, 4, 6, 8
/128
OSC32_IN
OSC32_OUT
Peripheral Clock
Enable (11 bits)
PCLK2
to APB2
peripherals
LSE OSC
32.768 kHz
to ADC
ADCCLK
to RTC
LSE
RTCCLK
RTCSEL[1:0]
LSI RC
40 kHz
to Independent Watchdog (IWDG)
LSI
IWDGCLK
Main
Clock Output
/2
MCO
PLLCLK
HSI
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
HSE
SYSCLK
MCO
ai15104
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
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Description
2.2
STM32F101x8, STM32F101xB
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F101x8/B devices, they are
specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities and a timer less. Highdensity devices have higher Flash memory and RAM capacities, and additional peripherals
like FSMC and DAC, while remaining fully compatible with the other members of the
STM32F101xx family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the
user to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F101xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3.
STM32F101xx family
Memory size
Low-density devices
Pinout
16 KB
Flash
32 KB
Flash(1)
Medium-density devices
64 KB
Flash
128 KB
Flash
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
144
100
64
48
36
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C
1 × ADC
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
1 × ADC
High-density devices
256 KB
Flash
384 KB
Flash
512 KB
Flash
32 KB
RAM
48 KB
RAM
48 KB
RAM
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Cs, 1 × ADC,
2 × DACs, FSMC (100 and 144 pins)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.
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STM32F101x8, STM32F101xB
Description
2.3
Overview
2.3.1
ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx medium-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.
2.3.2
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
2.3.3
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.3.4
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5
Nested vectored interrupt controller (NVIC)
The STM32F101xx medium-density access line embeds a nested vectored interrupt
controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
●
Closely coupled NVIC gives low latency interrupt processing
●
Interrupt entry vector table address passed directly to the core
●
Closely coupled NVIC core interface
●
Allows early processing of interrupts
●
Processing of late arriving higher priority interrupts
●
Support for tail-chaining
●
Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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Description
2.3.6
STM32F101x8, STM32F101xB
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
●
Boot from User Flash
●
Boot from System Memory
●
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9
Power supply schemes
●
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
●
VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
●
VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
2.3.10
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
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STM32F101x8, STM32F101xB
Description
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
2.3.11
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
MR is used in the nominal regulation mode (Run)
●
LPR is used in the Stop mode
●
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12
Low-power modes
The STM32F101xx medium-density access line supports three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.13
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
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Description
STM32F101x8, STM32F101xB
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.
2.3.14
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.3.16
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.3.17
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
2.3.18
●
A 24-bit down counter
●
Autoreload capability
●
Maskable system interrupt generation when the counter reaches 0.
●
Programmable clock source
General-purpose timers (TIMx)
There are three synchronizable general-purpose timers embedded in the STM32F101xx
medium-density access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
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STM32F101x8, STM32F101xB
Description
capture, output compare, PWM or one pulse mode output. This gives up to 12 input
captures / output compares / PWMs on the largest packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs. They all have independent DMA request
generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
2.3.19
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.20
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.3.21
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
2.3.22
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.23
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
Doc ID 13586 Rev 13
19/85
Description
STM32F101x8, STM32F101xB
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.3.24
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.25
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
20/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Pinouts and pin description
STM32F101xx medium-density access line LQFP100 pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 3.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREFVREF+
VDDA
PA0-WKUP
PA1
PA2
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
3
Pinouts and pin description
ai14386b
Doc ID 13586 Rev 13
21/85
Pinouts and pin description
STM32F101xx medium-density access line LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 4.
STM32F101x8, STM32F101xB
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14387b
STM32F101xx medium-density access line LQFP48 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 5.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
LQFP48
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
22/85
Doc ID 13586 Rev 13
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
ai14378d
STM32F101x8, STM32F101xB
STM32F101xx medium-density access line VFQPFN48 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 6.
Pinouts and pin description
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
3
34
4
33
32
5
6
31
VFQFPN48
7
30
8
29
9
28
10
27
11
26
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
ai18300
PB4
PB3
PA15
PA14
31
30
29
28
27
VDD_2
OSC_IN/PD0
2
26
VSS_2
OSC_OUT/PD1
3
25
PA13
NRST
4
24
PA12
VSSA
5
23
PA11
VDDA
6
22
PA10
PA0-WKUP
7
21
PA9
PA1
8
20
PA8
PA2
9
10
11
12
13
14
15
PB0
PB5
32
PA7
PB6
33
PA6
PB7
34
1
PA5
35
VDD_3
PA4
36
BOOT0
VSS_3
STM32F101xx medium-density access line VFQPFN36 pinout
PA3
17
PB2
16
19
18
VDD_1
VSS_1
QFN36
PB1
Figure 7.
ai14654
Doc ID 13586 Rev 13
23/85
Pinouts and pin description
Table 4.
STM32F101x8, STM32F101xB
Medium-density STM32F101xx pin definitions
VFQFPN36
Type(1)
I / O level(2)
Main
function(3)
(after reset)
-
-
1
-
PE2
I/O
FT
PE2
TRACECLK
-
-
2
-
PE3
I/O
FT
PE3
TRACED0
-
-
3
-
PE4
I/O
FT
PE4
TRACED1
-
-
4
-
PE5
I/O
FT
PE5
TRACED2
-
-
5
-
PE6
I/O
FT
PE6
TRACED3
1
1
6
-
VBAT
S
VBAT
2
2
7
-
PC13-TAMPERRTC(5)
I/O
PC13(6)
TAMPER-RTC
3
3
8
-
PC14OSC32_IN(5)
I/O
PC14(6)
OSC32_IN
4
4
9
-
PC15OSC32_OUT(5)
I/O
PC15(6)
OSC32_OUT
-
-
10
-
VSS_5
S
VSS_5
-
-
11
-
VDD_5
S
VDD_5
5
5
12
2
OSC_IN
I
OSC_IN
6
6
13
3
OSC_OUT
O
OSC_OUT
7
7
14
4
NRST
I/O
NRST
-
8
15
-
PC0
I/O
PC0
ADC_IN10
-
9
16
-
PC1
I/O
PC1
ADC_IN11
-
10
17
-
PC2
I/O
PC2
ADC_IN12
-
11
18
-
PC3
I/O
PC3
ADC_IN13
8
12
19
5
VSSA
S
VSSA
-
-
20
-
VREF-
S
VREF-
-
-
21
-
VREF+
S
VREF+
9
13
22
6
VDDA
S
VDDA
10
14
23
7
PA0-WKUP
I/O
PA0
WKUP/USART2_CTS(8)/
ADC_IN0/
TIM2_CH1_ETR(8)
11
15
24
8
PA1
I/O
PA1
USART2_RTS(8)/
ADC_IN1/TIM2_CH2(8)
12
16
25
9
PA2
I/O
PA2
USART2_TX(8)/
ADC_IN2/TIM2_CH3(8)
13
17
26
10
PA3
I/O
PA3
USART2_RX(8)/
ADC_IN3/TIM2_CH4(8)
-
18
27
-
VSS_4
S
VSS_4
LQFP48/
VFQFPN48
LQFP100
Alternate functions(3)(4)
LQFP64
Pins
24/85
Pin name
Doc ID 13586 Rev 13
Default
Remap
STM32F101x8, STM32F101xB
Medium-density STM32F101xx pin definitions (continued)
VFQFPN36
Main
function(3)
(after reset)
LQFP100
Type(1)
Alternate functions(3)(4)
LQFP64
LQFP48/
VFQFPN48
Pins
I / O level(2)
Table 4.
Pinouts and pin description
-
19
28
-
VDD_4
S
VDD_4
14
20
29
11
PA4
I/O
PA4
SPI1_NSS(8)/ADC_IN4
USART2_CK(8)/
15
21
30
12
PA5
I/O
PA5
SPI1_SCK(8)/ADC_IN5
16
22
31
13
PA6
I/O
PA6
SPI1_MISO(8)/ADC_IN6
TIM3_CH1(8)
17
23
32
14
PA7
I/O
PA7
SPI1_MOSI(8)/ADC_IN7
TIM3_CH2(8)
-
24
33
PC4
I/O
PC4
ADC_IN14
-
25
34
PC5
I/O
PC5
ADC_IN15
18
26
35
15
PB0
I/O
PB0
ADC_IN8/TIM3_CH3(8)
19
27
36
16
PB1
I/O
PB1
ADC_IN9/TIM3_CH4(8)
20
28
37
17
PB2
I/O
FT
PB2/BOOT1
-
-
38
-
PE7
I/O
FT
PE7
-
-
39
-
PE8
I/O
FT
PE8
-
-
40
-
PE9
I/O
FT
PE9
-
-
41
-
PE10
I/O
FT
PE10
-
-
42
-
PE11
I/O
FT
PE11
-
-
43
-
PE12
I/O
FT
PE12
-
-
44
-
PE13
I/O
FT
PE13
-
-
45
-
PE14
I/O
FT
PE14
-
-
46
-
PE15
I/O
FT
PE15
21
29
47
-
PB10
I/O
FT
PB10
I2C2_SCL/
USART3_TX (8)
TIM2_CH3
22
30
48
-
PB11
I/O
FT
PB11
I2C2_SDA/
USART3_RX (8)
TIM2_CH4
23
31
49
18
VSS_1
S
VSS_1
24
32
50
19
VDD_1
S
VDD_1
25
33
51
-
PB12
I/O
FT
PB12
SPI2_NSS / I2C2_SMBA /
USART3_CK (8)
26
34
52
-
PB13
I/O
FT
PB13
SPI2_SCK/
USART3_CTS(8)
27
35
53
-
PB14
I/O
FT
PB14
SPI2_MISO/
USART3_RTS(8)
28
36
54
-
PB15
I/O
FT
PB15
SPI2_MOSI
Pin name
Doc ID 13586 Rev 13
Default
Remap
25/85
Pinouts and pin description
Table 4.
STM32F101x8, STM32F101xB
Medium-density STM32F101xx pin definitions (continued)
VFQFPN36
Type(1)
I / O level(2)
Main
function(3)
(after reset)
-
-
55
-
PD8
I/O
FT
PD8
USART3_TX
-
-
56
-
PD9
I/O
FT
PD9
USART3_RX
-
-
57
-
PD10
I/O
FT
PD10
USART3_CK
-
-
58
-
PD11
I/O
FT
PD11
USART3_CTS
-
-
59
-
PD12
I/O
FT
PD12
TIM4_CH1 /
USART3_RTS
-
-
60
-
PD13
I/O
FT
PD13
TIM4_CH2
-
-
61
-
PD14
I/O
FT
PD14
TIM4_CH3
-
-
62
-
PD15
I/O
FT
PD15
TIM4_CH4
-
37
63
-
PC6
I/O
FT
PC6
TIM3_CH1
38
64
-
PC7
I/O
FT
PC7
TIM3_CH2
39
65
-
PC8
I/O
FT
PC8
TIM3_CH3
-
40
66
-
PC9
I/O
FT
PC9
TIM3_CH4
29
41
67
20
PA8
I/O
FT
PA8
USART1_CK/MCO
30
42
68
21
PA9
I/O
FT
PA9
USART1_TX(8)
31
43
69
22
PA10
I/O
FT
PA10
USART1_RX(8)
32
44
70
23
PA11
I/O
FT
PA11
USART1_CTS
33
45
71
24
PA12
I/O
FT
PA12
USART1_RTS
34
46
72
25
PA13
I/O
FT
JTMS-SWDIO
-
-
73
-
35
47
74
26
VSS_2
S
VSS_2
36
48
75
27
VDD_2
S
VDD_2
37
49
76
28
PA14
I/O
FT
JTCK/SWCLK
PA14
38
50
77
29
PA15
I/O
FT
JTDI
TIM2_CH1_ETR/
PA15/ SPI1_NSS
-
51
78
PC10
I/O
FT
PC10
USART3_TX
-
52
79
PC11
I/O
FT
PC11
USART3_RX
-
53
80
PC12
I/O
FT
PC12
USART3_CK
LQFP48/
VFQFPN48
LQFP100
Alternate functions(3)(4)
LQFP64
Pins
Pin name
Default
Remap
PA13
Not connected
5
5
81
2
PD0
I/O
FT
OSC_IN(7)
6
6
82
3
PD1
I/O
FT
OSC_OUT(7)
54
83
-
PD2
I/O
FT
PD2
-
-
84
-
PD3
I/O
FT
PD3
USART2_CTS
-
-
85
-
PD4
I/O
FT
PD4
USART2_RTS
26/85
Doc ID 13586 Rev 13
TIM3_ETR
STM32F101x8, STM32F101xB
Table 4.
Pinouts and pin description
Medium-density STM32F101xx pin definitions (continued)
VFQFPN36
Type(1)
I / O level(2)
Main
function(3)
(after reset)
-
-
86
-
PD5
I/O
FT
PD5
USART2_TX
-
-
87
-
PD6
I/O
FT
PD6
USART2_RX
-
-
88
-
PD7
I/O
FT
PD7
USART2_CK
39
55
89
30
PB3
I/O
FT
JTDO
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
40
56
90
31
PB4
I/O
FT
JNTRST
PB4 / TIM3_CH1
SPI1_MISO
41
57
91
32
PB5
I/O
42
58
92
33
PB6
I/O
43
59
93
34
PB7
I/O
44
60
94
35
BOOT0
I
45
61
95
-
PB8
I/O
FT
46
62
96
-
PB9
I/O
-
-
97
-
PE0
-
-
98
-
47
63
99
48
64
100
LQFP48/
VFQFPN48
LQFP100
Alternate functions(3)(4)
LQFP64
Pins
Pin name
Default
Remap
PB5
I2C1_SMBAl
TIM3_CH2 /
SPI1_MOSI
FT
PB6
I2C1_SCL(8)/
TIM4_CH1 (8)
USART1_TX
FT
PB7
I2C1_SDA(8)/
TIM4_CH2 (8)
USART1_RX
PB8
TIM4_CH3 (8)
I2C1_SCL
FT
PB9
TIM4_CH4 (8)
I2C1_SDA
I/O
FT
PE0
TIM4_ETR
PE1
I/O
FT
PE1
36
VSS_3
S
VSS_3
1
VDD_3
S
VDD_3
BOOT0
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
Doc ID 13586 Rev 13
27/85
Memory mapping
4
STM32F101x8, STM32F101xB
Memory mapping
The memory map is shown in Figure 8.
Figure 8.
Memory map
APB memory space
0xFFFF FFFF
0xE010 0000
0x6000 0000
0x4002 3400
0x4002 3000
0xFFFF FFFF
0xE010 0000
0xE000 0000
Cortex-M3 internal
peripherals
6
reserved
reserved
4K
CRC
1K
reserved
3K
0x4002 2000
Flash interface
1K
0x4002 1400
reserved
3K
0x4002 1000
RCC
1K
0x4002 0400
reserved
3K
0x4002 0000
DMA
1K
reserved
1K
USART1
1K
reserved
1K
0x4002 2400
7
reserved
0x4001 3C00
0x4001 3800
0xC000 0000
0x4001 3400
SPI1
1K
reserved
1K
reserved
1K
ADC1
1K
reserved
2K
0x4001 1800
Port E
1K
0x4001 1400
Port D
1K
0x4001 1000
Port C
1K
0x4001 0C00
Port B
1K
0x4001 0800
Port A
1K
0x4001 0400
EXTI
1K
0x4001 0000
AFIO
1K
reserved
35K
0x4001 3000
0x4001 2C00
5
0x4001 2800
0x4001 2400
0xA000 0000
0x4001 1C00
4
0x1FFF FFFF
reserved
0x1FFF F80F
0x8000 0000
Option Bytes
0x1FFF F800
3
System memory
0x1FFF F000
0x6000 0000
0x4000 7400
0x4000 7000
2
0x4000 0000
0x4000 6C00
reserved
Peripherals
0x4000 6800
0x4000 6400
0x4000 6000
0x2000 0000
SRAM
1K
BKP
1K
reserved
1K
reserved
1K
reserved
1K
reserved
1K
0x4000 5800
I2C2
1K
0x4000 5400
I2C1
1K
reserved
2K
0x4000 4800
USART3
1K
0x4000 4400
USART2
1K
reserved
2K
0x4000 5C00
1
PWR
0x0801 FFFF
0x4000 4C00
0
Flash memory
0x0800 0000
0x0000 0000
Aliased to Flash or
system memory
depending on
0x0000 0000 BOOT pins
Reserved
0x4000 3C00
SPI2
1K
0x4000 3400
reserved
1K
0x4000 3000
IWDG
1K
0x4000 2C00
WWDG
1K
0x4000 2800
RTC
1K
reserved
7K
0x4000 0800
TIM4
1K
0x4000 0400
TIM3
1K
0x4000 0000
TIM2
1K
0x4000 3800
0x4000 0C00
ai14379d
28/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V  VDD  3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Doc ID 13586 Rev 13
29/85
Electrical characteristics
Figure 9.
STM32F101x8, STM32F101xB
Pin loading conditions
Figure 10. Pin input voltage
STM32F10xxx pin
STM32F10xxx pin
C = 50 pF
VIN
ai14124b
ai14123b
5.1.6
Power supply scheme
Figure 11. Power supply scheme
VBAT
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Backup registers)
OUT
GP I/Os
IN
Level shifter
Po wer swi tch
1.8-3.6V
IO
Logic
Kernel logic
(CPU,
Digital
& Memories)
VDD
VDD
1/2/3/4/5
5 × 100 nF
+ 1 × 4.7 µF
VDD
1/2/3/4/5
VDDA
VREF
10 nF
+ 1 µF
Regulator
VSS
10 nF
+ 1 µF
VREF+
VREF-
ADC
Analog:
RCs, PLL,
...
VSSA
ai14125d
Caution:
30/85
In Figure 11, the 4.7 µF capacitor must be connected to VDD3.
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
5.1.7
Electrical characteristics
Current consumption measurement
Figure 12. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 5.
Symbol
VDD VSS
VIN
|VDDx|
|VSSX VSS|
VESD(HBM)
Voltage characteristics
Ratings
Min
Max
External main supply voltage (including
VDDA and VDD)(1)
–0.3
4.0
Input voltage on five volt tolerant pin(2)
VSS  0.3
+5.5
Input voltage on any other pin(2)
VSS 0.3
VDD+0.3
Variations between different VDD power pins
50
Variations between all the different ground
pins
50
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 5.3.11: Absolute
maximum ratings (electrical
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN<VSS.
Doc ID 13586 Rev 13
31/85
Electrical characteristics
Table 6.
STM32F101x8, STM32F101xB
Current characteristics
Symbol
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
IVDD
Total current out of VSS ground lines (sink)
IVSS
150
(1)
150
Output current sunk by any I/O and control pin
IIO
IINJ(PIN) (2)(3)
IINJ(PIN)
(2)
25
Output current source by any I/Os and control pin
 25
Injected current on NRST pin
±5
Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins
±5
Injected current on any other pin(4)
±5
Total injected current (sum of all I/O and control
Unit
pins)(4)
mA
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 7.
Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 8.
Unit
–65 to +150
°C
150
°C
General operating conditions
Symbol
Parameter
Min
Max
fHCLK
Internal AHB clock frequency
0
36
fPCLK1
Internal APB1 clock frequency
0
36
fPCLK2
Internal APB2 clock frequency
0
36
Standard operating voltage
2
3.6
2
3.6
VDD
VDDA(1)
VBAT
32/85
Value
Analog operating voltage
(ADC not used)
Analog operating voltage
(ADC used)
Conditions
Must be the same potential
as VDD(2)
Backup operating voltage
Doc ID 13586 Rev 13
Unit
MHz
V
V
2.4
3.6
1.8
3.6
V
STM32F101x8, STM32F101xB
Table 8.
Symbol
PD
TA
TJ
Electrical characteristics
General operating conditions (continued)
Parameter
Power dissipation at TA =
85 °C(3)
Ambient temperature
Conditions
Min
Max
LQFP100
434
LQFP64
444
LQFP48
363
VFQFPN36
1110
Unit
mW
Maximum power dissipation
–40
85
°C
Low power dissipation(4)
–40
105
°C
–40
105
°C
Junction temperature range
1. When the ADC is used, refer to Table 41: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 76).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 76).
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 9.
Symbol
tVDD
5.3.3
Operating conditions at power-up / power-down
Parameter
Conditions
Min
Max
VDD rise time rate
0

VDD fall time rate
20

Unit
µs/V
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Doc ID 13586 Rev 13
33/85
Electrical characteristics
.
Table 10.
Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Programmable voltage
detector level selection
VPVD
VPVDhyst
STM32F101x8, STM32F101xB
(2)
VPOR/PDR
VPDRhyst
(2)
Min
Typ
Max
Unit
PLS[2:0]=000 (rising edge)
2.1
2.18
2.26
V
PLS[2:0]=000 (falling edge)
2
2.08
2.16
V
PLS[2:0]=001 (rising edge)
2.19
2.28
2.37
V
PLS[2:0]=001 (falling edge)
2.09
2.18
2.27
V
PLS[2:0]=010 (rising edge)
2.28
2.38
2.48
V
PLS[2:0]=010 (falling edge)
2.18
2.28
2.38
V
PLS[2:0]=011 (rising edge)
2.38
2.48
2.58
V
PLS[2:0]=011 (falling edge)
2.28
2.38
2.48
V
PLS[2:0]=100 (rising edge)
2.47
2.58
2.69
V
PLS[2:0]=100 (falling edge)
2.37
2.48
2.59
V
PLS[2:0]=101 (rising edge)
2.57
2.68
2.79
V
PLS[2:0]=101 (falling edge)
2.47
2.58
2.69
V
PLS[2:0]=110 (rising edge)
2.66
2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56
2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76
2.88
3
V
PLS[2:0]=111 (falling edge)
2.66
2.78
2.9
V
PVD hysteresis
100
Power on/power down
reset threshold
Falling edge
1.8(1)
1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
PDR hysteresis
40
tRSTTEMPO(2) Reset temporization
1.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
34/85
mV
Doc ID 13586 Rev 13
2.5
mV
4.5
ms
STM32F101x8, STM32F101xB
5.3.4
Electrical characteristics
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 11.
Symbol
VREFINT
Embedded internal reference voltage
Parameter
Internal reference voltage
TS_vrefint(1)
ADC sampling time when reading
the internal reference voltage
VRERINT(2)
Internal reference voltage spread
over the temperature range
TCoeff(2)
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +85 °C
1.16
1.20
1.24
V
5.1
17.1(2)
µs
10
mV
100
ppm/
°C
VDD = 3 V ±10 mV
Temperature coefficient
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
●
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Doc ID 13586 Rev 13
35/85
Electrical characteristics
Table 12.
STM32F101x8, STM32F101xB
Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
External clock (2), all
peripherals enabled
IDD
Supply current
in Run mode
36 MHz
28.6
24 MHz
19.9
16 MHz
14.7
8 MHz
8.6
36 MHz
19.8
24 MHz
13.9
16 MHz
10.7
8 MHz
6.8
mA
External clock (4), all
peripherals Disabled
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13.
Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
External clock (2), all
peripherals enabled
IDD
Supply current in
Run mode
External clock(2) all
peripherals disabled
36 MHz
24
24 MHz
17.5
16 MHz
12.5
8 MHz
7.5
36 MHz
16
24 MHz
11.5
16 MHz
8.5
8 MHz
5.5
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
36/85
Doc ID 13586 Rev 13
mA
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
25
Consumption (mA)
20
15
36MHz
16MHz
8MHz
10
5
0
-40
0
25
70
85
Temperature (°C)
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
16
14
Consumption (mA)
12
10
36MHz
16MHz
8MHz
8
6
4
2
0
-40
0
25
70
85
Temperature (°C)
Doc ID 13586 Rev 13
37/85
Electrical characteristics
Table 14.
STM32F101x8, STM32F101xB
Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
External clock(2) all
peripherals enabled
IDD
Supply current in
Sleep mode
36 MHz
15.5
24 MHz
11.5
16 MHz
8.5
8 MHz
5.5
36 MHz
5
24 MHz
4.5
16 MHz
4
8 MHz
3
mA
External clock(2), all
peripherals disabled
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15.
Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
Parameter
Supply current
in Stop mode
IDD
Supply current
in Standby
mode
IDD_VBAT
Conditions
VDD/VBAT VDD/ VBAT VDD/VBAT TA =
= 2.0 V
= 2.4 V
= 3.3 V 85 °C(2)
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)
-
23.5
24
200
Regulator in Low-Power mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)
-
13.5
14
180
Low-speed internal RC oscillator and
independent watchdog ON
-
2.6
3.4
-
Low-speed internal RC oscillator ON,
independent watchdog OFF
-
2.4
3.2
-
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
-
1.7
2
4
0.9
1.1
1.4
1.9
Backup domain
Low-speed oscillator and RTC ON
supply current
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not rested in production.
38/85
Max
Doc ID 13586 Rev 13
Unit
µA
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 15. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values
Consumption ( µA )
2.5
2
2V
1.5
2.4 V
1
3V
0.5
3.6 V
0
–40 °C
25 °C
70 °C
85 °C
105 °C
Temperature (°C)
ai17351
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V
140
Consumption (µA)
120
100
80
3.3 V
3.6 V
60
40
20
0
-45
25
70
90
Temperature (°C)
Doc ID 13586 Rev 13
39/85
Electrical characteristics
STM32F101x8, STM32F101xB
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V
100
90
Consumption (µA)
80
70
60
3.3 V
50
3.6 V
40
30
20
10
0
–45 °C
25 °C
85 °C
Temperature (°C)
Figure 18. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V
3
Consumption (µA)
2.5
2
3.3 V
1.5
3.6 V
1
0.5
0
-45
25
70
Temperature (°C)
40/85
Doc ID 13586 Rev 13
90
STM32F101x8, STM32F101xB
Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
●
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
●
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Table 16 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 16.
Symbol
Typical current consumption in Run mode, code with data processing
running from Flash
Parameter
Conditions
External
clock(3)
IDD
Supply
current in
Run mode
fHCLK
Typ(1)
Typ(1)
All peripherals
enabled(2)
All peripherals
disabled
36 MHz
19
14.8
24 MHz
12.9
10.1
16 MHz
9.3
7.4
8 MHz
5.5
4.6
4 MHz
3.3
2.8
2 MHz
2.2
1.9
1 MHz
1.6
1.45
500 kHz
1.3
1.25
125 kHz
1.08
1.06
36 MHz
18.3
14.1
24 MHz
12.2
9.5
16 MHz
8.5
6.8
8 MHz
4.9
4
4 MHz
2.7
2.2
2 MHz
1.6
1.4
1 MHz
1.02
0.9
500 kHz
0.73
0.67
125 kHz
0.5
0.48
Unit
mA
Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Doc ID 13586 Rev 13
41/85
Electrical characteristics
Table 17.
STM32F101x8, STM32F101xB
Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol
Parameter
Conditions
(3)
External clock
IDD
Supply
current in
Sleep mode
fHCLK
Typ(1)
All peripherals All peripherals
enabled(2)
disabled
36 MHz
7.6
3.1
24 MHz
5.3
2.3
16 MHz
3.8
1.8
8 MHz
2.1
1.2
4 MHz
1.6
1.1
2 MHz
1.3
1
1 MHz
1.11
0.98
500 kHz
1.04
0.96
125 kHz
0.98
0.95
36 MHz
7
2.5
24 MHz
4.8
1.8
16 MHz
3.2
1.2
8 MHz
1.6
0.6
4 MHz
1
0.5
2 MHz
0.72
0.47
1 MHz
0.56
0.44
500 kHz
0.49
0.42
125 kHz
0.43
0.41
mA
Running on High
Speed Internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
42/85
Unit
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
●
all I/O pins are in input mode with a static value at VDD or VSS (no load)
●
all peripherals are disabled unless otherwise mentioned
●
the given value is calculated by measuring the current consumption
●
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 5.
Table 18.
Peripheral current consumption
Peripheral
Typical consumption at 25 °C(1)
TIM2
0.6
TIM3
0.6
TIM4
0.6
SPI2
0.08
USART2
0.21
USART3
0.21
I2C1
0.18
I2C2
0.18
GPIO A
0.21
GPIO B
0.21
GPIO C
0.21
GPIO D
0.21
GPIO E
0.21
Unit
APB1
mA
APB2
ADC1
1.
(2)
1.4
SPI1
0.24
USART1
0.35
fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
Doc ID 13586 Rev 13
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Electrical characteristics
Table 19.
STM32F101x8, STM32F101xB
High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
8
25
MHz
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high level voltage
0.7VDD
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
tr(HSE)
tf(HSE)
Cin(HSE)
16
ns
(1)
OSC_IN rise or fall time
20
OSC_IN input capacitance(1)
5
DuCy(HSE) Duty cycle
IL
V
pF
45
OSC_IN Input leakage current
VSS  VIN  VDD
55
%
±1
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
Table 20.
Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
32.768
1000
kHz
fLSE_ext
User external clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
0.7VDD
VDD
VLSEL
OSC32_IN input pin low level
voltage
VSS
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
V
Cin(LSE)
ns
OSC32_IN input capacitance(1)
DuCy(LSE) Duty cycle
IL
5
30
OSC32_IN Input leakage current VSS  VIN  VDD
1. Guaranteed by design, not tested in production.
44/85
50
Doc ID 13586 Rev 13
pF
70
%
±1
µA
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 19. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
tW(HSE)
t
THSE
External
clock source
fHSE_ext
OSC _IN
IL
STM32F10xxx
ai14127b
Figure 20. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
External
clock source
fLSE_ext
STM32F10xxx
ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 21. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Doc ID 13586 Rev 13
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Electrical characteristics
Table 21.
STM32F101x8, STM32F101xB
HSE 4-16 MHz oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Min
Typ
Max
Unit
4
8
16
MHz
Oscillator frequency
RF
Feedback resistor
200
k
C
Recommended load capacitance
versus equivalent serial
RS = 30
resistance of the crystal (RS)(3)
30
pF
i2
HSE driving current
VDD = 3.3 V, VIN = VSS
with 30 pF load
Oscillator transconductance
Startup
Startup time
VDD is stabilized
gm
tSU(HSE)
(4)
1
25
mA
mA/V
2
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
Bias
controlled
gain
OSC_OU T
STM32F10xxx
ai14128b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
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STM32F101x8, STM32F101xB
Electrical characteristics
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 22.
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 K
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
1.4
µA
gm
Oscillator transconductance
tSU(LSE)(4)
5
5
Startup time
VDD is stabilized
M
µA/V
3
s
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Note:
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL  7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 KH z
resonator
CL2
RF
Bias
controlled
gain
OSC32_OU T
STM32F10xxx
ai14129b
Doc ID 13586 Rev 13
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Electrical characteristics
5.3.7
STM32F101x8, STM32F101xB
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
High-speed internal (HSI) RC oscillator
Table 23.
Symbol
fHSI
HSI oscillator characteristics(1)
Parameter
Conditions
Min
Frequency
Typ
Unit
8
User-trimmed with the RCC_CR
register(2)
ACCHSI
Max
Accuracy of the HSI
oscillator
Factorycalibrated(4)
tsu(HSI)(4)
HSI oscillator
startup time
IDD(HSI)(4)
HSI oscillator power
consumption
MHz
1(3)
%
TA = –40 to 105 °C
–2
2.5
%
TA = –10 to 85 °C
–1.5
2.2
%
TA = 0 to 70 °C
–1.3
2
%
TA = 25 °C
–1.1
1.8
%
1
2
µs
100
µA
80
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 24.
LSI oscillator characteristics (1)
Symbol
fLSI(2)
tsu(LSI)
(3)
IDD(LSI)(3)
Parameter
Frequency
Min
Typ
Max
Unit
30
40
60
kHz
85
µs
1.2
µA
LSI oscillator startup time
LSI oscillator power consumption
0.65
1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
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●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 8.
Table 25.
Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP(1)
tWUSTOP(1)
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low-power mode)
5.4
Wakeup from Standby mode
50
µs
tWUSTDBY(1)
µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 26.
PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
25
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
36
MHz
tLOCK
PLL lock time
200
µs
Jitter
Cycle-to-cycle jitter
300
ps
fPLL_IN
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.
Table 27.
Flash memory characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
tprog
16-bit programming time
TA–40 to +85 °C
40
52.5
70
µs
tERASE
Page (1 KB) erase time
TA –40 to +85 °C
20
40
ms
Mass erase time
TA –40 to +85 °C
20
40
ms
tME
Doc ID 13586 Rev 13
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Electrical characteristics
Table 27.
Symbol
IDD
Vprog
STM32F101x8, STM32F101xB
Flash memory characteristics (continued)
Max(1)
Unit
Read mode
fHCLK = 36 MHz with 1 wait
state, VDD = 3.3 V
20
mA
Write / Erase modes
fHCLK = 36 MHz, VDD = 3.3 V
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
3.6
V
Parameter
Min(1)
Conditions
Supply current
Programming voltage
Typ
2
1. Guaranteed by design, not tested in production.
Table 28.
Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 °C to 85 °C
Min(1)
TA = 85 °C, 1 kcycle(2)
10
30
TA = 55 °C, 10 kcycle(2)
20
Unit
Typ
Max
kcycles
Years
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 29. They are based on the EMS levels and classes
defined in application note AN1709.
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Table 29.
Electrical characteristics
EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD 3.3 V, TA +25 °C,
fHCLK 36 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
VDD3.3 V, TA +25 °C,
applied through 100 pF on VDD and VSS pins fHCLK 36 MHz
to induce a functional disturbance
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC61967-2 standard which specifies the test board and the pin loading.
Table 30.
EMI characteristics
Symbol Parameter
SEMI
Peak level
Conditions
Monitored
frequency band
0.1 MHz to 30 MHz
VDD 3.3 V, TA 25 °C,
30 MHz to 130 MHz
LQFP100 package
compliant with
130 MHz to 1GHz
IEC 61967-2
SAE EMI Level
Doc ID 13586 Rev 13
Max vs. [fHSE/fHCLK]
Unit
8/36 MHz
7
8
dBµV
13
3.5
-
51/85
Electrical characteristics
5.3.11
STM32F101x8, STM32F101xB
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31.
ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA +25 °C
2
conforming to JESD22-A114
2000
VESD(CDM)
Electrostatic discharge
TA +25 °C
II
voltage (charge device model) conforming to JESD22-C101
500
V
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 32.
Symbol
LU
5.3.12
Electrical sensitivities
Parameter
Conditions
Static latch-up class
TA +85 °C conforming to JESD78A
Class
II level A
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
52/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Table 33.
Symbol
VIL
Electrical characteristics
I/O static characteristics
Parameter
Conditions
Ilkg
Max
–0.5
0.28 (VDD–2)+0.8
I/O FT(1) input low level voltage
–0.5
0.32 (VDD–2)+0.75
0.41 (VDD–2)+1.3
VDD+0.5
0.42 (VDD–2)+1
5.5
I/O FT(1) input high level
voltage
IO FT Schmitt trigger voltage
hysteresis(2)
Input leakage current
(4)
Unit
V
Standard IO Schmitt trigger
voltage hysteresis(2)
Vhys
Typ
Standard I/O input low level
voltage
Standard I/O input high level
voltage
VIH
Min
200
mV
5% VDD(3)
mV
VSS  VIN  VDD
Standard I/Os
1
VIN = 5 V
I/O FT
3
µA
RPU
Weak pull-up equivalent
resistor(5)
VIN VSS
30
40
50
k
RPD
Weak pull-down equivalent
resistor(5)
VIN VDD
30
40
50
k
CIO
I/O pin capacitance
5
pF
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
Doc ID 13586 Rev 13
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 23. Standard I/O input characteristics - CMOS port
VIH/VIL (V)
1.3
(V -2)+
V IH=0.41 DD
5V D
V =0.6 D
irement IH
ard requ
S stand
VIHmin
VILmax
CMO
1.71
1.59
1.59
1.3
0.8
0.7
rd re
CMOS standa
Input range
not guaranteed
1.25
–2)+0.8
VIL = 0.28(VDD
=0.35V DD
quirement V IL
2.7
2
1.08
1.08
11
1.96
1.71
3
3.3
VDD (V)
3.6
ai17277b
Figure 24. Standard I/O input characteristics - TTL port
6)(6),6
7)(MIN
44,REQUIREMENTS 6)( 6
6 $$
6 )(
)NPUTRANGE
NOTGUARANTEED
7),MAX
6 ),6 $$
44,REQUIREMENTS 6),6
6$$6
AI
54/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 25. 5 V tolerant I/O input characteristics - CMOS port
6)(6),6
6 $
6 $
IREMENTS )(
REQU
TANDARD
#-/3S
)NPUTRANGE
NOTGUARANTEED
6 ),6 $$
T6 ),6 $$
REQUIRMEN
/3STANDARD
#-
6 )(6 $$
6$$6
6$$
AIB
Figure 26. 5 V tolerant I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENT6 )(6
6 $$
6 )(
7)(MIN
7),MAX
)NPUTRANGE
NOTGUARANTEED
6 ),
6 $$
44,REQUIREMENTS6 ),6
6$$6
AI
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 6).
●
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 6).
Doc ID 13586 Rev 13
55/85
Electrical characteristics
STM32F101x8, STM32F101xB
Output voltage levels
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8. All I/Os are CMOS and TTL compliant.
Table 34.
Output voltage characteristics
Symbol
Parameter
VOL(1)
VOH
(2)
VOL(1)
VOH
(2)
VOL(1)
VOH
(2)
VOL(1)
VOH
(2)
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Conditions
TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
CMOS port
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA(3)
2.7 V < VDD < 3.6 V
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
IIO = +6 mA(3)
2 V < VDD < 2.7 V
Min
Max
Unit
0.4
V
VDD–0.4
0.4
V
2.4
1.3
V
VDD–1.3
0.4
V
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. Based on characterization data, not tested in production.
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STM32F101x8, STM32F101xB
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 35, respectively.
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8.
Table 35.
MODEx
[1:0] bit
value(1)
I/O AC characteristics(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
10
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
-
tEXTIpw
Frequency(2)
Output high to low level fall
time
Output low to high level rise
time
Conditions
CL = 50 pF, VDD = 2 V to 3.6 V
Max
Unit
2
MHz
125(3)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
(3)
125
CL= 50 pF, VDD = 2 V to 3.6 V
10
MHz
25(3)
CL= 50 pF, VDD = 2 V to 3.6 V
ns
25(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
20
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of external
signals detected by the
EXTI controller
10
ns
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 27.
3. Guaranteed by design, not tested in production.
Doc ID 13586 Rev 13
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 27. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 33).
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8.
Table 36.
NRST pin characteristics
Symbol
VIL(NRST)(1)
VIH(NRST)
(1)
Vhys(NRST)
RPU
Parameter
Conditions
Min
Typ
Max
NRST Input low level voltage
–0.5
0.8
NRST Input high level voltage
2
VDD+0.5
Unit
V
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor(2)
VF(NRST)(1)
NRST Input filtered pulse
VNF(NRST)(1)
NRST Input not filtered pulse
200
VIN VSS
30
40
mV
50
k
100
ns
300
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
Figure 28. Recommended NRST pin protection
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal reset
Filter
0.1 µF
STM32F10x
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
5.3.14
Electrical characteristics
TIM timer characteristics
The parameters given in Table 37 are guaranteed by design.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 37.
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
TIMx(1) characteristics
Parameter
Conditions
Min
Max
1
tTIMxCLK
27.8
ns
Timer resolution time
fTIMxCLK = 36 MHz
Timer external clock
frequency on CH1 to CH4
fTIMxCLK = 36 MHz
0
fTIMxCLK/2
MHz
0
18
MHz
16
bit
65536
tTIMxCLK
1820
µs
65536 × 65536
tTIMxCLK
119.2
s
Timer resolution
16-bit counter clock period
when internal clock is
selected
tMAX_COUNT Maximum possible count
Unit
1
fTIMxCLK = 36 MHz 0.0278
fTIMxCLK = 36 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Table 8.
The STM32F101xx medium-density access line I2C interface meets the requirements of the
standard I2C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Doc ID 13586 Rev 13
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Electrical characteristics
Table 38.
STM32F101x8, STM32F101xB
I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
(3)
0(4)
900(3)
20+0.1Cb
300
µs
th(SDA)
SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
Start condition hold time
4.0
0.6
tsu(STA)
Repeated Start condition setup
time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
µs
tw(STO:STA)
Stop to Start condition time (bus
free)
4.7
1.3
µs
Cb
Capacitive load for each bus line
0
300
µs
400
400
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than
4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
maximum I2C fast mode clock.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
60/85
ns
Doc ID 13586 Rev 13
pF
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 29. I2C bus AC waveforms and measurement circuit(1)
VDD
4 .7 kΩ
VDD
4 .7 kΩ
100 Ω
100 Ω
I²C bus
STM32F10x
SDA
SCL
Start repeated
Start
Start
tsu(STA)
SDA
tf(SDA)
tr(SDA)
th(STA)
tsu(SDA)
tw(SCLL)
tsu(STO:STA)
Stop
th(SDA)
SCL
tw(SCLH)
tr(SCL)
tsu(STO)
tf(SCL)
ai14133d
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39.
SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 k
400
0x801E
300
0x8028
200
0x803C
100
0x00B4
50
0x0168
20
0x0384
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
Doc ID 13586 Rev 13
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Electrical characteristics
STM32F101x8, STM32F101xB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
Symbol
fSCK
1/tc(SCK)
SPI characteristics(1)
Parameter
Conditions
Min
Max
Master mode
0
18
Slave mode
0
18
SPI clock frequency
MHz
SPI clock rise and fall
time
Capacitive load: C = 30 pF
tsu(NSS)(2)
NSS setup time
Slave mode
4 tPCLK
th(NSS)(2)
NSS hold time
Slave mode
73
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
SPI1
1
SPI2
5
tr(SCK)
tf(SCK)
tw(SCKH)(2)
tw(SCKL)(2)
8
60
tsu(MI) (2)
Data input setup time
Master mode
tsu(SI)(2)
Data input setup time
Slave mode
th(MI) (2)
Data input hold time
Master mode
th(SI)(2)
Data input hold time
Slave mode
3
Slave mode, fPCLK = 36 MHz,
Data output access time presc = 4
0
55
0
4 tPCLK
ta(SO)(2)(3)
1
SPI1
1
SPI2
5
ns
Slave mode, fPCLK = 24 MHz
(2)(4)
Data output disable time Slave mode
(2)(1)
Data output valid time
Slave mode (after enable edge)
tv(MO)(2)(1)
Data output valid time
Master mode (after enable
edge)
tdis(SO)
tv(SO)
th(SO)(2)
th(MO)(2)
Data output hold time
Unit
10
25
3
Slave mode (after enable edge)
25
Master mode (after enable
edge)
4
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 30. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 31. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Doc ID 13586 Rev 13
63/85
Electrical characteristics
STM32F101x8, STM32F101xB
Figure 32. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
5.3.16
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
Table 41.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input
pin
220(1)
µA
fADC
ADC clock frequency
0.6
14
MHz
fS(2)
Sampling rate
0.05
1
MHz
823
kHz
17
1/fADC
VREF+
V
50
k
fTRIG(2)
VAIN
160(1)
fADC = 14 MHz
External trigger frequency
0 (VSSA or VREFtied to ground)
Conversion voltage range(3)
See Equation 1 and
Table 42 for details
RAIN(2)
External input impedance
RADC(2)
Sampling switch resistance
1
k
CADC(2)
Internal sample and hold
capacitor
8
pF
tCAL(2)
Calibration time
fADC = 14 MHz
tlat(2)
Injection trigger conversion
latency
fADC = 14 MHz
tlatr(2)
Regular trigger conversion
latency
fADC = 14 MHz
tS(2)
Sampling time
fADC = 14 MHz
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
5.9
µs
83
1/fADC
0.214
µs
3(4)
1/fADC
0.143
µs
(4)
2
0.107
17.1
µs
1.5
239.5
1/fADC
1
µs
18
µs
0
fADC = 14 MHz
1/fADC
1
0
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin description for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
Doc ID 13586 Rev 13
65/85
Electrical characteristics
STM32F101x8, STM32F101xB
Equation 1: RAIN max formula:
TS
R AIN  ------------------------------------------------------------- – R ADC
N+2
f ADC  C ADC  ln  2

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 42.
RAIN max for fADC = 14 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (k)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 43.
Symbol
ADC accuracy - limited test conditions(1) (2)
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max(3)
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
±0.8
±1.5
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
3. Based on characterization, not tested in production.
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
ADC accuracy(1) (2) (3)
Table 44.
Symbol
ET
Electrical characteristics
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
Typ
Max(4)
±2
±5
±1.5
±2.5
±1.5
±3
±1
±2
±1.5
±3
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.
Figure 33. ADC accuracy characteristics
V
V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096
4096
EG
4095
4094
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4093
(2)
ET
(3)
7
(1)
6
5
4
EO
EL
3
ED
2
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
Doc ID 13586 Rev 13
ai14395b
67/85
Electrical characteristics
STM32F101x8, STM32F101xB
Figure 34. Typical connection diagram using the ADC
STM32F10xxx
VDD
RAIN(1)
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
AINx
VT
0.6 V
VAIN
Cparasitic
12-bit
converter
CADC(1)
IL±1 µA
ai14139d
1. Refer to Table 41 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 35 or Figure 36,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+
1 µF // 10 nF
V DDA
1 µF // 10 nF
V SSA/V REF-
ai14380b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
68/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 36. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
5.3.17
Temperature sensor characteristics
Table 45.
TS characteristics
Symbol
TL(1)
Avg_Slope(1)
V25(1)
tSTART(2)
TS_temp(3)(2)
Parameter
Min
VSENSE linearity with temperature
Typ
Max
Unit
1
2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25°C
1.34
1.43
1.52
V
10
µs
17.1
µs
Startup time
4
ADC sampling time when reading the
temperature
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
Doc ID 13586 Rev 13
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Package characteristics
STM32F101x8, STM32F101xB
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Package characteristics
Figure 37. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 38. Recommended footprint
outline(1)
(dimensions in mm)(1)(2)(3)
ddd C
Seating
Plane
A2
A
C
0.75
A1
A3
5.80
37
48
D
36
1
Pin no. 1 ID
R = 0.20
e
5.60
37
48
0.20
1
36
5.80
5.60
e
6.20
0.30
E
E2
b
6.20
12
25
13
0.55
24
L
0.50
12
25
7.30
ai15799
24
13
L
b
Bottom View
D2
V0_ME
1. Drawing is not to scale.
2. The back-side pad is not internally connected to the VSS or VDD power pads.
3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should
also be soldered to the PCB. It is recommended to connect it to VSS.
Table 46.
VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.020
0.050
0.0008
0.0020
A2
0.650
1.000
0.0256
0.0394
A3
0.250
A
0.0098
b
0.180
0.230
0.300
0.0071
0.0091
0.0118
D
6.850
7.000
7.150
0.2697
0.2756
0.2815
D2
2.250
4.700
5.250
0.0886
0.1850
0.2067
E
6.850
7.000
7.150
0.2697
0.2756
0.2815
E2
2.250
4.700
5.250
0.0886
0.1850
0.2067
e
0.450
0.500
0.550
0.0177
0.0197
0.0217
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13586 Rev 13
71/85
Package characteristics
STM32F101x8, STM32F101xB
Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package Figure 40. Recommended footprint
outline(1)
(dimensions in mm)(1)(2)(3)
Seating plane
C
ddd
C
A2 A
1.00
4.30
27
A1
A3
19
E2
28
18
b
27
19
0.50
4.10
18
28
4.30
4.10
4.80
4.80
e
D2
D
36
10
9
1
0.75
0.30
36
10
6.30
ai14870b
Pin # 1 ID
R = 0.20
1
9
L
E
ZR_ME
1. Drawing is not to scale.
2. The back-side pad is not internally connected to the VSS or VDD power pads.
3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should
also be soldered to the PCB.
Table 47.
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.020
0.050
0.0008
0.0020
A2
0.650
1.000
0.0256
0.0394
A3
0.250
A
0.0098
b
0.180
0.230
0.300
0.0071
0.0091
0.0118
D
5.875
6.000
6.125
0.2313
0.2362
0.2411
D2
1.750
3.700
4.250
0.0689
0.1457
0.1673
E
5.875
6.000
6.125
0.2313
0.2362
0.2411
E2
1.750
3.700
4.250
0.0689
0.1457
0.1673
e
0.450
0.500
0.550
0.0177
0.0197
0.0217
L
0.350
0.550
0.750
0.0138
0.0217
0.0295
ddd
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
72/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Package characteristics
Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile
quad flat package outline(1)
Figure 42. Recommended footprint(1)(2)
0.25 mm
0.10 inch
GAGE PLANE
75
k
51
D
L
D1
76
50
0.5
L1
D3
51
75
C
0.3
76
50
16.7
14.3
b
E3 E1 E
100
26
1.2
1
100
26
Pin 1
1
identification
25
12.3
25
ccc
C
16.7
e
A1
ai14906
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 48.
LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
D
15.80
D1
13.80
D3
Max
0.063
0.15
0.002
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.2
0.0035
16.00
16.2
0.622
0.6299
0.6378
14.00
14.2
0.5433
0.5512
0.5591
12.00
0.0059
0.0079
0.4724
E
15.80
16.00
16.2
0.622
0.6299
0.6378
E1
13.80
14.00
14.2
0.5433
0.5512
0.5591
E3
12.00
e
L
0.50
0.45
L1
k
ccc
0.4724
0.60
0.0197
0.75
0.0177
1.00
0°
3.5°
0.0236
0.0295
0.0394
7°
0.08
0.0°
3.5°
7.0°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13586 Rev 13
73/85
Package characteristics
STM32F101x8, STM32F101xB
Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile
quad flat package outline(1)
Figure 44. Recommended
footprint(1)(2)
A
A2
48
33
A1
0.3
49
E
b
E1
12.7
32
0.5
10.3
10.3
e
64
17
1.2
1
16
7.8
D1
c
L1
D
12.7
ai14909
L
ai14398b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 49.
LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.0630
0.15
0.0020
0.0059
1.40
1.45
0.0531
0.0551
0.0571
0.22
0.27
0.0067
0.0087
0.0106
0.20
0.0035
0.0079
D
12.00
0.4724
D1
10.00
0.3937
E
12.00
0.4724
E1
10.00
0.3937
e
0.50
0.0197

0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
1.00
0.0394
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
74/85
Typ
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Package characteristics
Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
package outline(1)
Figure 46. Recommended
footprint(1)(2)
Seating plane
C
A A2
A1
c
b
ccc
0.50
1.20
0.25 mm
Gage plane
C
36
D
0.30
25
37
24
D1
k
D3
A1
L
25
36
9.70
0.20
7.30
5.80
L1
7.30
24
37
48
13
12
1
1.20
E3 E1
5.80
E
9.70
ai14911b
48
Pin 1
identification
13
1
12
5B_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 50.
LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
A
Max
Min
Typ
1.600
Max
0.0630
A1
0.050
0.150
0.0020
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
0.200
0.0035
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
5.500
0.0059
0.0079
0.2165
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
e
L
0.500
0.450
L1
k
ccc
0.2165
0.600
0.0197
0.750
0.0177
1.000
0°
3.5°
0.0236
0.0295
0.0394
7°
0.080
0°
3.5°
7°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13586 Rev 13
75/85
Package characteristics
6.2
STM32F101x8, STM32F101xB
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions on page 32.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
●
TA max is the maximum ambient temperature in C,
●
JA is the package junction-to-ambient thermal resistance, in C/W,
●
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
●
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 51.
Package thermal characteristics
Symbol
JA
6.2.1
Parameter
Value
Thermal resistance junction-ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
VFQFPN 48 - 6 x 6 mm / 0.5 mm pitch
16
Thermal resistance junction-ambient
VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch
18
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
76/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 52: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F101xx junction temperature range.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 51 TJmax is calculated as follows:
–
For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the junction temperature range of the STM32F101xx (–40 < TJ < 105 °C).
Figure 47. LQFP64 PD max vs. TA
700
600
PD (mW)
6.2.2
Package characteristics
500
400
Suffix 6
300
200
100
0
65
75
85
95
105
115
TA (°C)
Doc ID 13586 Rev 13
77/85
Ordering information scheme
7
STM32F101x8, STM32F101xB
Ordering information scheme
Table 52.
Ordering information scheme
Example:
STM32 F 101 C
8
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
101 = access line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size(1)
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
T = LQFP
U = VFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Options
xxx = programmed parts
TR = tape and real
1. Although STM32F101x6 devices are not described in this datasheet, orderable part numbers that do not
show the A internal code after temperature range code 6 should be referred to this datasheet for the
electrical characteristics. The low-density datasheet only covers STM32F101x6 devices that feature the A
code.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
78/85
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
8
Revision history
Revision history
Table 53.
Document revision history
Date
Revision
06-Jun-2007
1
First draft.
2
IDD values modified in Table 11: Maximum current consumption in Run
and Sleep modes (TA = 85 °C).
VBAT range modified in Power supply schemes.
VREF+ min value, tSTAB, tlat and fTRIG added to Table 41: ADC
characteristics. Table 37: TIMx characteristics modified.
Note 6 modified and Note 8, Note 5 and Note 7 added below Table 4:
Medium-density STM32F101xx pin definitions.
Figure 20: Low-speed external clock source AC timing diagram,
Figure 11: Power supply scheme, Figure 28: Recommended NRST pin
protection and Figure 29: I2C bus AC waveforms and measurement
circuit(1) modified.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
in Table 32: Electrical sensitivities.
tSU(LSE) changed to tSU(LSE) in Table 21: HSE 4-16 MHz oscillator
characteristics.
In Table 28: Flash memory endurance and data retention, typical
endurance added, data retention for TA = 25 °C removed and data
retention for TA = 85 °C added. Note removed below Table 8: General
operating conditions.
VBG changed to VREFINT in Table 11: Embedded internal reference
voltage. IDD max values added to Table 11: Maximum current
consumption in Run and Sleep modes (TA = 85 °C).
IDD(HSI) max value added to Table 23: HSI oscillator characteristics.
RPU and RPD min and max values added to Table 33: I/O static
characteristics. RPU min and max values added to Table 36: NRST pin
characteristics (two notes removed).
Datasheet title corrected. USB characteristics section removed.
Features on page 1 list optimized. Small text changes.
20-Jul-07
Changes
Doc ID 13586 Rev 13
79/85
Revision history
Table 53.
Date
18-Oct-2007
80/85
STM32F101x8, STM32F101xB
Document revision history (continued)
Revision
Changes
3
VESD(CDM) value added to Table 31: ESD absolute maximum ratings.
Note added below Table 10: Embedded reset and power control block
characteristics. and below Table 21: HSE 4-16 MHz oscillator
characteristics.
Note added below Table 34: Output voltage characteristics and VOH
parameter description modified.
Table 41: ADC characteristics and Table 43: ADC accuracy - limited test
conditions modified.
Figure 33: ADC accuracy characteristics modified.
Packages are ECOPACK® compliant.
Tables modified in Section 5.3.5: Supply current characteristics.
ADC and ANTI_TAMPER signal names modified (see Table 4: Mediumdensity STM32F101xx pin definitions). Table 4: Medium-density
STM32F101xx pin definitions modified. Note 4 removed and values
updated in Table 21: Typical current consumption in Standby mode.
Vhys modified in Table 33: I/O static characteristics.
Updated: Table 29: EMS characteristics and Table 30: EMI
characteristics.
tVDD modified in Table 9: Operating conditions at power-up / powerdown.
Typical values modified, note 2 modified and note 3 removed in Table 25:
Low-power mode wakeup timings.
Maximum current consumption Table 12, Table 13 and Table 14 updated.
Values added and notes added in Table 15: Typical and maximum
current consumptions in Stop and Standby modes.
On-chip peripheral current consumption on page 43 added.
Package mechanical data inch values are calculated from mm and
rounded to 4 decimal digits (see Section 6: Package characteristics).
Vprog added to Table 27: Flash memory characteristics.
TS_temp added to Table 45: TS characteristics.
TS_vrefint added to Table 11: Embedded internal reference voltage.
Handling of unused pins specified in General input/output characteristics
on page 52. All I/Os are CMOS and TTL compliant.
Table 4: Medium-density STM32F101xx pin definitions: table clarified
and Note 7 modified.
Internal LSI RC frequency changed from 32 to 40 kHz (see Table 24: LSI
oscillator characteristics). Values added to Table 25: Low-power mode
wakeup timings. NEND modified in Table 28: Flash memory endurance
and data retention.
Option byte addresses corrected in Figure 8: Memory map.
ACCHSI modified in Table 23: HSI oscillator characteristics.
tJITTER removed from Table 26: PLL characteristics.
Appendix A: Important notes on page 71 added.
Added: Figure 13, Figure 14, Figure 16 and Figure 18.
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Table 53.
Date
22-Nov-2007
Revision history
Document revision history (continued)
Revision
Changes
4
Document status promoted from preliminary data to datasheet. Small
text changes.
STM32F101CB part number corrected in Table 1: Device summary.
Number of communication peripherals corrected for STM32F101Tx in
Table 2: Device features and peripheral counts (STM32F101xx mediumdensity access line) and Number of GPIOs corrected for LQFP package.
Power supply schemes on page 16 modified.
Main function and default alternate function modified for PC14 and PC15
in Table 4: Medium-density STM32F101xx pin definitions, Note 6 added,
Remap column added.
Figure 11: Power supply scheme modified. VDD VSS ratings modified
and Note 1 modified in Table 5: Voltage characteristics. Note 1 modified
in Table 6: Current characteristics.
Note 2 added in Table 10: Embedded reset and power control block
characteristics.
48 and 72 MHz frequencies removed from Table 12, Table 13 and
Table 14. MCU ‘s operating conditions modified in Typical current
consumption on page 41.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum value
added in Table 15: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 16 on page 41 and Table 17
on page 42. Table 18: Peripheral current consumption modified.
Figure 17: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 30: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 31: SPI timing diagram - slave
mode and CPHA = 1(1).
Figure 34: Typical connection diagram using the ADC modified.
tSU(HSE) and tSU(LSE) conditions modified in Table 21 and Table 22,
respectively. Maximum values removed from Table 25: Low-power mode
wakeup timings. tRET conditions modified in Table 28: Flash memory
endurance and data retention. Conditions modified in Table 29: EMS
characteristics.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 71. Small text changes in Table 34: Output voltage characteristics.
Section 5.3.11: Absolute maximum ratings (electrical sensitivity)
updated.
Details on unused pins removed from General input/output
characteristics on page 52.
Table 40: SPI characteristics updated. Notes added and Ilkg removed in
Table 41: ADC characteristics. Note added in Table 42 and Table 45.
Note 3 and Note 2 added below Table 43: ADC accuracy - limited test
conditions. Avg_Slope and V25 modified in Table 45: TS characteristics.
JAvalue for VFQFPN36 package added in Table 51: Package thermal
characteristicsI2C interface characteristics on page 59 modified.
Order codes replaced by Section 7: Ordering information scheme.
Doc ID 13586 Rev 13
81/85
Revision history
Table 53.
STM32F101x8, STM32F101xB
Document revision history (continued)
Date
14-Mar-2008
21-Mar-2008
22-May-2008
82/85
Revision
Changes
5
Figure 2: Clock tree on page 13 added.
CRC added (see CRC (cyclic redundancy check) calculation unit on
page 9 and Figure 8: Memory map on page 28 for address).
Maximum TJ value given in Table 7: Thermal characteristics on page 32.
PD, TA and TJ added, tprog values modified and tprog description clarified
in Table 27: Flash memory characteristics on page 49.
IDD modified in Table 15: Typical and maximum current consumptions in
Stop and Standby modes on page 38.
ACCHSI modified in Table 23: HSI oscillator characteristics on page 48,
note 2 removed.
tRET modified in Table 28: Flash memory endurance and data retention.
VNF(NRST) unit corrected in Table 36: NRST pin characteristics on
page 58.
Table 40: SPI characteristics on page 62 modified.
IVREF added in Table 41: ADC characteristics on page 65.
Table 43: ADC accuracy - limited test conditions added. Table 44: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 70).
Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints
added (see Figure 42, Figure 44, Figure 46 and Figure 40).
Section 6.2: Thermal characteristics on page 76 modified.
Appendix A: Important notes removed.
6
Small text changes.
In Table 28: Flash memory endurance and data retention:
– NEND tested over the whole temperature range
– cycling conditions specified for tRET
– tRET min modified at TA = 55 °C
Figure 2: Clock tree corrected. Figure 8: Memory map clarified.
V25, Avg_Slope and TL modified in Table 45: TS characteristics.
CRC feature removed.
7
Section 1: Introduction modified, Section 2.2: Full compatibility
throughout the family added. CRC feature added.
IDD_VBAT removed from Table 21: Typical current consumption in Standby
mode on page 42.
Values added to Table 39: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3
V) on page 61.
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 63
modified. Equation 1 corrected.
Section 6.2.2: Evaluating the maximum junction temperature for an
application on page 77 added.
Axx option added to Table 52: Ordering information scheme on page 78.
Doc ID 13586 Rev 13
STM32F101x8, STM32F101xB
Table 53.
Date
Revision history
Document revision history (continued)
Revision
Changes
21-Jul-2008
8
Small text changes.
Power supply supervisor on page 16 modified and VDDA added to
Table 8: General operating conditions on page 32.
Capacitance modified in Figure 11: Power supply scheme on page 30.
Table notes revised in Section 5: Electrical characteristics.
Maximum value of tRSTTEMPO modified in Table 10: Embedded reset and
power control block characteristics on page 34.
Values added to Table 15: Typical and maximum current consumptions
in Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
fHSE_ext modified in Table 19: High-speed external user clock
characteristics on page 44. fPLL_IN modified in Table 26: PLL
characteristics on page 49.
fHCLK corrected in Table 29: EMS characteristics.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 38: I2C characteristics on page 60, note 1 modified.
th(NSS) modified in Table 40: SPI characteristics on page 62 and
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 63.
CADC modified in Table 41: ADC characteristics on page 65 and
Figure 34: Typical connection diagram using the ADC modified.
fPCLK2 corrected in Table 43: ADC accuracy - limited test conditions and
Table 44: ADC accuracy.
Typical TS_temp value removed from Table 45: TS characteristics on
page 69.
LQFP48 package specifications updated (see Table 50, Table 45 and
Table 46).
Axx option removed from Table 52: Ordering information scheme on
page 78.
24-Jul-2008
9
First page modified: “Up to 2 x I²C interfaces” instead of “1 x I²C
interface”
10
STM32F101xx devices with 32 Kbyte Flash memory capacity removed,
document updated accordingly.
Section 2.2: Full compatibility throughout the family on page 14 updated.
Notes modified in Table 4: Medium-density STM32F101xx pin definitions
on page 24.
Note 2 modified below Table 5: Voltage characteristics on page 31,
|VDDx| min and |VDDx| min removed.
Note 2 added to Table 8: General operating conditions on page 32.
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 35.
IDD in standby mode at 85 °C modified in Table 15: Typical and maximum
current consumptions in Stop and Standby modes on page 38.
General input/output characteristics on page 52 modified.
Note added below Table 52: Ordering information scheme.
Section 7.1: Future family enhancements removed. Small text changes.
23-Sep-2008
Doc ID 13586 Rev 13
83/85
Revision history
Table 53.
STM32F101x8, STM32F101xB
Document revision history (continued)
Date
21-Apr-2009
22-Sep-2009
20-May-2010
84/85
Revision
Changes
11
I/O information clarified on page 1. Figure 8: Memory map modified.
In Table 4: Medium-density STM32F101xx pin definitions: PB4, PB13,
PB14, PB15, PB3/TRACESWO moved from Default column to Remap
column.
Note modified in Table 12: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 14: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 16, Figure 17 and Figure 18 show typical curves.
Table 19: High-speed external user clock characteristics and Table 20:
Low-speed external user clock characteristics modified.
ACCHSI max values modified in Table 23: HSI oscillator characteristics.
Small text changes.
12
Note 5 updated and Note 4 added in Table 4: Medium-density
STM32F101xx pin definitions.
VRERINT and TCoeff added to Table 11: Embedded internal reference
voltage. Typical IDD_VBAT value added in Table 15: Typical and maximum
current consumptions in Stop and Standby modes. Figure 15: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 19: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator
characteristics and Table 22: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables.
Table 23: HSI oscillator characteristics modified. Conditions removed
from Table 25: Low-power mode wakeup timings.
Figure 28: Recommended NRST pin protection modified.
Note 1 modified below Figure 21: Typical application with an 8 MHz
crystal.
Figure 28: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 50.
Jitter added to Table 26: PLL characteristics. CADC and RAIN parameters
modified in Table 41: ADC characteristics. RAIN max values modified in
Table 42: RAIN max for fADC = 14 MHz.
Small text changes.
13
Added STM32F101TB devices.
Added VFQFPN48 package.
Updated note 2 below Table 38: I2C characteristics
Updated Figure 29: I2C bus AC waveforms and measurement circuit(1)
Updated Figure 28: Recommended NRST pin protection
Updated Section 5.3.12: I/O port characteristics
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STM32F101x8, STM32F101xB
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