STMICROELECTRONICS STP130NH02L

STB130NH02L
STP130NH02L
N-CHANNEL 24V - 0.0034 Ω - 120A D²PAK/TO-220
STripFET™ III POWER MOSFET FOR DC-DC CONVERSION
Table 1: General Features
TYPE
STB130NH02L
STP130NH02L
■
■
■
■
■
■
■
Figure 1:Package
VDSS
RDS(on)
ID
24 V
24 V
< 0.0044 Ω
< 0.0044 Ω
90 A(2)
90 A(2)
TYPICAL RDS(on) = 0.0034 Ω @ 10 V
TYPICAL RDS(on) = 0.005 Ω @ 5 V
RDS(ON) * Qg INDUSTRY’s BENCHMARK
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
LOW THRESHOLD DEVICE
SURFACE-MOUNTING D2PAK (TO-263)
POWER PACKAGE IN TUBE (NO SUFFIX) OR
IN TAPE & REEL (SUFFIX “T4”)
3
1
D2PAK
TO-263
(Suffix “T4”)
3
1
2
TO-220
DESCRIPTION
The STB_P130NH02L utilizes the latest advanced
design rules of ST’s proprietary STripFET™ technology.
It is ideal in high performance DC-DC converter
applications where efficiency is to be achieved at very
high output currents.
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ SYNCHRONOUS RECTIFICATIONS FOR
TELECOM AND COMPUTER
■ OR-ING DIODE
Table 2: Ordering Information
SALES TYPE
STB130NH02LT4
STP130NH02L
MARKING
B130NH02L
P130NH02L
PACKAGE
TO-263
TO-220
PACKAGING
TAPE & REEL
TUBE
ABSOLUTE MAXIMUM RATINGS
Symbol
Vspike(1)
VDS
VDGR
VGS
ID(2)
ID(2)
IDM(3)
Ptot
EAS (4)
Tstg
Tj
April 2005
Parameter
Drain-source Voltage Rating
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
30
24
24
± 20
90
90
360
150
1
900
Unit
V
V
V
V
A
A
A
W
W/°C
mJ
-55 to 175
°C
Rev. 2.0
1/13
STB130NH02L STP130NH02L
Table 4: THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
°C/W
°C/W
°C
1.0
62.5
300
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
Table 5: OFF
Symbol
V(BR)DSS
IDSS
IGSS
Parameter
Test Conditions
Drain-source
Breakdown Voltage
ID = 25 mA, VGS = 0
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = 20 V
VDS = 20 V
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20 V
Min.
Typ.
Max.
24
Unit
V
TC = 125°C
1
10
µA
µA
±100
nA
Max.
Unit
Table 6: ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
VGS = 5 V
ID = 45 A
ID = 22.5 A
Min.
Typ.
1
V
0.0034
0.005
0.0044
0.008
Ω
Ω
Typ.
Max.
Unit
Table 7: DYNAMIC
Symbol
Test Conditions
gfs (5)
Forward Transconductance
VDS = 10 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 15V f = 1 MHz VGS = 0
Gate Input Resistance
f = 1 MHz Gate DC Bias = 0
Test Signal Level = 20 mV
Open Drain
RG
2/13
Parameter
ID = 45 A
Min.
55
S
4450
1126
141
pF
pF
pF
1.6
Ω
STB130NH02L STP130NH02L
ELECTRICAL CHARACTERISTICS (continued)
Table 8: SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 10 V
ID = 45 A
VGS = 10 V
RG = 4.7 Ω
(Resistive Load, Figure )
14
224
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD=10 V ID=90 A VGS=10 V
69
13
9
Max.
Unit
ns
ns
93
nC
nC
nC
Qoss(6)
Output Charge
VDS= 16 V
VGS= 0 V
27
nC
Qgls(7)
Third-quadrant Gate Charge
VDS< 0 V
VGS= 10 V
64
nC
Table 9: SWITCHING OFF
Symbol
td(off)
tf
Parameter
Turn-off Delay Time
Fall Time
Test Conditions
Min.
Typ.
Max.
Unit
69
40
54
ns
ns
Typ.
Max.
Unit
90
360
A
A
1.3
V
VDD = 10 V
ID = 45 A
VGS = 10 V
RG = 4.7Ω,
(Resistive Load, Figure 3)
Table 10: SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM
Source-drain Current
Source-drain Current (pulsed)
VSD (5)
trr
Qrr
IRRM
Test Conditions
Forward On Voltage
ISD = 45 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 90 A
di/dt = 100A/µs
Tj = 150°C
VDD = 15 V
(see test circuit, Figure 5)
Min.
VGS = 0
47
58
2.5
(1) Garanted when external Rg=4.7 Ω and tf < tfmax.
(2) Value limited by wire bonding
(3) Pulse width limited by safe operating area.
(4) Starting Tj = 25 oC, ID = 45A, VDD = 10V .
(5) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(6) Qoss = Coss*∆ Vin , Coss = Cgd + Cds . See Appendix A
(7) Gate charge for synchronous operation
Figure 3: Safe Operating Area
Figure 4: Thermal Impedance
ns
nC
A
3/13
STB130NH02L STP130NH02L
Figure 5: Output Characteristics
Figure 6: Transfer Characteristics
Figure 7: Transconductance
Figure 8: Static Drain-source On Resistance
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Capacitance Variations
4/13
STB130NH02L STP130NH02L
Figure 11: Normalized Gate Threshold Voltage vs
Temperature
Figure 12: Normalized on Resistance vs Temperature
Figure 13: Source-drain Diode Forward Characteristics
Figure 14: Normalized Breakdown Voltage vs
Temperature
.
.
5/13
STB130NH02L STP130NH02L
Figure 15: Unclamped Inductive Load Test Circuit
Figure 16: Unclamped Inductive Waveform
Figure 17: Switching Times Test Circuits For Resis-
Figure 18: Gate Charge test Circuit
tive Load
Figure 19: Test Circuit For Inductive Load Switch-
ing And Diode Recovery Times
6/13
STB130NH02L STP130NH02L
TO-220 MECHANICAL DATA
DIM.
mm.
MIN.
TYP.
inch.
MAX.
MIN.
A
4.4
4.6
0.173
TYP.
0.181
TYP.
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
0.107
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.40
2.70
0.094
0.106
H2
10
10.40
0.393
0.409
L2
16.40
L3
0.645
28.90
1.137
L4
13
14
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.20
6.60
0.244
0.260
L9
3.50
3.93
0.137
0.154
DIA
3.75
3.85
0.147
0.151
7/13
STB130NH02L STP130NH02L
D2PAK MECHANICAL DATA
DIM.
mm.
MIN.
MAX.
MIN.
A
4.4
4.6
0.173
0.181
A1
2.49
2.69
0.098
0.106
A2
0.03
0.23
0.001
0.009
TYP.
TYP.
B
0.7
0.93
0.028
0.037
B2
1.14
1.7
0.045
0.067
C
0.45
0.6
0.018
0.024
C2
1.21
1.36
0.048
0.054
D
8.95
9.35
0.352
D1
E
8
10
E1
0.368
0.315
10.4
0.394
8.5
0.409
0.334
G
4.88
5.28
0.192
0.208
L
15
15.85
0.591
0.624
L2
1.27
1.4
0.050
0.055
L3
1.4
1.75
0.055
0.069
M
2.4
3.2
0.094
R
V2
8/13
TYP.
inch.
0.4
0°
0.126
0.015
8°
0°
8°
STB130NH02L STP130NH02L
D2PAK FOOTPRINT
TUBE SHIPMENT (no suffix)*
TAPE AND REEL SHIPMENT (suffix ”T4”)*
REEL MECHANICAL DATA
DIM.
mm
MIN.
A
inch
MAX.
MIN.
330
B
1.5
C
12.8
D
20.2
G
24.4
N
100
T
MAX.
12.992
0.059
13.2
0.504
0.520
0.795
26.4
0.960
1.039
3.937
30.4
1.197
BASE QTY
BULK QTY
1000
1000
TAPE MECHANICAL DATA
DIM.
mm
inch
MIN.
MAX.
MIN.
MAX.
A0
10.5
10.7
0.413
0.421
B0
15.7
15.9
0.618
0.626
D
1.5
1.6
0.059
0.063
D1
1.59
1.61
0.062
0.063
E
1.65
1.85
0.065
0.073
F
11.4
11.6
0.449
0.456
K0
4.8
5.0
0.189
0.197
0.161
P0
3.9
4.1
0.153
P1
11.9
12.1
0.468
0.476
P2
1.9
2.1
0075
0.082
R
50
T
0.25
0.35
.0.0098
1.574
0.0137
W
23.7
24.3
0.933
0.956
* on sales type
9/13
STB130NH02L STP130NH02L
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
•
•
•
•
•
Very low RDS(on) to reduce conduction losses
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires:
•
Small Rg and Ls to allow higher gate current peak and to limit the voltage
feedback on the gate
•
Small Q g to have a faster commutation and to reduce gate charge losses
•
Low RDS(on) to reduce the conduction losses.
10/13
STB130NH02L STP130NH02L
Pconduction
Pswitching
High Side Switch (SW1)
Low Side Switch (SW2)
R DS(on)SW1 * I 2L * δ
R DS(on)SW2 * I 2L * (1 − δ )
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
IL
Ig
Zero Voltage Switching
Recovery
Not Applicable
Conduction
Not Applicable
Vf(SW2) * I L * t deadtime * f
Pgate(Q G )
Q g(SW1) * Vgg * f
Q gls(SW2) * Vgg * f
PQoss
Vin * Q oss(SW1) * f
Vin * Q oss(SW2) * f
2
2
Pdiode
1
Parameter
d
Qgsth
Qgls
Pconduction
Pswitching
Pdiode
Meaning
Duty-cycle
Post threshold gate charge
Third quadrant gate charge
On state losses
On-off transition losses
Conduction and reverse recovery diode losses
Pgate
PQoss
Gate drive losses
Output capacitance losses
1
Vin * Q rr(SW2) * f
Dissipated by SW1 during turn-on
11/13
STB130NH02L STP130NH02L
Table 11:Revision History
12/13
Date
Revision
April 2005
2.0
Description of Changes
ADDED PACKAGE TO-220
STB130NH02L STP130NH02L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners.
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13/13