TDA9105 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS PRELIMINARY DATA VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP DCCONTROLLED V-AMP, V-POS,S-AMP &C-COR ON/OFF SWITCH EWPCC VERTICAL PARABOLA GENERATOR WITH DC CONTROLLED KEYSTONE & AMPLITUDE AUTO TRACKING WITH V-POS & V-AMP This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors. This IC, combined with TDA9205 (RGB preamp), STV942x (OSD processor), ST727x (micro controller) and TDA817x (vertical booster), allows to realize very simple and high quality multimodes or multisync monitors. SHRINK42 (Plastic Package) ORDER CODE : TDA9105 PIN CONNECTIONS V-F OCUS 1 42 S P INBAL H-LOC KOUT 2 41 KEYBAL P LL2C 3 40 GEOMOUT GEOMETRY WAVE FORM GENERATOR FOR PARALELLOGRAM & SIDE PIN BALANCE CONTROL AUTO TRACKING WITH V-POS & V-AMP H-DUTY 4 39 EWAMP H-F LY 5 38 KEYS T H-G ND 6 37 EWO UT H-R EF 7 36 V-FLY DYNAMIC FOCUS VERTICAL PARABOLA OUTPUT FOR VERTICAL DYNAMIC FOCUS AUTO TRACKING WITH V-POS & V-AMP FC2 8 35 VDCIN FC1 GENERAL ACCEPT POSITIVE OR NEGATIVE HORIZONTAL & VERTICAL SYNC POLARITIES SEPARATE H & V TTL INPUT COMPOSITE BLANKING OUTPUT DESCRIPTION The TDA9105 is a monolithic integrated circuit assembled in a 42 pins shrink dual in line plastic package. 9 34 V-S YNC C0 10 33 V-P OS R0 11 32 VDCO UT P LL1F 12 31 V-AMP H-LOC KCAP 13 30 V-OUT P LL1INHIB 14 29 C-CORR H-P OS 15 28 VS-AMP XRAY-IN 16 27 V-CAP H-S YNC 17 26 V-RE F VCC 18 25 V-AGCCAP GND 19 24 V-GND H-O UTE M 20 23 MOIRE H-O UTC OL 21 22 BLK-OUT June 1996 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice. 9105-01.EPS .. .. .. . . .. .. .. . . . . . . . .. HORIZONTAL DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY SELF-ADAPTATIVE X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE 1st PLL LOCK /UNLOCK INFORMATION WIDE RANGE DC CONTROLLED H-POSITION ON/OFF SWITCH (FOR PWR MANAGEMENT) TWO H-DRIVE POLARITIES MOIRE OUTPUT 1/32 TDA9105 PIN DESCRIPTION Pin 1 Name V-FOCUS 2 3 4 H-LOCKOUT PLL2C H-DUTY 5 H-FLY First PLL Lock/Unlock Output Second PLL Loop Filter DC Control of Horizontal Drive Output Pulse Duty-cycle. If this Pin is grounded, the Horizontal and Vertical Outputs are inhibited. By connecting a Capacitor on this Pin a Soft-start function may be realized on H-drive Output. Horizontal Flyback Input (positive polarity) 6 7 8 H-GND H-REF FC2 Horizontal Section Ground Horizontal Section Reference Voltage, must be filtered VCO Low Threshold Filtering Capacitor 9 10 11 FC1 C0 R0 12 13 PLL1F H-LOCKCAP 14 15 PLL1INHIB H-POS 16 17 18 XRAY-IN H-SYNC VCC 19 20 21 GND H-OUTEM H-OUTCOL 22 BLK OUT 23 24 25 MOIRE V-GND V-AGCCAP 26 27 28 V-REF V-CAP VS-AMP Vertical Section Reference Voltage Vertical Sawtooth Generator Capacitor DC Control of Vertical S-Shape Amplitude 29 30 31 C-CORR V-OUT V-AMP DC Control of Vertical C-Correction Vertical Ramp Output (with frequency independant amplitude and S-Correction) DC Control of Vertical Amplitude Adjustment 32 VDCOUT Vertical Position Reference Voltage Output 33 34 35 V-POS V-SYNC VDCIN DC Control of Vertical Position Adjustment TTL-Compatible Vertical Sync Input Geometric Correction Reference Voltage Input 36 37 38 V-FLY EWOUT KEYST Vertical Flyback Input (positive polarity) East /West Pincushion Correction Parabola Output DC Control of Keystone Correction 39 40 41 EWAMP GEOMOUT KEYBAL 42 SPINBAL 2/32 Function Vertical Dynamic Focus Output VCO High Threshold Filtering Capacitor Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter First PLL Lock/Unlock Time Constant Capacitor. When Frequency is changing, a Blanking Pulse is generated on Pin 23, the duration of this Pulse is proportionnel to the Capacitor on Pin 13. TTL-Compatible Input for PLL1 Output Current Inhibition DC Control for Horizontal Centering X-RAY protection Input (with internal latch function) TTL compatible Horizontal Sync Input Supply Voltage (12V Typ.) Ground Horizontal Drive Output (emiter of internal transistor) Horizontal Drive Output (open collector of internal transistor) Blanking Output, activated during frequency changes, when X-RAY Input is triggered, when VS is too low, or when Device is in stand-by mode (through H-DUTY Pin 2) and during H-FLY, V-FLY, V-SYNC, VSawth retrace. DC Control East/West Pincushion Correction Amplitude Side Pin Balance & Parallelogram Correction Parabola Output DC Control of Parallelogram Correction DC Control of Side Pin Correction Amplitude 9105-01.TBL Moire Output Vertical Section Signal Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator 9105-02.EPS V-SYNC 34 V-GND 24 TDA9105 PULSE SHAPER POL DETECT H-FLY 35 22 36 32 33 30 31 25 27 V-SYNC BLK GEN 29 VERT OSC RAMP GENERATOR V-MID 28 S CORR V-REF X 2 VS-AMP V-Sync H-Sync C-CORR V-REF 26 SAFETY PROCESSOR H OUTPUT BUFFER 20 21 VCAP H-LOCKCAP 13 VS PULSE SHAPER 4 VAGCCAP PHASE SHIFTER 16 2 V-AMP PLL1 INHIB VIDEO UNLOCK 3 PLL2C V-OUT PLL1INHIB 14 LOCK UNLOCK IDENT 5 FC1 PHASE COMP H-FLY 9 H-LOCKOUT V-POS PULSE SHAPER POL DETECT R0 VCO 8 XRAY-IN VDCOUT H-SYNC 17 PHASE FREQUENCY COMP FC2 11 H-DUTY V-FLY V-REF C0 10 H-OUTCOL BLK-OUT H-GND 6 PLL1F 12 H-OUTEM VDCIN H-REF 7 H-POS 15 MOIRE V-FOCUS 42 SPINBAL 40 GEOMOUT 41 KEYBAL 39 EWAMP 37 EWOUT 38 KEYST 1 18 VCC 19 GND 23 MOIRE TDA9105 BLOCK DIAGRAM 3/32 TDA9105 QUICK REFERENCE DATA Notes : 1. Provided PLL inhibition input is used, see application diagram on page 27. 2. One for Horizontal section and one for Vertical section. 4/32 Value 15 to 150 1 to 3.7 YES YES (see note 1) YES YES YES YES YES YES YES YES YES YES 35 to 200 50 to 165 YES YES YES YES YES YES YES YES YES YES YES YES (see note 2) NO YES Unit kHz FH Hz Hz 9105-02.TBL Parameter Horizontal Frequency Autosynch Frequency (for Given R0, C0) ± Hor Sync Polarity Input Compatibility with Composite Sync on H-SYNC Input st Lock/Unlock Identification on 1 PLL DC Control for H-Position X-RAY Protection Hor DUTY Adjust Stand-by Function Two Polarities H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Input Composite Blanking Output Horizontal Moire Output Vertical Frequency Vertical Autosync (for 150nF) Vertical S-Correction Vertical C-Correction Vertical Amplitude Adjustment Vertical Position Adjustment East/West Parabola Output PCC (Pin Cushion Correction) Amplitude Adjustment Keystone Adjustment Dynamic Horizontal Phase Control Output Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections with V-AMP and V-POS Reference Voltage Mode Detection Vertical Dynamic Focus TDA9105 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit VCC Supply Voltage (Pin 18) 13.5 V VIN Max Voltage on Pins 4, 15, 28, 29, 31, 33, 38, 39, 41, 42 Pin 5 Pins 17, 34 Pin 16 8 1.8 6 12 V ESD Succeptibility Human Body Model, 100pF Discharge through 1.5kΩ EIAJ Norm, 200pF Discharge through 0Ω 2 300 kV V -40, +150 °C 150 °C 0, +70 °C Value Unit 65 °C/W VESD Tstg Tj Toper Storage Temperature Max Operating Junction Temperature Operating Temperature 9105-03.TBL Symbol Symbol Rth (j-a) Parameter Junction-Ambient Thermal Resistance Max. 9105-04.TBL THERMAL DATA HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Unit VCO R0min Oscillator Resistor Min Value (Pin 11) 6 kΩ C0min Oscillator Capacitor Min Value (Pin 10) 390 pF Fmax Maximum Oscillator Frequency HsVR Horizontal Sync Input Voltage (Pin 17) 0 150 kHz 5.5 V INPUT SECTION MinD Minimum Input Pulses Duration (Pin 17) Mduty Maximum Input Signal Duty Cycle (Pin 17) µS 0.7 25 % 5 mA 20 20 mA mA 6 V I5m Maximum Input Peak Current (Pin 5) HOI1 HOI2 Horizontal Drive Output Max Current Pin 20 Pin 21 Sourced current Sink current DC CONTROL VOLTAGES DCadj DC Voltage on DC Controls (Pins 4-15) VREF-H = 8V 2 5/32 9105-05.TBL OUTPUT SECTION TDA9105 HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit 10.8 12 13.2 V SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage (Pin 18) ICC VREF-H IREF-H Supply Current (Pin 18) Reference Voltage for Horizontal Section (Pin 7) Max Sourced Current on VREF-H (Pin 7) See Figure 1 I = 2mA 7.4 40 8 60 8.6 5 mA V mA VREF-V IREF-V Reference Voltage for Vertical Section (Pin 26) Max Sourced Current on VREF-V (Pin 26) I = 2mA 7.4 8 8.6 5 V mA 0.8 V INPUT SECTION/PLL1 VINTH Horizontal Input Threshold Voltage (Pin 17) Low level voltage High level voltage VREF-H = 8V R0 = 6.49kΩ, C0 = 680pF VVCO VCOG VCO Control Voltage (Pin 12) VCO Gain, dF/dV (Pin 12) Hph f0 CR IHLock0 Horizontal Phase Adjust (Pin 15) % of Horizontal period Free Running Frequency (adjustable by changing R0) R0 = 6.49kΩ, C0 = 680pF PLL1 Capture Range R0 = 6.49kΩ, C0 = 680pF See conditions on Fig. 1 Fh Min Fh Max PLL 1 Inhibition (Pin 14) PLL ON V14 V14 (Typ. Threshold = 1.6V) PLL OFF Max Output Current on HLock Output I2 VHLock0 Low Level Voltage on HLock Output PLLinh 2 1.6 to 6.2 17 25 ±12.5 27 V kHz/V 29 f0 3.7 x f0 10 kHz kHz V V mA 0.5 V 0.8 2 V2 with I2 = 10mA 0.25 % kHz SECOND PLL AND HORIZONTAL OUTPUT SECTION Hjit Flyback Input Threshold Voltage (Pin 5) See Figure 14 Horizontal Jitter See Application Diagram (Pins 8-9) HDmin Horizontal Drive Output Duty-cycle (Pin 20 or 21) (see Note) Minimum HDmax HDvd Maximum Horizontal Drive Low Level Output Voltage HDem Horizontal Drive High Level Output Voltage (output on Pin 20) XRAYth X-RAY Protection Input Threshold Voltage (Pin 16) ISblkO Maximum Output Current on Composite Blanking Output VSblkO Low-Level Voltage on Composite Blanking Output (Blanking ON) ISmoiO Maximum Output Current on Moire Output VSmoiO Low-Level Voltage on Moire Output Vphi2 VOFF VSCinh Internal Clamping Voltage on 2nd PLL Loop Filter Output (Pin 3) Threshold Voltage to Stop H-out, V-out and to Activate BLKout (OFF Mode when V4 < VOFF) (Pin 4) Supply Voltage to Stop H-out, V-out when VCC < VSCinh (Pin 18) V4 = 2V V4 = 6V V4 = VREF - 100mV Pin 20 to GND, V21-V20 , IOUT = 20mA Pin 21 to VCC, IOUT = 20mA 0.65 0.75 V 80 ppm 32 53.5 57.5 34 56 60 1.1 9.5 10 TBD 8 I22 % % % V V TBD V 10 mA V22 with I22 = 10mA 0.25 0.5 V I23 V23 with I23 = 10mA 0.25 10 0.5 mA V 1 V V V Vmin Vmax V4 1.6 3.2 TBD 7.5 Note : If H-drive is taken on Pin 20 (Pin 21 connected to supply), H-D is the ratio of low level duration to horizontal period. If H-drive is taken on Pin 21 (Pin 20 grounded), H-D is the ratio of high level duration to horizontal period. In both cases, H-D period driving horizontal scanning transistor off. 6/32 36 58.5 62.5 1.7 V 9105-06.TBL FBth TDA9105 Symbol VSVR VEWM VDHPCM VDHPCm VDFm Rload Parameter Vertical Sync Input Voltage (Pin 34) Maximum EW Output Voltage (Pin 37) Maximum Dynamic Horizontal Phase Control Output Voltage (Pin 40) Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40) Minimum Vertical Dynamic Focus Output Voltage (Pin 1) Minimum Load for less than 1% Vertical Amplitude Drift (Pin 25) Min. 0 Typ. Max. 5.5 6.5 6.5 Unit V V V V V MΩ Typ. 2 Max. Unit µA 0.9 0.9 65 9105-07.TBL VERTICAL SECTION Operating Conditions Electrical Characteristics (VCC = 12V, Tamb = 25°C) IBIASN VSth VSBI Parameter Bias Current (current sourced by PNP Base) (Pins 28-29) Bias Current (Pin 31) (sinked by NPN base) Vertical Sync Input Threshold Voltage (Pin 34) VFRF Vertical Sync Input Bias Current (Current Sourced by PNP Base) Voltage at Ramp Bottom Point (Pin 27) Voltage at Ramp Top Point (with Sync) (Pin 27) Voltage at Ramp Top Point (without Sync) (Pin 27) Minimum Vertical Sync Pulse Width (Pin 34) Vertical Sync Input Maximum Duty-cycle (Pin 34) Vertical Sawtooth Discharge Time Duration (Pin 27) Vertical Free Running Frequency ASFR RAFD AUTO-SYNC Frequency (see Note 1) Ramp Amplitude Drift Versus Frequency Rlin Vpos Ramp Linearity on Pin 30 Vertical Position Adjustment Voltage (Pin 32) IVPOS Max Current on Vertical Position Control Output (Pin 32) Vertical Output Voltage (Pin 30) (peak-to-peak voltage on Pin 30) VRB VRT VRTF VSW VSmDut VSTD VOR VOUTDC V0I dVS Ccorr VFly Th VFly Inh IBIAS DCIN DC Voltage on Vertical Output (Pin30) Vertical Output Maximum Current (Pin 30) Max Vertical S-Correction Amplitude V28 = 2V inhibits S-CORR V28 = 6V gives maximum S-CORR Max Vertical C-Correction Amplitude Vertical Flyback Threshold (Pin 36) Inhibition of Vertical Flyback Input (Pin 36) Bias Current (Pin 35) (sourced by PNP base) Test Conditions For V28-29 = 2V For V31 = 6V High-level Low-level V34 = 0.8V Min. 1 µA V V µA 2/8 5/8 VRT-0.1 VREF-V VREF-V V 0.5 2 0.8 5 15 µS % With 150nF cap 70 µS V28 = 2V, V29 grounded, Measured on Pin 27 Cosc (Pin27) = 150nF 50 With C 27 = 150nF V31 = 6V, C27 = 150nF 50Hz < f < 165Hz V28, V29 grounded V33 = 2V V33 = 4V 3.65 V33 = 6V 100 Hz V31 = 2V V31 = 4V V31 = 6V See Note 2 2 3 4 7/16 ±5 ∆V/V30pp at T/4 ∆V/V30pp at 3T/4 V29 = 2V V29 = 4V V29 = 6V See Note 1 For V35 = V32 3.75 165 100 0.5 3.2 3.5 3.8 ±2 3.3 2.2 -4 TBD +4 -5 TBD 0 TBD +5 1 TBD VREF- 0.5 2 TBD Hz ppm/Hz % V V V mA V V V VREF-V mA % % % % % V V µA Notes : 1. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 2. Typically 3.5V for Vertical reference voltage typical value (8V). 7/32 9105-08.TBL Symbol IBIASP TDA9105 VERTICAL SECTION (continued) East/West Function Symbol Parameter Test conditions Min. Typ. Max. Unit EWDC DC Output Voltage (see Figure 2) V33 = 4V , V35 = V32, V38 = 4V 2.5 V TDEWDC DC Output Voltage Thermal Drift See Note 2 100 ppm/°C Parabola Amplitude V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32 , V38 = 4V, V39 = 6V V39 = 2V 2.9 0 V V 0.36 0.82 1.45 V V V EWtrack KeyAdj Parabola Amplitude versus V-AMP Control (tracking between V-AMP and E/W) Keystone Adjustment Capability : A/B Ratio (see Figure 2) B/A Ratio Keytrack Keystone versus V-POS control (tracking between V-POS and EW) A/B Ratio B/A Ratio TBD V28 = 2V, V29 grounded V33 = 4V, V35 = V32, V38 = 4V, V39 = 4V V31 = 2V V31 = 4V V31 = 6V V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32 , V39 = 4V V38 = 6V V38 = 2V TBD TBD V28 = 2V, V29 grounded, V31 = 6V, V38 = 4V, V39 = 6V V33 = 2V, V35 = V32 V33 = 6V, V35 = V32 0.48 0.48 9105-09.TBL EWpara 0.54 0.54 Notes : 1. When Pin 36 >VREF - 0.5V, Vfly input is inhibited and vertical blanking on composite blanking output is replaced by vertical sawtooth discharge time. 2. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. Dynamic Horizontal Phase Control Function Parameter Test Conditions DC Ouput Voltage (see Figure 3) V33 = 4V, V35 = V32 , V41 = 4V TDDHPC DC DC Output Voltage Thermal Drift See Note Side Pin Balance Parabola Amplitude (see Figure 3) V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32, V41 = 4V V42 = 6V V42 = 2V SPBpara SPBtrack ParAdj Side Pin balance Parabola Amplitude versus V-amp Control (tracking between V-amp and SPB ) Parallelogram Adjustment Capability A/B ratio (see Figure.3) B/A ratio Partrack 8/32 Parallelogram versus V-pos Control (tracking between V-pos and DHPC) A/B ratio B/A ratio Min. TBD V28 = 2V, V29 grounded, V33 = 4V, V35 = V32 , V41 = 4V, V42 = 6V V31 = 2V V31 = 4V V31 = 6V V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32, V42 = 6V V41 = 6V V41 = 2V V28 = V31 = V33 = V33 = 2V, V29 grounded, 6V, V41 = 4V, V42 = 6V 2V, V35 = V32 , 6V, V35 = V32 Typ. Unit V 100 ppm/°C +1.45 - 1.45 0.36 0.82 1.45 TBD TBD Max. 4 TBD V V V V V 0.12 0.12 0.53 0.53 9105-10.TBL Symbol DHPCDC TDA9105 VERTICAL SECTION (continued) Vertical Dynamic Focus Function Parameter Test Conditions VDFDC DC Output Voltage (see Figure 4) V33 = 4V, V35 = V32 TDVDFDC DC Output Voltage Thermal Drift See Note VDFAMP Parabola Amplitude versus V-amp (tracking between V-amp and VDF) (see Figure 4) V28 = 2V, V29 grounded, V33 = 4V, V35 = V32, V31 = 2V V31 = 4V V31 = 6V Parabola Assymetry versus V-pos Control (tracking between V-pos and VDF) A/B ratio B/A ratio V28 = 2V, V29 grounded, V31 = 6V, VDFKEY V33 = 2V, V35 = V32, V33 = 6V, V35 = V32 Min. Typ. Max. Unit 6 V 100 ppm/C -0.84 -1.78 -3.14 -0.72 -1.57 -2.85 -0.6 -1.36 -2.56 0.42 0.48 0.52 0.58 0.62 0.68 V V V 9105-11.TBL Symbol Note : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 9/32 220nF 9105-03.EPS 2.2 µF 2.2 µF 34 24 26 TDA9105 PULSE SHAPER POL DETECT PLL1 INHIB 14 13 PULSE SHAPER POL DETECT V-REF 17 6 7 10nF 29 S CORR 1µF 28 12 1.8kΩ 680pF 1% 150nF 1% 27 25 6.49kΩ 0.1% 31 V-MID 470nF 1% VERT OSC RAMP GENERATOR 8 47nF 5 47nF PHASE COMP 9 30 VIDEO UNLOCK 11 VCO 10 LOCK UNLOCK IDENT 4.7µF V-REF PHASE FREQUENCY COMP 15 33 3 10kΩ 32 V-SYNC H-FLY PHASE SHIFTER 2 16 36 VS BLK GEN 10kΩ VCC 22 1kΩ 20 X2 H OUTPUT BUFFER 21 SAFETY PROCESSOR PULSE SHAPER 4 VCC 35 18 12V VCC V-Sync H-Sync MOIRE 2.2µF 10/32 42 40 41 39 37 38 1 19 23 100nF VCC VCC 10kΩ 10kΩ 10kΩ 10kΩ TDA9105 Figure 1 : Testing Circuit 22nF TDA9105 Figure 2 : E/W Output Figure 3 : Dynamic Horizontal Phase Control Output V42 = 6V V41 = 6V B B SPBPARA 9105-04.EPS EWDC DHPCDC V42 = 2V 9105-05.EPS A EWPARA A Figure 4 : Vertical Dynamic Focus Function A VDFAMP B 9105-06.EPS VDFDC V33 = 2V 11/32 TDA9105 TYPICAL VERTICAL OUTPUT WAVEFORMS Function Vertical Size Vertical Position DC Control Vertical DC In/Out Control Pin 31 Output Pin Control Voltage Specification Picture Image 2V 2V 6V 4V 30 33 32 35 1 37 40 2V 4V 6V 3.2V 3.5V 3.8V T h i s te r mi n al i s a P in controlling the center position of ge o me t ri c co r re c ti o n signals. When connected to Pin 32, ”Autotracking” occurs. 2V 25 30 ∆V 6V ∆V = 4% VPP VPP ∆V 2V Vertical C Linearity ∆V = 5% VPP VPP 29 30 ∆V 6V VPP 12/32 ∆V = 5% VPP 9105-13.TBL / 9105-07.EPS TO 9105-13.EPS Vertical S Linearity TDA9105 TYPICAL GEOMETRY OUTPUT WAVEFORMS Function Control Pin Output Pin Control Voltage Specification V39 = 4V 4.95V Picture Image 2.95V 2V Trapezoid Control 38 2.5V 37 4.95V 2.95V 6V 2.5V V38 = 4V Pin Cushion Control 2V 39 2.5V 0V 37 2.9V 6V V42 = 4V Parrallelogram Control 41 2V 4V 3V 6V 4V 3V 40 V41 = 4V 42 4V 1.45V 9105-14.TBL / 9105-14.EPS TO 9105-22.EPS 2V Side Pin Balance Control 40 1.45V 6V Vertical Dynamic Focus 6V 1 3V Note : The specification of Output voltage is indicated on 4VPP vertical sawtooth output condition.The output voltage depends on vertical sawtooth output voltage. 13/32 TDA9105 OPERATING DESCRIPTION GENERAL CONSIDERATIONS Power Supply The typical value of the power supply voltage VCC is 12V. Perfect operation is obtained if VCC is maintained in the limits : 10.8V → 13.2V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputs of the circuit are inhibited if VCC < 7.6 typically. In order to have a very good powersupplyrejection, the circuit is internally powered by several internal voltage references (The unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal part. These voltage references can be used for the DC control voltages applied on the concerned pins by the way of potentiometers or digital to analog converters (DAC’s). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the ”jitter” on vertical and horizontal output signals. In order to have a good tracking with the voltage reference value, it’s better to maintain the control voltages between VREF /4 and 3/4 ⋅ VREF. The input current of the DC control inputs is typically very low (about a few µA). Depending on the internal structure of the inputs, it can be positive or negative (sink or source). DC Control Adjustments The circuit has 10 adjustment capabilities : 2 for the horizontal part, 2 for the E/W correction, 4 for the vertical part, 2 for the Dynamic Horizontal phase control. The corresponding inputs of the circuit has to be driven with a DC voltage typically comprised between 2 and 6V for a value of the internal voltage reference of 8V. Concerning the duty cycle of the input signal, the following signals may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T ≤ 25%. Synchronisation occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7µs. Figure 5 : HORIZONTAL PART Input section The horizontal input is designed to be sensitive to TTL signals typically comprised between 0 and 5V. The typical threshold of this input is 1.6V. This input stage uses an NPN differential stage and the input current is very low. Figure 6 : Input Structure 1.6V 9105-24.EPS H-SYNC Figure 7 Example of Practical DC Control Voltage Generation DC Control Voltage 9105-23.EPS PWM DAC Output 9105-25.EPS VREF 14/32 PLL1 The PLL1 is composed of a phase comparator, an external filter and a Voltage Controlled Oscillator (VCO). The phase comparator is a ”phase frequency” type, designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a ”charge pump”, composed of 2 current sources sink and source (I = 1mA typ.) TDA9105 OPERATING DESCRIPTION (continued) Figure 8 : Principle Diagram H-LOCKCAP 13 H-LOCKOUT 2 PLL1INHIB PLL1F 14 12 R0 11 C0 10 LOCKDET High CHARGE PUMP COMP1 E2 PLL INHIBITION VCO Low H-POS 15 OSC 9105-26.EPS H-SYNC 17 INPUT INTERFACE 3.2V PHASE ADJUST tive frequency range has to be smaller (e.g. 30kHz → 85kHz). In the absence of synchronisation signal the control voltage is equal to 1.6V typ. and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhas to be always higher than the free frequency and a margin has to be taken. As an example for a synchro range from 30kHz to 85kHz, the suggested free frequency is 27kHz. Figure 9 PLL1F 12 9105-27.EPS The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A ”CRC” filter is generally used (see Figure 9). PLL1 is inhibited by applying a high level on Pin 14 (PLLinhib) which is a TTL compatible input. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V (see Figure 10). The control voltage of the VCO is typically comprised between 1.6V and 6V (see Figure 10). The theoreticalfrequencyrange of this VCO is in the ratio 1 → 3.75, but due to spread and thermal drift of external components and the circuit itself, the effecFigure 10 : Details of VCO I0 6.4V 2 RS FLIP FLOP I0 Loop Filter 12 4 I0 1.6V 2 11 (1.6V < V12 < 6V) 10 C0 9105-28.EPS R0 6.4V 1.6V 0 0.75T T 15/32 TDA9105 OPERATING DESCRIPTION (continued) The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage adjustable between 2.4V and 4V (by Pin 15). So a ±45°phase adjustment is possible (see Figure 11). Figure 11 : PLL1 Timing Diagram H Osc Sawtooth 0.75T 0.25T 6.4V 2.4V<Vb<4V Vb 1.6V Phase REF1 Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS . A ± T/8 phase adjustment is possible. The two VCO threshold can be filtered by connecting capacitor on Pins 8-9. The TDA9103 also includes a LOCK/UNLOCK identification block which senses in real-time 9105-29.EPS H Synchro whether the PLL is locked on the incoming horizontal sync signal or not. The resulting information is available on HLOCKOUT output (Pin 2). The block diagram of the LOCK/UNLOCK function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drive the charge pump). When the PLL is locked, on point A there is a very small negative pulse (100ns) at each horizontal cycle, so after R-C filter, there is a high level on Pin 13 which force HLOCKOUT to high level (provided that HLOCKOUT is pulled up to VCC). When the PLL is unlocked, the 100ns negative pulse on A becomes much larger and consequently the average level on Pin 13 will decrease. When it reaches 6.5V, point B goes to low level forcing HLOCKOUT output to ”0”. The status of Pin 13 is approximately the following : - Near 0V when there is no H-SYNC, - Between 0 and 4V with H-SYNC frequency different from VCO, - Between 4 and 8V when H-SYNC frequency = VCO frequency but not in phase, - Near to 8V when PLL is locked. It is important to notice that Pin 13 is not an output pin and must only be used for filtering purpose (see Figure 12). Figure 12 : LOCK/UNLOCK Block Diagram 2 16/32 NOR1 A 20kΩ H-Lock CAP 13 6.5V 220nF B HLOCKOUT 9105-30.EPS From Phase Comparator TDA9105 OPERATING DESCRIPTION (continued) PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO (see Figure 13). The phase comparator of PLL2 is followed by a charge pump with a ±0.5mA (typ.) output current. The flyback input is composed of an NPNtransistor. This input has to be current driven. The maximum recommanded input current is 2mA (see Figures 14 and 15). Figure 13 : PLL2 Timing Diagram H Osc Sawtooth 0.25T 0.75T 6.4V 4V 1.6V Figure 14 : Flyback Input Electrical Diagram Flyback Internally Shaped Flyback 400Ω Q1 HFLY 5 H Drive 9105-31.EPS Duty Cycle The duty cycle of H-drive is adjustable between 30% and 50%. 9105-32.EPS 20kΩ Ts GND 0V Figure 15 : Dual PLL Block Diagram PLL1INHIB Filter R0 C0 14 12 11 10 C Lockdet HLOCKOUT 2 13 LOCKDET High INPUT INTERFACE E2 Adjust Rapcyc 4 CHARGE PUMP COMP1 PLL INHIBITION Horizontal Adjust 15 Low Cap PHi2 3 PHASE ADJUST VCO OSC 3.2V 4V High RAP CYC CHARGE PUMP Low VA COMP2 EN FLYBACK 5 Flyback VB PWM LOGI PWM BUFFER 21 SortCOLL 20 SortEM 17/32 9105-33.AI Horizontal 17 Input TDA9105 OPERATING DESCRIPTION (continued) X-RAY PROTECTION : the activation of the X-ray protection is obtained by application of a high level on the X-ray input (>8V). Consequences of X-ray protection are : - Inhibition of H drive output, - Activation of composite blanking output. The reset of this protection is obtained by VCC switch off (see Figure 17). Figure 16 : Output stage simplified diagram, showing the two possibilities of connection 21 VCC H-DRIVE 20 VCC 21 H-DRIVE Outputs inhibition The application of a voltage lower than 1V (typ.) on Pin 4 (duty cycle adjust) inhibits the horizontal and vertical outputs. This is not memorised. 20 9105-34.EPS Output Section The H-drive signal is transmitted to the output through a shaping block ensuring a duty cycle adjustable from 30% to 50%. In order to ensure a reliable operation of the scanning power part, the output is inhibited in the following circumstances : - VCC too low, - Xray protection activated, - During the horizontal flyback, - Output voluntarily inhibited through Pin 4. The output stage is composed of a Darlington NPN bipolar transistor. Both the collector and the emitter are accessible (see Figure 16). The output Darlington is in off-state when the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltage drop of the output darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. Figure 17 : Safety Functions Block Diagram VCC Checking VCC REF XRAY Protection XRAY VCC off S R Q H OUTPUT INHIBITION Inhibition H-Duty cycle 1V V OUTPUT INHIBITION Flyback 0.7V LOGIC BLOCK V sawtooth retrace time H-fly 18/32 to 2ND PLL 9105-35.EPS V-fly Vsync COMPOSITE BLANKING TDA9105 OPERATING DESCRIPTION (continued) Moire Function Figure 18 : Moire Function Block Diagram H-S YNC Ck Q D Rs t Q 23 Monosta ble Ck D Q Q 9105-36.EPS V-SYNC Figure 19 : Moire Output Waveform EVEN FRAME H V MOIRE ODD FRAME H 9105-37.EPS V MOIRE Geometric Corrections The principle is represented in Figure 20. Starting from the vertical ramp, a parabola shaped is generatedfor E/Wcorrection, dynamic horizontal phase control correction, and vertical dynamic Focus correction. The core of the parabola generator is an analog multiplier. The output current of which is equal to : ∆I = k (VRAMP - VDCIN)2. Where VRAMP is the vertical ramp, typically comprised between 2 and 5V, VDCIN is a vertical DC input adjustable in the range 3.2V → 3.8V in order to generate a dissymmetric parabola if required (keystone adjustment). In order to keep good screen geometry for any end user preferences adjustment we implemented the possibility to have ”geometry tracking”. To enable the ”tracking” function, the VDCOUT must be connected to VDCIN. It is possible to inhibit VPOS tracking by applying a fixed DC voltage on the VDCIN Pin. This DC voltage in that case must be taken from the vertical reference and adjusted to 3.5V with an external bridge resistor. Due to large output stages voltage range (E/W, BALANCE, FOCUS), the combination of tracking function with maximum vertical amplitude max. or min. vertical position and maximum gain on the DC control inputs may leads to the output stages saturation. This must be avoided by limiting the output voltage by apropriate DC control voltages. 19/32 TDA9105 OPERATING DESCRIPTION (continued) Geometric Corrections (continued) Figure 20 : Geometric Corrections Principle VERT. DYN. FOCUS OUT ANALOG MULTIPLIER VERTICAL RAMP 2 EW AMP VDCIN EW OUT VDCIN KEYSTONE SIDEPIN AMP SIDE PIN BAL. OUT 9105-38.EPS VDCIN KEY BALANCE For E/Wpart and Dynamic Horizontal phase control part, a sawtooth shaped differential current in the following form is generated: ∆I’ = k’ (VRAMP -VDCIN). Then ∆I and ∆I’ are added together and converted into voltage. These two parabola are respectively available on Pin 37 and Pin 40 by the way of an emitter follower which has to be biased by an external resistor (10kΩ). They can be DC coupled with external circuitry. EW VOUT = 2.5V + K1’ (VRAMP - VDCIN) + K1 (VRAMP - VDCIN)2 K1 is adjustable by EW amp control (Pin 39) K1’ is adjustable by KEYST control (Pin 38) 20/32 Dyn. Hor. VOUT = 4V + K2’ (VRAMP - VDCIN) + K2 (VRAMP - VDCIN)2 Phase Control K2 is adjustable by SPB amp control (Pin 42) K2’ is adjustable by KEYBAL control (Pin 41) For vertical dynamic focus part, only a constant amplitude parabola is generated in the form : VOUT = 6V - 0.75 x (VAMP - VDCIN)2. The output connection is the same as the two other corrections (Pins 37-40). It is important to note that the parasitic parabola during the discharge of the vertical oscillator capacitor is suppressed. TDA9105 OPERATING DESCRIPTION (continued) VERTICAL PART Figure 21 : Vertical Part Block Diagram CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 27 25 OSC CAP DISCH. V_SYNC 34 SYNCHRO SAMPLING SAMP. CAP S CORRECTION OSCILLATOR 28 VS_AMP POLARITY 29 COR_C C CORRECTION Vlow Sawth. Disch. 30 VERT_OUT 31 VERT_AMP PARABOLA GENERATOR 37 EW_OUT 38 EW_CENT 39 EW_AMP 40 SPB_OUT 42 SPB_AMP 9105-39.EPS 41 SPB_CENT 1 V_FOCUS The vertical part generates a fixed amplitude ramp which can be affected by a S and C correction shape. Then, the amplitude of this ramp is adjusted to drive an external power stage. The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. It can be usedas voltage reference for any DC adjusment to keep a high accuracy to each adjustment. Its typical value is : V26 = VREF = 8V. The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, VL (VL = VREF/4) and VH (VH = 5/8 ⋅ VREF). 21/32 TDA9105 OPERATING DESCRIPTION (continued) VERTICAL PART (continued) Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. Typical free running frequency can be calculated by : −5 f0 (Hz) = 1.5 ⋅ 10 ⋅ 1 COSC (nF) A negative or positive TTL level pulse applied on Pin 34 (VSYNC) can synchronise the ramp in the frequency range [fmin, fmax]. This frequency range depends on the external capacitor connected on Pin 27. A capacitor in the range [150nF, 220nF] is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can be calculated by : fmax = 2.5 ⋅ f0 and fmin = 0.33 ⋅ f0 If S or C corrections are applied, these values are slighty affected. If an external synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than half a second: the highest voltage of the ramp on Pin 27 is sampled on the sampling capacitor connected on Pin 25 (VAGCCAP) at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Pin 36, Vfly is the vertical flyback input used to generate the composite blanking signal. If Vfly is not used, (VREF - 0.5), at minimum, must be connected to this input. DC Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally; their ampli- 22/32 tude are DC adjustable on Pin 28 (VSAMP) and Pin 29 (COR-C). S correction is non effective for VSAMP lower than VREF/4 and maximum for VSAMP = 3/4 ⋅ VREF. C correction is non effective for COR-C grounded and maximum for : COR-C = VREF/4 or COR-C = 3/4 ⋅ VREF. Endly, the amplitude of this S and C corrected ramp can be adjusted by the voltage applied on Pin 31 (VAMP). The adjusted ramp is available on Pin 30 (VOUT) to drive an external power stage. The gain of this stage is typically ±30% when voltage applied on Pin 31 is in the range VREF/4 to 3/4 ⋅ VREF. The DC value of this ramp is kept constant in the frequency range , for any correction applied on it. Its typical value is : VDCOUT = VMID = 7/16 ⋅ VREF . A DC voltage is available on Pin 32 (VDCOUT). It is driven by the voltage applied on Pin 33 (VPOS) For a voltage control range between VREF/4 and 3/4 ⋅ VREF, the voltage available on Pin 32 is : VDCOUT = 7/16 ⋅ VREF ± 300mV. So, the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. Basic Equations In first approximation, the amplitude of the ramp on Pin 30 (VOUT) is : VOUT - VMID = (VCAP - VMID) [1 + 0.16 ⋅ (VAMP - VREF/2)] with VMID = 7/16 ⋅ VREF ; typically 3.5V VMID is the middle value of the ramp on Pin 27 VCAP = V27 , ramp with fixed amplitude. On Pin 32 (VDCOUT), the voltage (in volts) is calculated by : VDCOUT =VMID + 0.16 ⋅ (VPOS - VREF/2). VPOS is the voltage applied on Pin 33. The current available on Pin 27 (when VSAMP = VREF /4) is : IOSC = 3/8 ⋅ VREF ⋅ COSC ⋅ f COSC : capacitor connected on Pin 27 f synchronisation frequency The recommanded capacitor value on Pin 25 (VAGC) is 470nF. Its ensures a good stability of the internal closed loop. TDA9105 INTERNAL SCHEMATICS Figure 22 Figure 26 Href 9105-44.EPS 5 Pins 1-37-40 1mA max Figure 27 9105-40.EPS V CC Figure 23 Pins V CC 2-22-23 9105-41.EPS N MOS 9105-45.EPS 10mA max. 7 Figure 28 Figure 24 Href 8 9105-42.EPS 9105-46.EPS 3 Figure 29 Figure 25 9 9105-47.EPS P MOS 9105-43.EPS 4 23/32 TDA9105 INTERNAL SCHEMATICS (continued) Figure 30 Figure 34 P MOS 10 9105-52.EPS 9105-48.EPS 14 Figure 31 Figure 35 9105-49.EPS 11 Figure 32 15 P MOS P MOS 9105-53.EPS N MOS Figure 36 9105-50.EPS 12 16 Figure 33 24/32 9105-54.EPS N MOS 9105-51.EPS 13 TDA9105 INTERNAL SCHEMATICS (continued) Figure 37 Figure 39 P MOS P MOS 25 N P 17 9105-57.EPS N 9105-55.EPS P Figure 40 Figure 38 V CC 21 20 9105-58.EPS 9105-56.EPS 20mA max. 26 Figure 41 V REF V REF V CC V REF N P N MOS 9105-59.EPS 27 25/32 TDA9105 INTERNAL SCHEMATICS (continued) Figure 42 Figure 46 VCC VREF 32 9105-60.EPS 9105-64.EPS 28 Figure 47 VREF Figure 43 29 VREF N MOS 9105-61.EPS 33 9105-65.EPS Figure 44 VCC Figure 48 VREF 9105-62.EPS 34 9105-66.EPS 30 Figure 49 Figure 45 VREF 31 26/32 9105-67.EPS 9105-63.EPS 35 TDA9105 INTERNAL SCHEMATICS (continued) Figure 50 Figure 51 VREF VREF Pins 38-39 41-42 36 9105-69.EPS 9105-68.EPS P MOS 27/32 HOUT HFLY VSYNC BLK J19 1 1 J3 HSYNC XRAY IN 9105-70.EPS J5 TP6 J2 TP2 J18 HFLY 1 J25 DYN 1 FOCUS CON1 R74 10k Ω TP5 TP7 TP4 C8 100µF +12V TP3 10kΩ R33 10kΩ R71 SW1 on 5.6kΩ R91 + S1 off + C9 100nF C36 1 µF + HDF R2 120kΩ C52 C34 1µF R84 47kΩ R5 120kΩ R3 10kΩ R1 3.9k Ω 1N4148 D4 R90 1Ω TP14 R88 10kΩ R83 1kΩ R6 10k Ω C6 220nF C3 10nF R7 3.9k Ω C48 R32 6.49kΩ 1% 1nF 24 23 22 20 21 25 26 27 28 29 30 31 32 33 34 35 19 18 17 16 15 14 13 12 11 10 9 8 36 37 6 7 38 5 39 4 41 40 T D A 9 1 0 5 IC1 TP13 42 PINCSH 3 2 1 C39 1µF R10 3.9k Ω 47nF C50 680pF 5% HREF C45 220pF C1 22nF TP12 R31 1.8kΩ + + R87 10kΩ 4.7kΩ R89 R80 2.7kΩ C7 4.7µF + R9 10k Ω C35 1µF R11 120kΩ SBPAMP C2 C30 47µF 47nF C51 15nF C54 +12V 330kΩ 15kΩ + R94 HREF R8 120kΩ R93 R4 3.9k Ω C29 100nF HSHIFT R12 10kΩ KEYBAL R17 120kΩ 0/5V to 2/6V INTERFACE C4 470nF C5 C37 1µF + 100nF VSHIFT R13 3.9k Ω R15 10kΩ R20 120kΩ + C28 47µF V REF C38 1µF + 150nF C27 TP1 KEYST R14 120kΩ +12V R73 10k Ω R16 3.9k Ω R18 10k Ω J3b R21 10kΩ R23 120kΩ R22 3.9k Ω R19 3.9k Ω C42 1µF + C43 1µF + VSIZE 1% 33.2kΩ R82 1% 43.2kΩ R81 VREF CCOR C40 1µF + R25 3.9k Ω 1 2 3 4 5 6 7 R27 10kΩ R29 120kΩ J2b R24 10kΩ R26 120kΩ 1 2 3 4 C41 1µF + VREF SCOR R28 3.9k Ω J1b R30 10kΩ 28/32 1 2 3 4 C53 1µF + R35 C11 470pF C10 100nF 1 7 2 IC2 TDA8172 5 3 C14 470µF 4 6 D1 1N4004 Q1 BC557 Q10 BC547 R44 10Ω R38 5.6k Ω -12V +12V R85 15kΩ 1kΩ R54 470Ω BC557 Q3 R53 1kΩ E/W POWER STAGE R51 6.2kΩ 1kΩ R92 R52 27kΩ +12V R86 4.7kΩ L1 10µH +12V VERTICAL DEFLECTION STAGE R36 12kΩ 5.6kΩ R37 R70 12kΩ D5 1N4148 27kΩ R75 HSIZE + + 39kΩ 22kΩ R45 Q2 STD5N20 + 2.2Ω 1W C44 220pF C19 1nF -12V HDRIVE R47b 33Ω 3W V YOKE 3 1 2 J22 3 1 2 J23 1 J21 E/W 1 J24 HORIZONTAL DRIVER STAGE G 5576-00 T1 1/2W 1Ω R40 220Ω 1/2W R39 TP15 TP11 R46 560Ω R59 Q9 TIP122 C32 100nF R47a 47Ω 3W C31 100nF C15 220nF R41 1.5Ω C20 100µF 63V R57 270kΩ R56 + C12 35V 100µF C13 470µF BC557 Q4 R55 270kΩ TDA9105 APPLICATION DIAGRAMS Figure 52 : Demonstration Board +12V 9105-71.EPS Pc1 47kΩ Q HOUT Cc1 47pF +12V Q Q Pc6 47kΩ Jc2 KEYBAL SBPAMP 1 2 3 4 HDF HSHIFT Pc4 47kΩ Jc1 HFLY Cc4 10µF RC CX T T Icc1B 14528 Pc5 47kΩ 1 2 3 4 Cc5 100nF Icc1A 14528 Cc2 47pF R R C C X T T Q Pc2 47kΩ Pc3 47kΩ +12V Pc7 47kΩ PINCSH Pc10 47kΩ Pc11 47kΩ Jc3 Pc12 47kΩ SCOR CCOR 1 2 3 4 5 6 7 KEYST VSHIFT VSIZE 1 Jc4 CON1 1 Jc26 Cc4 10µF HSIZE +5V TDA9105 APPLICATION DIAGRAMS Figure 53 : Control Board 29/32 Pc13 4.7kΩ Pc9 47kΩ Pc8 47kΩ TDA9105 APPLICATION DIAGRAMS 9105-72.TIF Figure 54 : PCB Layout 30/32 TDA9105 APPLICATION DIAGRAMS 9105-73.EPS Figure 55 : Components Layout 31/32 TDA9105 PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 e3 21 e2 SDIP42 Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70 2.54 Millimeters Typ. 3.81 0.46 1.02 0.25 38.10 13.72 1.778 15.24 3.30 Max. 5.08 4.57 0.56 1.14 0.38 38.35 16.00 14.48 18.54 1.52 3.56 Min. 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50 0.10 Inches Typ. 0.150 0.0181 0.040 0.0098 1.5 0.540 0.070 0.60 0.130 Max. 0.200 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570 0.730 0.060 0.140 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 32/32 SDIP42.TBL 1 PMSDIP42.EPS Gage Plane