SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
•
•
•
•
•
Low rDS(on) . . . 0.4 Ω Typ
High-Voltage Output . . . 60 V
Pulsed Current . . . 3 A Per Channel
Fast Commutation Speed
Direct Logic-Level Interface
DW PACKAGE
(TOP VIEW)
GND
SOURCE4/GND
GATE4
NC
DRAIN4
SOURCE3
DRAIN3
GATE3
NC
NC
description
The TPIC5424L is a monolithic logic-level power
DMOS array that consists of four electrically
isolated N-channel enhancement-mode DMOS
transistors, two of which are configured with a
common source.
The TPIC5424L is offered in a 16-pin thermally
enhanced dual-in-line (NE) package and a 20-pin
wide-body surface-mount (DW) package. The
TPIC5424L is characterized for operation over the
case temperature range of − 40°C to 125°C.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SOURCE2/GND
GATE2
NC
NC
DRAIN2
SOURCE1
DRAIN1
GATE1
NC
NC
NC − No internal connection
NE PACKAGE
(TOP VIEW)
DRAIN2
SOURCE2/GND
GATE2
GND
GND
GATE4
SOURCE4/GND
DRAIN4
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SOURCE1
DRAIN1
GATE1
GND
GND
GATE3
DRAIN3
SOURCE3
schematic
DRAIN1
DRAIN3
Q1
Q3
Z1
GATE1
D1
D2
Z3
GATE3
SOURCE3
SOURCE1
DRAIN4
DRAIN2
Q2
Q4
GATE2
Z2
Z4
GATE4
GND, SOURCE2, SOURCE4
Copyright 1994, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
1
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q2, Q4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-to-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A
Single-pulse avalanche energy, EAS, TC = 25°C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 mJ
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%.
DISSIPATION RATING TABLE
2
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
DW
NE
1389 mW
2075 mW
11.1 mW/
mW/°C
C
16.6 mW/°C
279 mW
415 mW
•
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•
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID = 250 µA,
ID = 1 mA,
See Figure 5
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)
Reverse drain-to-GND breakdown voltage (across
D1, D2)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 1 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1 A,
VGS = 0 (Z1, Z2, Z3, Z4),
See Notes 2 and 3 and Figure 12
VF
Forward on-state voltage, GND-to-drain
ID = 1 A (D1, D2),
See Notes 2 and 3
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short circuited to
source
VGS = 5 V,
IGSSR
Reverse gate current, drain short circuited to
source
Ilkg
rDS(on)
VGS = 0
VDS = VGS,
MIN
TYP
MAX
60
1.5
V
1.85
2.2
100
VGS = 5 V,
UNIT
V
V
0.4
0.48
V
1
1.2
V
4.6
V
0.05
1
0.5
10
VDS = 0
10
100
nA
VSG = 5 V,
VDS = 0
10
100
nA
VDGND = 48 V
(D1, D2)
TC = 25°C
TC = 125°C
0.05
1
Leakage current, drain-to-GND
0.5
10
TC = 25°C
0.4
0.48
Static drain-to-source on-state resistance
VGS = 5 V,
ID = 1 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.65
0.68
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse-transfer capacitance,
common source
VDS = 25 V,
f = 1 MHz,
µA
A
Ω
VDS = 15 V,
ID = 0.5 A,
See Notes 2 and 3 and Figure 9
gfs
A
µA
1.25
VGS = 0,
See Figure 11
1.39
S
220
275
120
150
100
125
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
TEST CONDITIONS
Reverse-recovery time
IS =0.5 A,
VGS = 0,
See Figures 1 and 14
QRR
VDS = 48 V,
di/dt = 100 A/µs,
Total diode charge
•
MIN
55
Z2 and Z4
150
D1 and D2
200
Z1 and Z3
0.06
Z2 and Z4
0.3
D1 and D2
0.7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
TYP
Z1 and Z3
MAX
UNIT
ns
µC
3
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
34
68
40
82
21
42
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Fall time
25
50
Qg
Total gate charge
3.9
5
0.55
0.8
2.5
3.6
Turn-off delay time
RL = 25 Ω,
See Figure 2
VDD = 25 V,
tdis = 10 ns,
VDS = 48 V,
See Figure 3
ID = 1 A,
ten = 10 ns,
VGS = 10 V,
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
Internal drain inductance
5
LS
Internal source inductance
5
Rg
Internal gate resistance
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
RθJA
Junction-to-ambient thermal resistance
(see Note 4)
RθJP
Junction-to-pin thermal resistance
MIN
TYP
DW package
90
NE package
60
All outputs with equal power
DW package
NE package
25
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink
PARAMETER MEASUREMENT INFORMATION
1.5
VDS = 48 V
VGS = 0
TJ = 25°C
Z1 and Z3
I S − Source-to-Drain Diode Current − A
1
Reverse di/dt = 100 A/µs
0.5
0
25% of IRM†
− 0.5
Shaded Area = QRR
−1
− 1.5
−2
IRM†
− 2.5
0
50
trr(SD)
100
150
200
250
300
350
400
450
500
t − Time − ns
† IRM = maximum recovery current
NOTE A. The above waveform is representative of Z2, Z4, D1, and D2 in
shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
4
•
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•
30
MAX
UNIT
°C/W
°C/W
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
tdis
ten
RL
Pulse Generator
5V
VDS
VGS
0
VGS
Rgen
50 Ω
tr
tf
CL 30 pF
(see Note A)
50 Ω
td(off)
td(on)
DUT
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
12-V
Battery
0.2 µF
50 kΩ
5V
0.3 µF
Qgs(th)
VDD
VDS
0
Qg
Same Type
as DUT
Qgd
VGS
DUT
IG = 1 µA
Gate Voltage
IG CurrentSampling Resistor
ID CurrentSampling Resistor
Time
WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
•
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•
5
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
tav
tw
23.3 mH
Pulse Generator
(see Note A)
5V
VGS
VDS
ID
0
IAS
(see Note B)
VGS
50 Ω
ID
DUT
0
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 3 A.
I
V
t av
AS
(BR)DSX
Energy test level is defined as E
+
+ 180 mJ.
AS
2
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2.5
0.8
VDS = VGS
ID = 1 A
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
On-State Resistance − Ω
0.7
r DS(on) − Static Drain-to-Source
VGS(th) − Gate-to-Source Threshold Voltage − V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.6
VGS = 4.5 V
0.5
VGS = 5 V
0.4
0.3
0.2
0.1
0
− 40 − 20
0
20
40
60
0
− 40 − 20
80 100 120 140 160
Figure 5
6
0
20
40
60
80 100 120 140 160
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 6
•
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•
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
1
0.9
0.8
0.7
3
TJ = 25°C
0.6
0.5
VGS = 4.5 V
0.4
VGS = 5 V
0.3
0.2
2
1
VGS = 3 V
0.1
0.10
1
ID − Drain Current − A
0
10
0
2
4
6
8 10 12 14 16 18
VDS − Drain-to-Source Voltage − V
Figure 7
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
30
Total Number of
Units = 2888
VDS = 15 V
ID = 0.5 A
TJ = 25°C
I D − Drain Current − A
25
20
Figure 8
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
20
15
10
2
TJ = − 40°C
1
TJ = 150°C
5
TJ = 25°C
TJ = 125°C
0
1.455
1.443
1.430
1.418
1.405
1.393
1.380
1.368
1.355
0
1.343
TJ = 75°C
1.330
Percentage of Units − %
nVGS = 0.2 V
TJ = 25°C
VGS = 4 V
I D − Drain Current − A
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
0
1
2
3
4
5
6
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
Figure 10
•
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•
7
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
500
3
450
I SD − Source-to-Drain Diode Current − A
f = 1 MHz
VGS = 0
TJ = 25°C
Capacitance − pF
400
350
300
Ciss
250
200
Coss
150
100
Crss
50
VGS = 0
2
1
0.6
0.4
TJ = 125°C
0.1
0
10
20
30
40
0.1
VDS − Drain-to-Source Voltage − V
1
VSD − Source-to-Drain Voltage − V
Figure 11
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
4
3
30
VDD = 48 V
20
2
1
10
0
0
0.5
1
1.5
2
2.5
3
3.5
150
Z2 and Z4
125
100
75
50
Z1 and Z3
25
VDD = 20 V
0
VDS = 48 V
VGS = 0
IS = 0.5 A
TJ = 25°C
See Figure 1
175
trr − Reverse-Recovery Time − ns
5
VDD = 30 V
40
200
6
VDD = 20 V
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
ID = 0.5 A
TJ = 25°C
See Figure 3
4
4.5
0
5
0
100
Qg − Gate Charge − nC
Figure 13
8
10
Figure 12
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
50
TJ = 25°C
0.2
TJ = 75°C
0
60
TJ = − 40°C
TJ = 150°C
200
300
400
Reverse di/dt − A/µs
Figure 14
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•
500
600
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
MAXIMUM PEAK-AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
5
See Figure 4
I AS − Maximum Peak-Avalanche current − A
I D − Maximum Drain Current − A
TC = 25°C
1 µs†
10 ms†
1 ms†
500 µs†
1
DW Pkg
NE Pkg
DC Conditions
0.1
0.1
1
10
VDS − Drain-to-Source Voltage − V
4
3
TC = 25°C
TC = 125°C
2
1
0.01
100
0.1
1
10
100
tav − Time Duration of Avalanche − ms
† Less than 2% duty cycle
Figure 16
Figure 15
•
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•
9
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
NE PACKAGE†
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
R θ JA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.1
0.01
tw − Pulse Duration − s
† Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17
10
•
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•
1
10
SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
DW PACKAGE†
NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
R θ JA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.1
0.01
1
10
tw − Pulse Duration − s
† Device mounted on FR4 printed-circuit board with no heat sink
NOTES: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 18
•
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•
11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPIC5424LDW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
TPIC5424LNE
OBSOLETE
PDIP
NE
16
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI003 – OCTOBER 1994
NE (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
20 PIN SHOWN
0.070 (1,78) MAX
11
20
PINS **
DIM
A
C
1
20
0.914 (23,22)
MIN
MAX
B
16
0.780 (19,80)
0.975 (24,77)
MIN
0.930 (23,62)
MAX
1.000 (25,40)
10
C
MIN
0.240 (6,10)
0.260 (6,61)
MAX
0.260 (6,60)
0.280 (7,11)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25) M
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
B
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25) M
0°– 15°
0.010 (0,25) NOM
4040054 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (16 pin only)
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