TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 1.2V - 8V, 3A PFET Load Switch with Adjustable Slew Rate, Fast Transient Isolation and Hysteretic Control Check for Samples: TPS27082L FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • • Low ON Resistance, High Current PFET – RDS(ON) = 32mΩ (Typical) at VGS = –4.5V – RDS(ON) = 44mΩ (Typical) at VGS = –3.0V – RDS(ON) = 85mΩ (Typical) at VGS = –1.8V – RDS(ON) = 97mΩ (Typical) at VGS = –1.5V – RDS(ON) = 155mΩ (Typical) at VGS = –1.2V Adjustable Turn-ON and Turn-OFF Slew Rate – 10µsec Default Minimum Output Rise Time at VIN=5V Adjustable Turn-ON and Turn-OFF Slew Rate Supports a Wide Range of VIN 1.2V up to 8V Excellent OFF Isolation Even Under Fast Input Transients 1.0V up to 8V NMOS Control Logic Interface With Adjustable Hystersis Fully Protected Against ESD (All Pins) – HBM 2kV, CDM 500V Very Low ON-state Quiescent Current (Down to 1.2µA) Very Low OFF-state Leakage Current (Typ 100nA) Available in 2.9mm x 1.6mm x 0.75mm SOT-23 (DDC) Package High Side Load Switch Inrush-current Control Power Sequencing and Control Stand-by Power Isolation Portable Power Switch DESCRIPTION The TPS27082L IC is a high side load switch that integrates a Power PFET and a control circuit in a tiny TSOT-23 package. TPS27082L requires very low ON-state quiescent current and offers very low OFFstate leakage thus optimizing system power efficiency. TPS27082L ON/OFF logic interface features hysteresis, thus providing a robust logic interface even under very noisy operating conditions. TPS27082L ON/OFF interface supports direct interfacing to low voltage GPIOs down to 1V. The TPS27082L level shifts ON/OFF logic signal to VIN levels without requiring an external level shifter. TPS27082L features a novel OFF isolation circuit that prevents PMOS from turning ON in applications that may have fast transients, at the VIN pin when the load switch is in the OFF-state. TPS27082L VIN TPS27082LDDC (TOP VIEW) VOUT Q1 (4) R1 (2, 3) ESD 1 GND ESD C1 R1/C1 R1/C1 6 2 VOUT ON/OFF 5 3 VOUT VIN 4 (6) 2.9mm x 1.6mm x 0.75mm TSOT-23(DDC) ESD TPS27082L Package (DDC) Q2 ON/OFF Logic & Control (5) Component Table (Typical Application) ESD RS=12.5kΩ (1) GND Component Description R1 Level Shift Pull-up Resistor C1 Optional (1) Simplified Block & Application Diagram 1 (1) Required for load inrush current (slew rate) control. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) (1) TJ PART NUMBER –40°C to 125°C TPS27082LDDCR PACKAGE 6-Pin Thin SOT TOP-SIDE MARKING Reel of 3000 BU_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Contact factory for details and availability for PREVIEW devices, minimum order quantity may apply. (2) ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Specified at TJ = –40°C to 125°C (unless otherwise noted) VALUE UNIT MIN MAX VINmax, VOUTmax VIN, VOUT pin maximum voltage with respect to GND pin –0.1 8 V VON/OFF ON/OFF control voltage –0.3 8 V Max continuous drain current of Q1 IQ1-ON 3 Max pulsed drain current of Q1 (4) 9.5 Max power dissipation at TA = 25°C, TJ = 150°C (4) PD All pins 1190 mW ESD Rating – HBM 2000 V ESD Rating – CDM 500 V 125 (5) °C 150 °C 150 °C TA Operating free-air ambient temperature range TJ-max Operating virtual junction temperature Tstg Storage temperature range (1) (2) (3) (4) (5) 6 Pin-TSOT, θJA =105°C/W A -40 –65 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operating at the absolute TJ-max of 150°C can affect reliability – for higher reliability it is recommended to ensure TJ < 125°C Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance. Pulse Width < 300µs, Duty Cycle < 2% TJ-max limits and other related conditions apply. Refer to SOA charts, Figure 8 through Figure 13 DISSIPATION RATINGS (1) (2) (3) BOARD PACKAGE θJC θJA (4) TA < 25°C TA = 70°C TA = 85°C TA = 105°C DERATING FACTOR ABOVE TA = 25°C High-K (JEDEC 51-7) 6-Pin TSOT (DDC) 43°C/W 105°C/W 1190 mW 760 mW 619 mW 428 mW 9.55 mW/°C (1) (2) (3) (4) 2 Maximum dissipation values for retaining a maximum allowable device junction temperature of 150°C Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance Package thermal data based on a 76x114x1.6mm, 4-layer board with 2-oz Copper on outer layers Operating at the absolute TJ-max of 150°C can affect reliability; TJ ≤ 125°C is recommended Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS Full temperature range spans TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS FULL TEMP RANGE (1) TA =TJ = 25°C MIN TYP MAX MIN UNIT MAX OFF CHARACTERISTICS BVIN VON/OFF = 0 V, VGS(Q1) = 0 V, ID(Q1) = 250 µA VIN breakdown voltage VIN pin total forward leakage current (2) IFIN –8 –8 V VIN = 8 V, ON/OFF = 0 V, RL = 2.5 Ω 0.15 30 VIN = 5 V, ON/OFF = 0 V, RL = 2.5 Ω 0.04 12 µA ON CHARACTERISTICS (3) VT+ (VIH) Positive going ON/OFF threshold voltage (4) VT– (VIL) Negative going ON/OFF threshold voltage (4) ∆VT (VT+–VT–) ON/OFF input logic hysteresis (4) RDSQ1(ON) RGNDON Q1 Channel ON resistance (5) R1/C1 pin to GND pin resistance when Q2 is ON Q1 DRAIN-SOURCE DIODE PARAMETERS VIN = 5.0 V, R1 = 125 kΩ (1), RL = 2.5 Ω 1.0 VIN = 5.0 V, R1 = 1 MΩ, RL = 2.5 Ω 1.0 VIN = 5.0 V, ID(Q1) < 175 µA, R1 =125 kΩ (1) 400 VIN = 5.0 V, ID(Q1) < 175 µA, R1 = 1 MΩ 270 VIN = 5.0 V, R1 = 125 kΩ (1) 600 VIN = 5.0 V, R1 = 1 MΩ 730 mV VGSQ1 = –4.5V, ID = 3.0 A 32 52 64 VGS1Q1 = -3.0V, ID =2 .5 A 44 66 84 VGS1Q1 = -2.5V, ID = 2.5 A 50 76 92 VGSQ1 = -1.8V, ID = 2.0 A 82 113 147 VGSQ1 = -1.5V, ID = 1.0 A 97 150 173 VGSQ1 = -1.2V, ID = 0.50 A 155 250 260 VON/OFF = 1.8 V 12.5 14.2 14.5 V mΩ kΩ (1) (3) (6) IFSD Source-drain diode peak forward current VFSD(Q1) = 0.8V, VON/OFF = 0 V VFSD Source-drain diode forward voltage IFSD(Q1) = -0.6A, VON/OFF = 0 V (1) (2) (3) (4) (5) (6) V 1.0 A 1.0 V Specified by design only Refer to IFVIN plots for more information Pulse width < 300µs, Duty cycle < 2% Refer to charts for more information on VT+/VT– thresholds Refer to SOA charts for operating current information Not rated for continuous current operation Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 3 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com TPS27082LDDC (TOP VIEW) 1 GND R1/C1 6 2 VOUT ON/OFF 5 3 VOUT VIN 4 2.9mm x 1.6mm x 0.75mm TSOT-23(DDC) TPS27082LD and TPS27082LDRV PINOUT PIN FUNCTIONS PIN NAME NO. GND 1 VOUT 2, 3 DESCRIPTION Connect to the system GND Drain Terminal of Power PFET (Q1) – If required, connect a slew control capacitor between pins VOUT and R1/C VIN 4 Source Terminal of Power PFET (Q1) – connect a pull-up resistor between the pins VIN and R1/C1 ON/OFF 5 Active high enable – when driven with a high impedance driver, connect an external pull down resistor to GND R1/C1 6 Gate Terminal of Power PFET (Q1) TPS27082L VIN VOUT Q1 (4) R1 (2, 3) ESD ESD C1 R1/C1 (6) ESD Q2 ON/OFF Logic & Control (5) ESD RS=12.5kΩ (1) GND Typical Application Diagram 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 APPLICATION INFORMATION The TPS27082L IC is a high side load switch that integrates a Power PFET and its control circuit in a tiny TSOT23 package. TPS27082L supports up to 8V supply input and up to 3A of load current. The TPS27082L can be used in a variety of applications. Figure 1 shows a general application of TPS27082L to control capacitive load inrush current. TPS27082L VIN VOUT Q1 (2, 3) (4) R1 ESD ESD C1 R1/C1 (6) ESD Q2 ON/OFF Logic & Control (5) ESD RS=12.5kΩ (1) GND Figure 1. Typical Application Diagram Configuring Q1 ON resistance VGS-Q1, Gate-Source voltage, of PMOS transistor Q1 sets its ON resistance RDSQ1(ON). Connecting a high value pull up resistor R1 maximizes ON state VGS-Q1 and thus minimizes the VIN to VOUT voltage drop. Use the following equation for calculating VGS-Q1: R1 VGSQ1 = - VIN ´ V R1 + 12.5 kΩ (1) e.g. R1= 125kΩ, VIN = 5V sets VGSQ1 = -4.5V NOTE It is recommended to keep R1 ≥ 125 kΩ. Higher value resistor R1 reduces ON-state quiescent current, increases turn-OFF delay, while reducing ON/OFF negative going threshold voltage VT–. Configuring Turn-ON slew rate Switching a large capacitive load CL instantaneously results in a load inrush current given by the following equation: VOUTfinal – VOUTinitial dv Iinrush = Cload ´ = Cload ´ dt Vout Slew Rate (2) An uncontrolled fast rising ON/OFF logic input may result in a high slew rate (dv/dt)at the output thus leading to a higher load inrush current. To control the inrush current connect a capacitor C1 as shown in the Figure 1. Use the following approximate empirical equation to configure the TPS27082L slew rate to a specific value. trise = 50 ´ 103 ´ C1 sec VIN2/3 (3) Where trise is the time delta starting from the ON/OFF signal’s rising edge to charge up the load capacitor CL from 10% to 90% of VIN voltage. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 5 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com Table 1. Capacitor C1 Selection for Standard Output Rise Time C1 (F) R1 = 125 kΩ trise (µSec) (Typical) VIN=7V VIN=5V VIN=3.3V VIN=1.8V 5 0 0 0 0 0 50 3.46n 2.77n 2.10n 1.41n 1.08n 100 6.91n 5.54n 4.21n 2.82n 2.16n 250 17.3n 13.8n 10.5n 7.05n 5.40n 470 32.5n 26.0n 19.8n 13.3n 10.1n 1000 69.1n 55.4n 42.1n 28.2n 21.6n VIN=1.2V Note: The trise equation and the capacitor C1 values recommended in the table above are under typical conditions and are accurate to within ±20%. Ensure R1 > 125kΩ; and select a closest standard valued capacitor C1. Configuring Turn-OFF delay TPS27082L PMOS turn-OFF delay from the falling edge of ON/OFF logic signal depends upon the component values of resistor R1 and capacitor C1. Lower values of resistor R1 ensures quicker turn-OFF. toff > (R1 × C1 sec) (4) OFF Isolation Under VIN Transients TPS27082L architecture helps isolate fast transients at the VIN when PFET is in the OFF state. Best transient isolation is achieved when an external capacitor C1 is not connected across VOUT and R1/C1 pins. When a capacitor C1 is present the VIN to VOUT coupling is capacitive and is set by the C1 to CL capacitance ratio. TPS27082L architecture prevents direct conduction through PFET. Low Voltage ON/OFF Interface To turn ON the load switch apply a voltage > 1.0V at the ON/OFF pin. The TPS27082L features hysteresis at its ON/OFF input. The turn-ON and turn-OFF thresholds are dependent upon the value of resistor R1. Refer to the ELECTRICAL CHARACTERISTICS Table and Figure 14 for details on the positive and negative going ON/OFF thresholds. In applications where ON/OFF signal is not available connect ON/OFF pin to the VIN pin. The TPS27082L will turn ON and OFF in sync with the input supply connected to VIN. On-chip Power Dissipation Use below approximate equation to calculate TPS27082L’s on-chip power dissipation PD: PD = IDQ12 × RDSQ1(ON) (5) Where, IDQ1 is the DC current flowing through the transistor Q1. Refer to the ELECTRICAL CHARACTERISTICS Table and the Figure 16 through Figure 22 to estimate RDSQ1(ON) for various values of VGSQ1. Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid transistors Q1 going into saturation region set VGS > VDS+1.0V. E.g. VGS > 1.5V and VDS < 200mV ensures switching region. Thermal Reliability For higher reliability it is recommended to limit TPS27082L IC’s die junction temperature to less than 125°C. The IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to calculate maximum on-chip power dissipation to restrict the die junction temperature target to safe limits: PD(MAX) = (TJ(MAX) - TA ) qJA (6) Where TJ(MAX) is the target maximum junction temperature, TA is the operating ambient temperature, and θJA is the package junction to ambient thermal resistance. 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 Improving Package Thermal Performance The package θJA value under standard conditions on a High-K board is available in the Dissipation Rating Table. θJA value depends upon the PC board layout. An external heat sink and/or a cooling mechanism like a cold air fan can help reduce θJA and thus improving device thermal capability. Refer to TI’s design support web page at www.ti.com/thermal for a general guidance on improving device thermal performance. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 7 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com APPLICATION EXAMPLES TFT LCD Module Inrush Current Control VOUT VIN 3-5V Input (2, 3) (4) VIN Q1 CIN COUT R1 (6) TFT LCD Module C1 R1/C1 (5) GPIO Q2 ON/OFF R2 (1) R2 Figure 2. Inrush Current Control Using TPS27082L LCD panels require inrush current control to prevent permanent system damages during turn-ON and turn-OFF events. Standby Power Isolation VDD VOUT VIN Up to 8V Input (2, 3) (4) VDD Q1 CIN COUT R1 (6) R1/C1 Always ON Modules Standby Module (5) GPIO Q2 ON/OFF (1) R2 Figure 3. Standby Power Generation Using TPS27082L Many applications have some always ON modules to support various core functions. However, some modules are selectively powered ON or OFF to save power and multiplexing of various on board resources. Such modules that are selectively turned ON or OFF require standby power generation. In such applications TPS27082L requires only a single pull-up resistor. In this configuration the VOUT voltage rise time is approximately 250ns when VIN = 5V. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 Boost Regulator with True Shutdown VOUT VIN 1.8 - 8V Input (2, 3) (4) CIN SW VIN Q1 CIN R1 (6) R1/C1 FB (5) GPIO Q2 ON/OFF R2 (1) SHDN Boost Reg Figure 4. True Shutdown Using TPS27082L The most common boost regulator topology provides a current leakage path through inductor and diode into the feedback resistor even when the regulator is shut down. Adding a TPS27082L in the input side power path prevents this leakage current and thus providing a true shutdown. Single Module Multiple Power Supply Sequencing SW Supply (DC-DC) CVDD VOUT1 VIN (2, 3) (4) LDO Q1 CIN CVDDIO R1 (6) VDDIO DVDD VDD C1 R1/C1 (5) Q2 CPU/MCU/SOC ON/OFF R2 (1) R2 Figure 5. Power Sequencing Using TPS27082L, Example 1 Most modern SOCs and CPUs require multiple voltage inputs for its Analog, Digital cores and IO interfaces. These ICs require that these supplies be applied simultaneously or in a certain sequence. TPS27082L when configured, as shown in Figure 5, with the VOUT1 rise time adjusted appropriately through resistor R2 and capacitor C1, will delay the early arriving LDO output to match up with late arriving DC-DC output and thus achieving power sequencing. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 9 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com Multiple Modules Interdependent Power Supply Sequencing 1.2 - 8V Input VOUT2 VOUT1 VIN VDD2 Q1 VDD1 Q1 CIN (2, 3) (4) (2, 3) (4) COUT2 R3 COUT1 R1 (6) (6) C1 R1/C1 Module1 (CPU/MCU) R1/C1 (5) C2 Module2 (5) Q2 Q2 ON/OFF ON/OFF GPIO R2 (1) R2 (1) R4 R2 Figure 6. Power Sequencing Using TPS27082L, Example 2 For system integrity reasons a certain power sequencing may be required among various modules. As shown in Figure 6, Module 2 will power up only after Module 1 is powered up and the Module 1 GPIO output is enabled to turn ON Module 2. TPS27082L when used as shown in Figure 6 will not only sequence the Module 2 power, but also it will help prevent inrush current into the power path of Module 1 and 2. Multiple Modules Interdependent Supply Sequencing without a GPIO Input Up to 8V Input VOUT VIN (2, 3) (4) VDD1 Q1 CIN COUT1 R1 (6) C1 R1/C1 Module1 (5) Q2 ON/OFF R2 (1) R2 VOUT (2, 3) (4) VDD2 Q1 COUT2 R3 (6) C1 R1/C1 Module2 (5) Q2 ON/OFF R2 (1) R4 Figure 7. Power Sequencing using TPS27082L, Example 3 When a GPIO signal is not available connecting the ON/OFF pin of TPS27082 connected to Module 2 will power up Module 2 after Module 1, when resistor R4 and capacitor C1 are chosen appropriately. The two TPS27082L in this configuration will also control load inrush current. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 PFET Q1 Minimum Safe Operating Area (Refer to DISSIPATION RATINGS (1) (2) (3) for PC board details ) (1) (2) (3) Figure 8. Q1 SOA at VGS_Q1=-4.5V Figure 9. Q1 SOA at VGS_Q1=-3.0V Figure 10. Q1 SOA at VGS_Q1=-2.5V Figure 11. Q1 SOA at VGS_Q1=-1.8V Figure 12. Q1 SOA at VGS_Q1=-1.5V Figure 13. Q1 SOA at VGS_Q1=-1.2V Maximum dissipation values for retaining a maximum allowable device junction temperature of 150°C Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance Package thermal data based on a 76x114x1.6mm, 4-layer board with 2-oz Copper on outer layers Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 11 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com PFET Q1 Minimum Safe Operating Area (continued) (Refer to DISSIPATION RATINGS(1)(2)(3) for PC board details ) Figure 14. ON/OFF Positive and Negative Going Threshold Voltage Figure 15. VIN Pin Leakage Current 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L TPS27082L www.ti.com SLVSBR5 – DECEMBER 2012 Typical VIN to VOUT Voltage Drop Characteristic Plots Figure 16. Vdrop vs IL; VGS_Q1 = –1.2V Figure 17. Vdrop vs IL; VGS_Q1 = –1.8V Figure 18. Vdrop vs IL; VGS_Q1 = –2.5V Figure 19. Vdrop vs IL; VGS_Q1 = –3.3V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L 13 TPS27082L SLVSBR5 – DECEMBER 2012 www.ti.com Typical VIN to VOUT Voltage Drop Characteristic Plots (continued) Figure 20. Vdrop vs IL; VGS_Q1 = –4.5V Figure 21. Vdrop vs IL; VGS_Q1 = –5.5V Figure 22. Vdrop vs IL; VGS_Q1 = –7V 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS27082L PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) TPS27082LDDCR ACTIVE Package Type Package Pins Package Qty Drawing SOT DDC 6 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) CU SN MSL Peak Temp Samples (3) (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS27082LDDCR Package Package Pins Type Drawing SOT DDC 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 9.5 Pack Materials-Page 1 3.17 B0 (mm) K0 (mm) P1 (mm) 3.1 1.1 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS27082LDDCR SOT DDC 6 3000 180.0 180.0 30.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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