PHILIPS TZA3034

INTEGRATED CIRCUITS
DATA SHEET
TZA3034
SDH/SONET STM1/OC3
postamplifier
Product specification
Supersedes data of 1999 Mar 16
File under Integrated Circuits, IC19
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
FEATURES
APPLICATIONS
• Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
• Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high speed data networks
• Wideband operation from 1.0 kHz to 150 MHz typical
• Wideband RF gain block.
• Applicable in 155 Mbits/s SDH/SONET receivers
• Single supply voltage from 3.0 to 5.5 V
GENERAL DESCRIPTION
• Positive Emitter Coupled Logic (PECL) compatible data
outputs
The TZA3034 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3033. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 155 Mbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level detection status outputs are differential outputs
for optimum noise margin and ease of use.
• Programmable input signal level detection which can be
adjusted using a single external resistor
• On-chip DC offset compensation without external
capacitor.
ORDERING INFORMATION
TYPE
NUMBER
TZA3034T
PACKAGE
NAME
SO16
TZA3034TT
TSSOP16
TZA3034U
−
1999 Nov 03
DESCRIPTION
VERSION
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
bare die in waffle pack carriers; die dimensions 1.55 × 1.55 mm
2
−
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
BLOCK DIAGRAM
TEST
handbook, full pagewidth
2
(2, 10, 15, 21, 26)
DC-OFFSET
COMPENSATION
DIN
DINQ
TZA3034
(24) 13
4 (7)
A1
5 (8)
A2
A3
(23) 12
(16) 8
25 kΩ
DOUT
DOUTQ
JAM
RECTIFIER
(18) 10
RSET
Vref
16 (30)
15 (29)
A4
1 kΩ
ST
STQ
BAND GAP
REFERENCE
(3, 4, 6, 9)
3
AGND
(17) 9
(1, 14)
1
SUB
(11, 12)
6
(13)
7
VCCA
CF
(19, 20, 22, 25)
11
DGND
(27, 28)
14
VCCD
MGR281
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
handbook, halfpage
SUB 1
handbook, halfpage
16 RSET
SUB 1
15 Vref
TEST 2
AGND 3
DIN 4
15 Vref
TEST 2
14 VCCD
AGND 3
13 DOUT
DIN 4
TZA3034T
14 VCCD
13 DOUT
TZA3034TT
DINQ 5
12 DOUTQ
DINQ 5
12 DOUTQ
VCCA 6
11 DGND
VCCA 6
11 DGND
CF 7
10 ST
JAM 8
9
CF 7
STQ
10 ST
JAM 8
MGR282
9
STQ
MBK997
Fig.2 Pin configuration of TZA3034T.
1999 Nov 03
16 RSET
Fig.3 Pin configuration of TZA3034TT.
3
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
PINNING
SYMBOL
PIN
PAD
TZA3034T
TYPE(1)
TZA3034U
TZA3034TT
DESCRIPTION
SUB
1
1, 14
S
substrate pin; must be at the same potential as pin AGND
TEST
2
2, 10, 15,
21, 26
−
for test purpose only; to be left open in the application
AGND
3
3, 4, 6, 9
S
analog ground; must be at the same potential as pin DGND
DIN
4
7
I
differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
DINQ
5
8
I
differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
VCCA
6
11, 12
S
analog supply voltage; must be at the same potential as pin VCCD
CF
7
13
A
input for connection of capacitor to set time constant of level detector
input filter (optional); the capacitor should be connected between
VCCA and pin CF
JAM
8
16
I
PECL-compatible input; controls the output buffers,
pins DOUT and DOUTQ; when a LOW signal is applied, the output
buffers will follow the input signal; when a HIGH signal is applied, the
output buffers will latch into LOW and HIGH states respectively;
when not connected, pin JAM is actively pulled LOW
STQ
9
17
O
PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is HIGH; complementary to pin ST
ST
10
18
O
PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is LOW; complementary to pin STQ
DGND
11
19, 20, 22,
25
S
digital ground; must be at the same potential as pin AGND
DOUTQ
12
23
O
PECL-compatible differential output; this pin will be forced into a
HIGH condition when pin JAM is HIGH; complementary to pin DOUT
DOUT
13
24
O
PECL-compatible differential output; this pin will be forced into a
LOW condition when pin JAM is HIGH; complementary to
pin DOUTQ
VCCD
14
27, 28
S
digital supply voltage; must be at the same potential as VCCA
Vref
15
29
O
band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 kΩ
RSET
16
30
A
input signal level detector threshold setting; nominal DC voltage is
VCCA − 1.5 V; threshold level is set by connecting an external resistor
between VCCA and pin RSET or by forcing a current into pin RSET;
default value for this resistor is 180 kΩ which corresponds with
approximately 4 mV (p-p) differential input signal
n.c.
−
5, 31, 32
−
not connected
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
1999 Nov 03
4
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower −3 dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.
FUNCTIONAL DESCRIPTION
The TZA3034 accepts up to 155 Mbits/s SDH/SONET
data streams, with amplitudes from 2 mV up to 1.5 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs
pin DIN and pin DINQ. The input can be used both
single-ended and differential, but differential operation is
preferred for better performance.
DC-offset compensation
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3034, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3034, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL outputs,
pins ST and STQ. This flag can also be used to prevent
the PECL outputs pins DOUT and DOUTQ from reacting
to noise in the absence of a valid input signal, by
connecting pin STQ to pin JAM. This guarantees that data
will only be transmitted when the input signal-to-noise ratio
is sufficient for low bit error rate system operation.
Input signal level detection
The TZA3034 allows for user-programmable input signal
level detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL flags (pins ST and STQ)
indicate whether the input signal is above or below the
programmed threshold level.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the level
detector. This filter has a nominal 1 µs time constant and
additional filtering can be achieved by using an external
capacitor between VCCA and pin CF (the internal driving
impedance nominally is 25 kΩ). The resultant signal is
then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between VCCA and pin RSET, or by forcing a current into
pin RSET (see Fig.6).
The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3034 can be DC coupled, but
AC coupling is preferred. In case of DC coupling, the
driving source must operate within the allowable input
signal range (1.3 V to VCCA). Also a DC offset voltage of
more than a few millivolts should be avoided, since the
internal DC offset compensation circuit has a limited
correction range.
1999 Nov 03
TZA3034
5
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
The relationship between the threshold current and the
detected input voltage is approximately:
I RSET = 0.0018 × ( V DIN – V DINQ ) [ A ]
Dissipation
Since the thermal resistance from junction to ambient
Rth(j-a) of the TSSOP package is higher than the thermal
resistance of the SO package (see Chapter “Thermal
characteristics”), the dissipation should be considered
when using the TZA3034TT version.
(1)
In the formulas (1) and (3), the voltage on pin DIN and
pin DINQ is measured as peak-to-peak value.
Since the voltage on pin RSET is held constant at 1.5 V
below VCCA, the current flowing into this pin will be:
1.5
I RSET = ------------- [ A ]
R ADJ
The formula to calculate the worst case die temperature is:
T j = T amb + R th ( j – a ) × P max
(2)
(4)
where
Tj = junction temperature
Combining these two formulas results in a general formula
to calculate RADJ for a given input signal level detection:
830
R ADJ = ---------------------------------------- [ Ω ]
( V DIN – V DINQ )
TZA3034
Tamb = ambient temperature
Rth(j-a) = thermal resistance from junction to ambient
(3)
Pmax = maximum power dissipation.
For the TZA3034T (SO package), the worst case die
temperature Tj = 85 + 115 × 0.3 = 119.5 °C which is below
the maximum operating temperature.
Example: Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.0018 × 0.004 = 7.2 µA should flow
into pin RSET. This can be set using a current source or
simply by connecting a resistor of the appropriate value.
The resistor must be connected between VCCA and
pin RSET. In this example the value would be:
830
R ADJ = --------------- = 207.5 kΩ
0.004
For the TZA3034TT (TSSOP package), the worst case die
temperature Tj = 85 + 150 × 0.3 = 130 °C which is higher
than the maximum operating temperature, and therefore
strongly discouraged. It is recommended to lower the
thermal resistance from junction to ambient, e.g. by means
of a dedicated board layout.
The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.
However, if the ambient temperature is limited to 75 °C or
the power supply is limited to 3.3 ±0.3 V, the junction
temperature will stay below the maximum value without
further precautions.
A function is provided to automatically disable the signal
transmission when the chip senses that the input signal is
below the programmed threshold level. This function can
be put into operation by connecting pin JAM with pin STQ.
When the input signal is below the programmed threshold
level, the data outputs are then forced to a predetermined
state (pin DOUT = LOW and pin DOUTQ = HIGH).
PECL output circuits
The output circuit of ST and STQ is given in Fig.7.
The output circuit of DOUT and DOUTQ is given in Fig.8.
Some PECL termination schemes are given in Fig.9.
Response time of the input signal level detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1 µs internal plus the
additional capacitor at pin CF). For SDH/SONET
applications, couple capacitors of 1.5 nF are
recommended, leading to a high-pass frequency of
approximately 30 kHz and a maximum assert time of
30 µs.
1999 Nov 03
6
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
VCC
handbook, halfpage
VOH(max)
VOH(min)
(1)
(2)
VOL(max)
VOL(min)
MGS812
GND
(1) Output signal on pins DOUT or ST; complementary to output signal (2).
(2) Output signal on pins DOUTQ or STQ; complementary to output signal (1)
Fig.4 Logic level symbol definitions for PECL outputs.
VCC
handbook, halfpage
DIN
DINQ
4.5 kΩ
4.5 kΩ
2.1 V
1 mA
MGR958
Fig.5 Data input circuit DIN and DINQ.
1999 Nov 03
7
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
VCCA
handbook, halfpage
RADJ
RSET
VRSET
IRSET
TZA3034
MGS813
VRSET = VCCA − 1.5 V.
Fig.6 level detect input circuit RSET.
VCC
handbook, halfpage
VLOW
VHIGH
ST
10 kΩ
MGS814
Output STQ is complementary to output ST.
Fig.7 PECL output circuit ST and STQ.
VCC
handbook,
halfpage
105 Ω
105 Ω
DOUT
DOUTQ
0.5 mA
9 mA
0.5 mA
MGR247
Fig.8 PECL output circuit DOUT and DOUTQ.
1999 Nov 03
8
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
VCC − 2 V
handbook, full pagewidth
R1 = 50 Ω
VI
R1 = 50 Ω
VO
Zo = 50 Ω
VIQ
VOQ
MGR248
VCC = 3.3 V
handbook, full pagewidth
R1 = 127 Ω
VI
R1 = 127 Ω
VO
Zo = 50 Ω
VIQ
VOQ
R2 = 82.5 Ω
GND
R2 = 82.5 Ω
MGR249
VCC = 5.0 V
handbook, full pagewidth
R1 = 83.3 Ω
VI
R1 = 83.3 Ω
VO
Zo = 50 Ω
VIQ
VOQ
R2 = 125 Ω
GND
Fig.9 PECL output termination schemes.
1999 Nov 03
9
R2 = 125 Ω
MGR250
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134.
SYMBOL
PARAMETER
VCC
supply voltage
Vn
DC voltage
In
MIN.
−0.5
MAX.
UNIT
+6
V
pins DIN, DINQ, CF, JAM and RSET
−0.5
VCC + 0.5
V
pins STQ, ST, DOUTQ and DOUT
VCC − 2
VCC + 0.5
V
pin Vref
−0.5
+3.2
V
pins DIN, DINQ, CF and JAM
−1
+1
mA
pins STQ, ST, DOUTQ and DOUT
−25
+10
mA
pin Vref
−2
+2.5
mA
pin RSET
DC current
−2
+2
mA
Ptot
total power dissipation
−
300
mW
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
Tamb
ambient temperature
−40
+85
°C
HANDLING
This device is ESD sensitive and should be handled with care. Precautions should be taken to avoid damage through
electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can
be obtained by bonding the VCC and GND pads first, the remaining pads may then be bonded to their external
connections in any order.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITION
VALUE
UNIT
SO16 package
115
K/W
TSSOP16 package
150
K/W
thermal resistance from junction to ambient note 1
Note
1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single-sided
57 × 57 × 1.6 mm FR4 epoxy printed-circuit board with 35 µm thick copper traces. The measurements are performed
in still air.
1999 Nov 03
10
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
CHARACTERISTICS
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient
temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCC
supply voltage
3
3.3
5.5
V
ICCD
digital supply current
notes 1 and 2
−
18
31
mA
ICCA
analog supply current
note 2
−
15
24
mA
Ptot
total power dissipation
notes 1 and 2
−
110
300
mW
Tj
junction temperature
−40
−
+125
°C
Tamb
ambient temperature
−40
+25
+85
°C
Input signal pins DIN and DINQ
Vi(se)(p-p)
single-ended input signal
voltage (peak-to-peak)
note 3
0.002
−
1.5
V
Vi(dif)(p-p)
differential input signal voltage
(peak-to-peak)
note 3
0.004
−
3.0
V
VI
absolute input signal voltage
1.3
2.1
VCCA
V
VIO(eq)
equivalent input signal offset
voltage
−
−
50
µV
VIO(cor)
input offset voltage correction
note 4; positive
−
3
−
mV
note 4; negative
−
−3
−
mV
Ri
input resistance
single-ended
2.9
4.5
7.6
kΩ
Ci
input capacitance
single-ended; note 5
−
−
2.5
pF
Vn(i)(rms)
equivalent input RMS noise
voltage
notes 5 and 6
−
40
60
µV
−
60
µA
Input signal level detect pin RSET
IRSET
reference current
notes 5 and 7
5
VRSET
reference voltage
referred to VCCA
VCCA − 1.65 VCCA − 1.5
VCCA − 1.4
V
Vth(p-p)
threshold adjusting range
(single-ended and
peak-to-peak)
Vi = 155 Mbit/s PRBS 2
27 − 1 sequence;
note 5
−
12
mV
hys
hysteresis
electrically measured
2
3
6
dB
RF
filter resistance
14
25
41
kΩ
tF
filter time constant
0.5
1.0
2.0
µs
CF = 0; note 5
PECL output pins DOUT and DOUTQ
VOL
LOW-level output voltage
note 8
VCC − 1.84
−
VCC − 1.6
V
VOH
HIGH-level output voltage
note 8
VCC − 1.1
−
VCC − 0.9
V
tr
rise time
20% to 80%; note 5
−
1.5
2.2
ns
tf
fall time
80% to 20%; note 5
−
1.5
2.2
ns
tPWD
pulse width distortion
note 5
−
−
0.3
ns
f−3dB(l)
low frequency −3 dB point
−
0.85
1.5
kHz
f−3dB(h)
high frequency −3 dB point
−
150
−
MHz
1999 Nov 03
11
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
SYMBOL
PARAMETER
TZA3034
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PECL output pins ST and STQ
VOL
LOW-level output voltage
note 8
VCC − 1.84
−
VCC − 1.6
V
VOH
HIGH-level output voltage
note 8
VCC − 1.1
−
VCC − 0.9
V
CL
load capacitance
RL = ∞
−
−
20
pF
RL = 1 kΩ
−
−
100
pF
RL = 50 Ω
−
−
1000
pF
−
VCC − 1.49
V
PECL input pin JAM
VIL
LOW-level input voltage
−
VIH
HIGH-level input voltage
VCC − 1.165 −
−
V
II(JAM)
JAM input current
note 9
−20
−
+20
µA
note 10
1.165
1.20
1.235
V
Reference voltage output pin Vref
Vref
reference voltage
Notes
1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected.
2. Maximum currents are specified at Tj = 125 °C, VCC = 5.5 V and worst case processing.
3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input
signal of 0.5 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10−10.
4. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to
avoid malfunctioning of the DC offset compensation circuit.
5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee
RF functionality.
6.
total output RMS noise
Input RMS noise = --------------------------------------------------------------low frequency gain
7. The reference current can be set by connecting a resistor between VCCA and pin RSET. The corresponding input
signal level detect range is from 2 to 12 mV (p-p) single-ended. See Section “Input signal level detection” for detailed
information.
8. RL = 50 Ω connected to a level of VCC − 2 V (see Fig.9).
9. Internal pull-down resistor of 500 kΩ to DGND.
10. Internal series resistor of 1 kΩ.
1999 Nov 03
12
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
TYPICAL PERFORMANCE CHARACTERISTICS
MGR944
MGR945
1.5
50
handbook, halfpage
handbook, halfpage
Vo(dif)
ICC
(mA)
(V)
1.4
40
(1)
1.3
(2)
30
1.2
20
1.1
10
−40
0
40
80
Tj (°C)
1.0
−40
120
0
40
80
Tj (°C)
120
PECL outputs not connected.
(1) VCC = 5.5 V.
(2) VCC = 3.0 V.
Vo(dif) = VDOUT − VDOUTQ.
Fig.10 Total power supply current as function of
junction temperature.
Fig.11 Differential output voltage as function of
junction temperature.
MGR946
1.4
MGR947
2.0
handbook, halfpage
handbook, halfpage
t
(ns)
Vo(dif)
(V)
1.8
1.3
1.6
1.2
tf
tr
1.4
1.1
1.2
1
10−3
10−2
10−1
1
Vi(dif)(p-p) (V)
1.0
10−3
10
10−2
10−1
1
Vi(dif)(p-p) (V)
10
Vo(dif) = VDOUT − VDOUTQ.
Fig.12 Differential output voltage as function of
differential input voltage.
1999 Nov 03
Fig.13 Differential output rise time and fall time as
function of differential input voltage.
13
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR949
MGR948
50
2.0
handbook, halfpage
handbook, halfpage
Vi(dif)
t
(ns)
(mV)
1.6
40
1.2
30
(1)
(2)
(3)
0.8
20
0.4
10
0
−40
(4)
0
0
40
80
Tj (°C)
0
120
10
20
30
40
IRSET (µA)
50
Vi(dif) = VDIN − VDINQ.
(1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH).
(2) Input high threshold for 27 − 1 PRBS pattern (pin ST = HIGH).
(3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW).
(4) Input low threshold for 27 − 1 PRBS pattern (pin ST = LOW).
Fig.14 Differential output rise time and fall time as
function of junction temperature.
Fig.15 Status detect level as function of IRSET.
MGR951
MGR950
5
40
handbook, halfpage
handbook, halfpage
Vi(dif)
hys
(dB)
(1)
(mV)
4
30
(2)
(1)
3
(2)
20
2
(3)
10
1
(4)
0
−40
0
40
80
Tj (°C)
0
120
0
10
20
30
40
IRSET (µA)
50
Vi(dif) = VDIN − VDINQ.
(1) Input high threshold for IRSET = 45 µA (pin ST = HIGH).
(2) Input low threshold for IRSET = 45 µA (pin ST = LOW).
(3) Input high threshold for IRSET = 10 µA (pin ST = HIGH).
(4) Input low threshold for IRSET = 10 µA (pin ST = LOW).
(1) 1 0 1 0 pattern.
(2) 27 − 1 PRBS pattern.
Fig.16 Status detect level as function of junction
temperature.
Fig.17 Status detect hysteresis as function of
IRSET.
1999 Nov 03
14
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR953
MGR952
0.003
4
handbook, halfpage
handbook, halfpage
hys
(dB)
Ratio
(A/V)
(1)
3
(2)
0.002
(1)
(2)
2
0.001
1
0
−40
0
0
40
80
Tj (°C)
0
120
10
20
30
40
IRSET (µA)
50
I RSET
Ratio = ------------- where Vi(dif) = input low threshold (pin ST = LOW).
V i ( dif )
(1) IRSET = 10 µA.
(2) IRSET = 45 µA.
(1) 27 − 1 PRBS pattern.
(2) 1 0 1 0 pattern.
Fig.18 Status detect hysteresis as function of
junction temperature.
Fig.19 Status detect ratio as function of IRSET.
MGR955
MGR954
1.55
0.3
handbook, halfpage
handbook, halfpage
VRSET
t PWD
(V)
(ns)
(1)
1.53
0.2
(2)
1.51
0.1
0
10−3
10−2
10−1
1
Vi(dif)(p-p) (V)
1.49
−40
10
40
80
Tj (°C)
120
VRSET = VCCA − 1.5 V.
(1) VCC = 5.5 V.
(2) VCC = 3.0 V.
Fig.20 Pulse Width Distortion (tPWD) as function of
differential input voltage.
1999 Nov 03
0
Fig.21 VRSET as function of junction temperature.
15
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
MGR942
handbook, full pagewidth
200 mV/div
Fig.22 Differential output waveform with 4 mV differential input voltage.
MGR943
handbook, full pagewidth
200 mV/div
Fig.23 Differential output waveform with 2 V differential input voltage.
1999 Nov 03
16
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
APPLICATION INFORMATION
VCC
handbook, full pagewidth
100 nF
RSET
VCCA
6
(11, 12)
1.5 nF
DIN
100 nF
180 kΩ
16
(30)
CF
Vref
7
(13)
15
(29)
4 (7)
VCCD
14
(27, 28)
(24) 13
DOUT
TZA3034
data in
1.5 nF
DINQ
data out
5 (8)
(23) 12
(3, 4, 6, 9) (1, 14)
3
1
AGND
SUB
(16)
8
JAM
(17)
9
DOUTQ
(18) (19, 20, 22, 25)
10
11
STQ
ST
DGND
level detect
status
1 kΩ
50 Ω
50 Ω
MGR284
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.24 Application diagram.
1999 Nov 03
17
VCC − 2 V
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
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(1)
22 nF
100 nF
VCC
DREF
6
(11, 12)
1
7
TZA3033T
10 nF
IPhoto 3
31 pF
6
18
2
4
GND
OUT
100 Ω
1.5 nF
noise filter:
1-pole, 100 MHz
5
GND
1.5 nF
OUTQ
DIN
RSET
16
(30)
CF
7
(13)
VCCD
Vref
15
(29)
14
(27, 28)
4 (7)
(24) 13
DOUT
TZA3034
data out
DINQ 5 (8)
(23) 12
(3, 4, 6, 9) (1, 14)
3
1
AGND
GND
100 nF
135 kΩ
VCCA
8
(1)
SUB
(16)
8
JAM
(17)
9
STQ
DOUTQ
(18) (19, 20, 22, 25)
10
11
ST
DGND
64.4 nH
29.2
pF
64.4 nH
Philips Semiconductors
680 nF
(1)
SDH/SONET STM1/OC3 postamplifier
ewidth
1999 Nov 03
VCC
level detect
status
4.5
pF
1 kΩ
50 Ω
50 Ω
MGR285
VCC − 2 V
optional noise filter:
3-pole, 120 MHz Bessel
Product specification
Fig.25 STM1/OC3 receiver using the TZA3033T and TZA3034.
TZA3034
(1) Ferrite bead e.g. Murata BLM10A700S.
The numbers in brackets refer to the pad numbers of the bare die version.
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
BONDING PADS
COORDINATES(1)
SYMBOL
PAD
X
Y
SUB
1
−235.7
+647.8
TEST
2
−392.8
+647.8
AGND
3
−532.8
+647.8
AGND
4
−647.8
+507.1
n.c.
5
−647.8
+350.0
AGND
6
−647.8
+210.0
DIN
7
−647.8
+70.0
DINQ
8
−647.8
−70.0
AGND
9
−647.8
−210.0
TEST
10
−647.8
−350.0
VCCA
11
−647.8
−507.1
VCCA
12
−532.8
−647.8
CF
13
−392.8
−647.8
SUB
14
−235.7
−647.8
TEST
15
−78.6
−647.8
JAM
16
+61.4
−647.8
STQ
17
+218.5
−647.8
ST
18
+375.6
−647.8
DGND
19
+532.7
−647.8
DGND
20
+647.8
−507.1
TEST
21
+647.8
−350.0
DGND
22
+647.8
−210.0
DOUTQ
23
+647.8
−70.0
DOUT
24
+647.8
+70.0
DGND
25
+647.8
+210.0
TEST
26
+647.8
+350.0
VCCD
27
+647.8
+507.1
VCCD
28
+532.7
+647.8
Vref
29
+392.7
+647.8
RSET
30
+235.6
+647.8
n.c.
31
+78.5
+647.8
n.c.
32
−78.6
+647.8
Note
1. The x and y coordinates represent the position of the
centre of the pad with respect to the centre of the die
(see Fig.26).
1999 Nov 03
19
TZA3034
Philips Semiconductors
Product specification
SUB
n.c.
n.c.
RSET
Vref
VCCD
3
2
1
32
31
30
29
28
AGND
4
27
VCCD
n.c.
5
26
TEST
AGND
6
25
DGND
DIN
7
24
DOUT
DINQ
8
0
23
DOUTQ
AGND
9
y
22
DGND
TEST
10
21
TEST
VCCA
11
20
DGND
x
0
16
17
18
19
ST
DGND
SUB
15
STQ
14
JAM
13
TEST
12
CF
TZA3034U
VCCA
1.55(1)
mm
TEST
handbook, full pagewidth
TZA3034
AGND
SDH/SONET STM1/OC3 postamplifier
1.55(1) mm
MGR283
(1) Typical value.
Fig.26 Bonding pad locations of TZA3034U.
Table 1
Physical characteristics of bare die
PARAMETER
VALUE
Glass passivation
2.1 µm PSG (PhosphoSilicate Glass) on top of 0.65 µm oxynitride
Bonding pad dimension
minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
Metallization
1.22 µm W/AlCu/TiW
Thickness
380 µm nominal
Size
1.55 × 1.55 mm (2.4 mm2)
Backing
silicon; electrically connected to GND potential through substrate contacts
Attache temperature
<440 °C; recommended die attache is glue
Attache time
<15 s
1999 Nov 03
20
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.050
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.041
0.228
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
1999 Nov 03
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
21
o
8
0o
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
1999 Nov 03
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
22
o
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Nov 03
TZA3034
23
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable(2)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Nov 03
24
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Nov 03
25
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
NOTES
1999 Nov 03
26
TZA3034
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
NOTES
1999 Nov 03
27
TZA3034
Philips Semiconductors – a worldwide company
Argentina: see South America
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Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
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SCA 68
© Philips Electronics N.V. 1999
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Printed in The Netherlands
465012/100/03/pp28
Date of release: 1999
Nov 03
Document order number:
9397 750 06334