DATA SHEET MOS INTEGRATED CIRCUIT µPD75237 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75237 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM, I/O ports, a fluorescent display tube (FIP ®) controller/driver, A/D converters, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip. The µPD75237 has the more improved peripheral functions including the RAM capacity, FIP controller/driver display capabilities, I/O ports, A/D converter and serial interface than those of the µ PD75217. The µPD75237 is most suited for advanced and popular VCR timer and tuner applications, single-chip configurations of system computers, advanced CD players and advanced microwave ovens. The µPD75P238 PROM product and various types of development tools (IE-75001-R, assemblers and others) are available for evaluation in system development or small-volume production. FEATURES ● ● ● ● ● Built-in, large-capacity ROM and RAM • Program memory (ROM): 24K × 8 • Data memory (RAM): 1K × 4 ● I/O port: 64 ports (except FIP dedicated pins) Minimum instruction execution time: 0.67 µs (when operated at 6.0 MHz) Instruction execution time varying function to achieve ● ● ● ● 8-bit A/D converter: 8 channels Powerful timer/counter function: 5 channels 8-bit serial interface: 2 channels Interrupt function with importance attached to applications Product with built-in PROM: µPD75P238 a wide range of power supply voltages Built-in programmable FIP controller/driver • Number of segments: 9 to 24 • Number of digits: 9 to 16 ORDERING INFORMATION Ordering Code µPD75237GJ-×××-5BG Package 94-pin plastic QFP (20 × 20 mm) Quality Grade Standard Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-2807A (O. D. No. IC-8009A) Date Published March 1993 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1991 µPD75237 LIST OF µPD75237 FUNCTIONS Item Function Built-in memory capacity ROM: I/O line except FIP dedicated pins 64 lines ( 24448 × 8 bits, RAM: ● ) ● ● Instruction cycle ● ● ● Fluorescent display tube (FIP) controller/driver ● ● ● ● ● Number of segments : 9 to 24 Number of digits : 9 to 16 Dimmer function : 8 levels Pull-down resistor mask option Key scan interrupt generation enabled ● 5 channels ● ● ● Serial interface Input pin : 16 Input/output pin : 24 Output pin : 24 0.67 µs/1.33 µs/2.67 µs/10.7 µs (when operated at 6.0 MHz) 0.95 µs/1.91 µs/3.82 µs/15.3 µs (when operated at 4.19 MHz) 122 µs (when operated at 32.768 kHz) ● Timer/counter 1024 × 4bits 2 channels ● ● Basic interval timer : Watchdog timer applicable Timer/event counter Watch timer : Buzzer output enabled Timer/pulse generator : 14-bit PWM output enabled Event counter SBI/3-wire type 3-wire type ● Multi-interrupt enabled by hardware ● External interrupt: 3 interrupts ● External test input: 1 input ● ● ● ● Interrupt ● ● ● Internal interrupt: 5 interrupts ● ● ● ● Internal test input: 2 inputs ● ● System clock oscillator ● ● ● Mask option ● ● 2 Main system clock Subsystem clock Both-edge detection Detected edge programmable (with noise remove function) Detected edge programmable Rising edge detection Timer/pulse generator Timer/event counter Basic interval timer Serial interface #0 Key scan interrupt Clock timer Serial interface #1 : 6.0 MHz, 4.19 MHz : 32.768 kHz standard High withstand voltage port Ports 4 and 5 Port 7 : Pull-down resistor or open-drain output : Pull-up resistors : Pull-down resistor Operating temperature range –40 to +85 °C Operating voltage 2.7 to 6.0 V (standby data hold: 2.0 to 6.0 V) Package 94-pin plastic QFP (20 × 20 mm) µPD75237 AN1 AN2 AN3 AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 P31 PIN CONFIGURATION P32 P33 P40 P41 P42 P43 VSS P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 VDD S4/P130 S5/P131 S6/P132 S7/P133 S8/P140 S9/P141 VDD VLOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 PH3/T10/S15/P153 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 µPD75237GJ-×××-5BG AN0 AVREF AVDD VDD VDD X2 X1 IC XT2 XT1 VSS S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 7372 71 1 70 2 69 3 68 4 67 5 66 6 65 7 64 8 63 9 62 10 61 11 60 12 59 13 58 14 57 15 56 16 55 17 54 18 53 19 52 20 51 21 50 22 49 23 48 24252627282930313233343536373839404142434445 4647 Note Be sure to supply power to AVDD , VDD , VSS and AVSS pins (pin Nos. 3, 4, 5, 11, 30, 48, 65 and 87) . Remarks Connect the IC (Internally Connected) pin to GND. 3 TI0 INTBT TIMER/EVENT COUNTER #0 TI0/P13 PTO0/P20 PROGRAM COUNTER (15) CY ALU SP (8) SBS (2) INTT0 BANK WATCH TIMER BUZ/P23 INTW GENERAL REG. TIMER/PULSE GENERATOR PPO/P80 ROM PROGRAM MEMORY 24448x8 INTTPG SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SERIAL INTERFACE0 DECODE AND CONTROL RAM DATA MEMORY 1024x4 PORT0 4 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30-P33 PORT4 4 P40-P43* PORT5 4 P50-P53* PORT6 4 P60-P63 PORT7 4 P70-P73 PORT8 4 P80-P83 PORT9 4 P90-P93 10 INTCSI 4 SI1/P83 SO1/P82 SCK1/P81 SERIAL INTERFACE1 FIP CONTROLLER/ DRIVER T0-T9 T10/S15/PH3/P153T13/S12/PH0/P150 T14/S11/P143T15/S10/P142 10 S0/P120-S9/P141 8 S16/P100-S23/P113 fx/2N INT0/P10 INT1/P11 INT2/P12 INT4/P00 INTERRUPT CONTROL CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK Φ VLOAD PORT10-15 24 TI0 EVENT COUNTER PCL/P22 XT1XT2 X1 X2 RESET 8 P100-P153 VDD VSS VDD A/D CONVERTER BIT SEQ. BUFFER(16) * PORT4 and PORT5 are 10 V middle-high voltage N-ch open-drain input/output ports. µPD75237 AN0-AN3 AN4/P90-AN7/P93 AVDD AVREF AV SS 2 BLOCK DIAGRAM 4 BASIC INTERVAL TIMER µPD75237 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 7 1.1 1.2 1.3 1.4 2. µPD75237 ARCHITECTURE AND MEMORY MAP................................................................................ 16 2.1 2.2 2.3 3. 28 28 30 32 33 33 36 40 DIGITAL INPUT/OUTPUT PORTS ................................................................................................................... 41 CLOCK GENERATOR ........................................................................................................................................ 50 CLOCK OUTPUT CIRCUIT ................................................................................................................................ 58 BASIC INTERVAL TIMER ................................................................................................................................. 61 TIMER/EVENT COUNTER ................................................................................................................................ 63 WATCH TIMER .................................................................................................................................................. 69 TIMER/PULSE GENERATOR ........................................................................................................................... 71 EVENT COUNTER ............................................................................................................................................. 77 SERIAL INTERFACE .......................................................................................................................................... 79 A/D CONVERTER ........................................................................................................................................... 113 BIT SEQUENTIAL BUFFER: 16 BITS ............................................................................................................. 119 FIP CONTROLLER/DRIVER ............................................................................................................................ 119 INTERRUPT FUNCTIONS ...................................................................................................................... 131 5.1 5.2 5.3 5.4 5.5 6. PROGRAM COUNTER (PC): 15 BITS .............................................................................................................. PROGRAM MEMORY (ROM): 24448 WORDS × 8 BITS ............................................................................... DATA MEMORY ................................................................................................................................................ GENERAL REGISTER: 8 × 4 BITS × 4 BANKS ............................................................................................... ACCUMULATOR ............................................................................................................................................... STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ....................................................... PROGRAM STATUS WORD (PSW): 8 BITS ................................................................................................... BANK SELECT REGISTER (BS) ....................................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 41 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 5. DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE ..................................................... 16 GENERAL REGISTER BANK CONFIGURATION ............................................................................................ 19 MEMORY MAPPED I/O .................................................................................................................................... 22 INTERNAL CPU FUNCTIONS .................................................................................................................. 28 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4. PORT PINS ........................................................................................................................................................... 7 NON-PORT PINS .................................................................................................................................................. 9 PIN INPUT/OUPUT CIRCUIT LIST ................................................................................................................... 11 RECOMMENDED CONNECTIONS OF µPD75237 UNUSED PINS ............................................................... 15 INTERRUPT CONTROL CIRCUIT CONFIGURATION ................................................................................... INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES ........................................................................... INTERRUPT SEQUENCE ................................................................................................................................ MULTI-INTERRUPT SERVICE CONTROL ..................................................................................................... VECTOR ADDRESS SHARING INTERRUPT SERVICING ........................................................................... 131 133 138 139 141 STANDBY FUNCTIONS ......................................................................................................................... 142 6.1 6.2 6.3 STANDBY MODE SETTING AND OPERATING STATE .............................................................................. 142 STANDBY MODE RELEASE .......................................................................................................................... 144 OPERATION AFTER STANDBY MODE RELEASE ....................................................................................... 146 5 µPD75237 7. RESET FUNCTIONS ............................................................................................................................... 147 8. INSTRUCTION SET ................................................................................................................................ 150 8.1 8.2 8.3 9. CHARACTERISTIC INSTRUCTIONS OF µPD75237 ..................................................................................... 150 INSTRUCTION SET AND OPERATION ......................................................................................................... 153 OPERATION CODES ....................................................................................................................................... 162 MASK OPTION SELECTION ................................................................................................................. 168 10. APPLICATION BLOCK DIAGRAM ........................................................................................................ 169 11. ELECTRICAL SPECIFICATIONS ........................................................................................................... 170 ★ 12. CHARACTERISTIC CURVES (REFERENCE VALUES) ........................................................................ 183 13. PACKAGE INFORMATION ................................................................................................................... 185 14. RECOMMEDED SOLDERING CONDITIONS ....................................................................................... 186 APPENDIX A. LIST OF µPD75238 SERIES PRODUCT FUNCTIONS..................................................... 187 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................... 188 6 µPD75237 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) Pin Name I/O P00 DualFunction Pin Input / Output 8-Bit After Reset Circuit Type *1 I/O Function INT4 P01 Input SCK0 P02 SO0/SB0 P03 SI0/SB1 P10 B 4-bit input port (PORT0). Built-in pull-up resistor can be specified in 3-bit units by software for P01 to P03. Input INT1 P12 INT2 P13 TI0 P20 PTO0 P21 Input/ output P22 P23 — PCL F –B M–C × Input B –C 4-bit input/ output port (PORT2). Built-in pull-up resistor can be specified in 4-bit units by software. × Input E–B Programmable 4-bit input/ output port (PORT3). Input/ output specifiable in 1-bit units. Built-in pull-up resistor can be specified in 4-bit units by software. × Input E–C High level (when a pullup resistor is incorporated) or high impedance M 4-bit input port (PORT1). Built-in pull-up resistor can be specified in 4-bit units by software. BUZ P30 *2 P31 *2 P32 *2 — Input/ output — — — P33 *2 — N-ch open-drain 4-bit input/output port (PORT4). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open drain. — N-ch open-drain 4-bit input/ output port (PORT5). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open drain. High level (when a pullup resistor is incorporated) or high impedance M Programmable 4-bit input/output port (PORT6). Input/output specifiable in 1-bit units. Built -in pull-up resistor can be specified in 4-bit units by software. Input E–C VSS level (when a pulldown resistor is incorporated) or high impedance V *2 P40 to P43 Input/ output ● *2 P50 to P53 Input/ output — P60 P61 P62 — — — P70 — P72 P73 * 1. 2. Input/ output P63 P71 F –A Input Noise removing function available INT0 P11 × Input/ output — — ● 4-bit input/output port (PORT7). Built-in pull-down resistor can be incorporated in 1-bit units (mask option). — Schmitt trigger inputs are circled. Can drive LED directly. 7 µPD75237 1.1 PORT PINS (2/2) DualFunction Pin P80 Input/ output PPO P81 Input/ output SCK1 P82 Input/ output SO1 E P83 Input SI1 B P91 Input AN5 P92 AN6 P93 AN7 P100 S16 S17 Output P102 S18 P103 S19 P110 S20 P111 Output S21 P112 S22 P113 S23 P120 S0 P121 S1 Output P122 S2 P123 S3 P130 S4 P131 Output S6 P133 S7 P140 S8 S9 P141 Output P142 S10/T15 P143 S11/T14 P150 S12/T13/PH0 S13/T12/PH1 Output P152 S14/T11/PH2 P153 S15/T10/PH3 PH0 S12/T13/P150 PH1 A 4-bit input port (PORT8). 4-bit input port (PORT9). × Input S13/T12/P151 Output PH2 S14/T11/P152 PH3 S15/T10/P153 × Input ● VLOAD level (when a pulldown resistor to VLOAD is incorporated), V SS level (when a pulldown resistor to VSS is incorporated) or high impedance P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). F Y–A I–F P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). ● P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). S5 P132 P151 Function AN4 P101 8 Input / Output Circuit Type * I/O P90 * 8-Bit After Reset I/O Pin Name VLOAD level (when a pulldown resistor to VLOAD is incorporated) or high impedance P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). P142 and P143 can drive LED directly. ● P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). These ports can drive LED directly. P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). Schmitt trigger inputs are circled. × I–C µPD75237 1.2 NON-PORT PINS (1/2) Pin Name I/O T0 to T9 DualFunction Pin Function PH3/P153 to T13/S12 PH0/P150 T14/S11 Digit/segment output dual-function high-voltage high-current output pins. Extra pins can be used as PORTH. These pins can be used as PORT15 in the static mode. Digit/segment output dual-function high-voltage high-current output pins. These pins can be used as POTR14 in the static mode. P143 T15/S10 P142 P120 to S0 to S3 P123 Output P130 to S4 to S7 P133 S8 P140 S9 P141 P103 Segment high-voltage output pins. These pins can be used as PORT10 and PORT11 in the static mode. P110 to S20 to S23 * VLOAD level (when a pull-down resistor to VLOAD is inc o r p o rated) or high impedance. I–C FIP controller/driver output pins. Segment high-voltage output Pull-down resistor can pins. be incorporated in bit These pins can be used as units (mask option). PORT12 to PORT14 in the static mode. P100 to S16 to S19 Input / Output Circuit Type * Digit output high-voltage highcurrent output pins. — T10/S15 to After Reset P113 TI0 Input P13 External event pulse input to timer/event counter #0 and event counter #1. PTO0 Output P20 PCL Output BUZ VLOAD level (when a pull-down resistor to VLOAD is inc o r p o rated), VSS level (when a pull-down resistor to VSS is incorporated) or high impedance I–F — B –C Timer/event counter output. Input E–B P22 Clock output. Input E–B Output P23 Fixed frequency output (for buzzer or system clock trimming). Input E–B SCK0 Input/ output P01 Serial clock input/output. Input F –A SO0/SB0 Input/ output P02 Serial data output. Serial bus input/output. Input F –B SI0/SB1 Input/ output P03 Serial data input. Serial bus input/output. Input M–C Schmitt trigger inputs are circled. 9 µPD75237 1.2 NON-PORT PINS (2/2) Pin Name I/O INT4 Input DualFunction Pin P00 P10 INT0 After Reset Input / Output Circuit Type * Edge-detected vectored interrupt input (valid for detection of rising and falling edges). — B — B –C — B –C Edge-detected vectored interrupt input (detected edge selection possible). Input INT1 Function Asynchronous P11 Input INT2 Clocked P12 Edge-detected testable input (rising edge detection). Asynchronous SCK1 Input/ output P81 Serial clock input/output. Input F SO1 Output P82 Serial data output. Input E SI1 Input P83 Serial data input. Input B — AN0 to AN3 Input Analog input to A/D converter. — Y–A P90 to P93 AN4 to AN7 Y AVDD — — A/D converter power supply. — — AVREF Input — A/D converter reference voltage input. — Z AVSS — — A/D converter reference GND potential. — — X1, X2 Input — Main system clock oscillation crystal/ceramic connection. An external clock is input to X1 and an antiphase clock is input to X2. — — XT1 Input — — — XT2 — Subsystem clock oscillation crystal connection. An external clock is input to XT1 and XT2 is made open. RESET Input — System reset input. — B PPO Output P80 Input — Timer/pulse generator pulse output. VDD (3 – Pin) — — Positive power supply. — — VSS (2 – Pin) — — GND potential. — — VLOAD — — FIP controller/driver pull-down resistor connect/power supply. — — * 10 Schmitt trigger inputs are circled. µPD75237 1.3 PIN INPUT/OUTPUT CIRCUIT LIST (1/4) TYPE A TYPE D VDD VDD data P-ch P-ch IN OUT output disable N-ch N-ch Push-Pull Output which can be Set to Output High Impedance (with Both P-ch and N-ch Set to OFF) CMOS-Specified Input Buffer TYPE B TYPE E data IN/OUT Type D output disable IN Type A Schmitt Trigger Input Having Hysteresis Characteristics TYPE B-C Input/Output Circuit Consisting of Type D Push-Pull Output and Type A Input Buffer TYPE E-B VDD VDD P.U.R P.U.R P-ch output disable P.U.R enable P-ch data IN/OUT Type D IN output disable P.U.R:Pull-Up Resistor Schmitt Trigger Input Having Hysteresis Characteristics Type A P.U.R:Pull-Up Resistor 11 µPD75237 1.3 PIN INPUT/OUTPUT CIRCUIT LIST (2/4) VDD TYPE E-C VDD TYPE F-B P.U.R P.U.R P.U.R enable output disable (P-ch) P-ch data P.U.R enable P-ch VDD P-ch IN/OUT Type D IN/OUT data output disable output disable output disable (N-ch) Type A N-ch Type B P.U.R:Pull-Up Resistor P.U.R:Pull-Up Resistor TYPE F TYPE F-C VDD P.U.R data IN/OUT P.U.R enable Type D output disable P-ch data IN/OUT Type D output disable Type B Type B Input/Output Circuit Consisting of Type D Push-Pull Output and Type B Schmitt Trigger Input TYPE F-A P.U.R:Pull-Up Resistor TYPE I-C VDD P.U.R P.U.R enable VDD VDD P-ch data data P-ch OUT IN/OUT Type D N-ch output disable P-ch P.D.R (Mask Option) VLOAD Type B P.D.R:Pull-Down Resistor P.U.R:Pull-Up Resistor 12 µPD75237 1.3 PIN INPUT/OUTPUT CIRCUIT LIST (3/4) TYPE I-F TYPE V VDD VDD data IN/OUT data P-ch Type D P-ch output disable OUT P.D.R (Mask Option) N-ch Type A VLOAD P.D.R (Mask Option) P.D.R:Pull-Down Resistor P.D.R:Pull-Down Resistor TYPE M TYPE Y VDD P.U.R (Mask Option) AVDD IN/OUT P-ch data IN N-ch output disable AVDD N-ch Sampling C AVSS AVSS AVSS Reference Voltage (from the Series Resistance String Voltage Tap) Middle-High Voltage Input Buffer P.U.R:Pull-Up Resistor TYPE M-C TYPE Y-A VDD P.U.R P.U.R enable AVDD P-ch P-ch IN/OUT data N-ch IN AVDD Sampling C N-ch output disabie AVSS AVSS Type B P.U.R:Pull-Up Resistor AVSS Reference Voltage (from the Series Resistance String Voltage Tap) 13 µPD75237 1.3 PIN INPUT/OUTPUT CIRCUIT LIST (4/4) TYPE Z AVss 14 µPD75237 1.4 RECOMMENDED CONNECTIONS OF µPD75237 UNUSED PINS Pin P00/INT4 Recommended Connection Connect to V SS P01/SCK0 P02/SO0/SB0 Connect to V SS or VDD P03/SI1/SB1 P10/INT0 to P12/INT2 Connect to V SS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ Input state : Connect to VSS or VDD P30 to P33 P40 to P43 Ouput state : Leave open P50 to P53 P60 to P63 P70 to P73 P80/PPO P81/SCK1 P82/SO1 Connect to V SS P83/SI1 P90/AN4 to P93/AN7 P100/S16 to P103/S19 P110/S20 to P113/S23 P120 to P123 Leave open P130 to P133 P140 to P143 P150 to P153 AN0 to AN3 Connect to V SS AVREF AVDD Connect to V DD AVSS Connect to V SS XT1 Connect to V SS or VDD XT2 Leave open VLOAD Connect to V SS 15 µPD75237 2. µPD75237 ARCHITECTURE AND MEMORY MAP The µPD75237 has the following three architectural features. (a) (b) (c) Data memory bank configuration General register bank configuration Memory mapped I/O Each feature is outlined below. 2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE As shown in Fig. 2-1, the µ PD75237 incorporates a static RAM (928 words × 4 bits) at addresses 000H to 19FH and 200H to 3FFH in the data memory space and a display data memory (96 words × 4 bits) at addresses 1A0H to 1FFH and peripheral hardware (input/output ports, timers, etc.) at addresses F80H to FFFH. For addressing of this 12-bit address data memory space, the memory bank has a configuration wherein the lower 8 bits are directly or indirectly specified by an instruction and the higher 4-bit address is specified by a memory bank (MB). A memory bank enable flag (MBE) and a memory bank select register (MBS) are incorporated to specify the memory bank (MB) and addressing operations shown in Fig. 2-1 and Table 2-1 can be carried out. (MBS is a register to select the memory bank and can set 0, 1, 2, 3 and 15. MBE is a flag to determine whether the memory bank selected by MBS should be validated or not. Since MBE is automatically saved/reset for interrupt or subroutine processing, it can be freely set for either processing.) For data memory space addressing, set MBE = 1 normally and manipulate the memory bank static RAM specified by MBS. Efficient programming is possible by using the MBE = 0 or MBE = 1 mode for each program processing. Applicable Program Processing 16 MBE = 0 mode Interrupt service Processing of repeating built-in hardware manipulation and static RAM manipulation Subroutine processing MBE = 1 mode Normal program processing µPD75237 Fig. 2-1 Date Memory Configuration and Addressing Range in Each Addressing Mode Addressing Mode Memory Bank Enable Flag 000H MBE =0 MBE =1 @HL @H+mem. bit MBE =0 MBE =1 @DE @DL — Stack pmem. Address- fmem. bit @L ing — — — General Register Area 01FH 020H 07FH mem mem. bit MBS =0 MBS =0 SBS =0 MBS =1 MBS =1 SBS =1 Data Area Static RAM (Memory Bank 2) MBS =2 MBS =2 SBS =2 Data Area Static RAM (Memory Bank 3) MBS =3 MBS =3 SBS =3 MBS = 15 MBS = 15 Data Area Static RAM (Memory Bank 0) 0FFH 100H 19FH 1A0H Data Area Static RAM (Memory Bank 1) Display Data Memory Area 1FFH 200H Stack Area 2FFH 300H 3FFH Not Incorporated F80H FC0H Peripheral Hardware Area (Memory Bank 15) FFFH Remarks — : Don’t care 17 µPD75237 Table 2-1 Addressing Modes Addressing Mode 1-bit direct addressing Identifier mem.bit Address Specified Bit indicated by bit of address indicated by MB and mem, where: When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS Address indicated by MB and mem, where : When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS 4-bit direct addressing mem Address indicated by MB and mem (mem is an even address), where: When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS 8-bit direct addressing @HL Address indicated by MB and HL, where : MB = MBE• MBS @HL+ @HL– Address indicated by MB and HL, where : MB = MBE• MBS HL+ automatically increments L register after addressing. HL– automatically decrements L register after addressing. 4-bit register indirect addressing 8-bit register indirect addressing @DE Address indicated by DE of memory bank 0 @DL Address indicated by DL of memory bank 0 @HL Address indicated by MB and HL, where : MB = MBE• MBS Bit 0 of L register is ignored. fmem.bit Bit manipulation addressing pmem.@L @H + mem.bit Stack addressing Bit indicated by bit of address indicated by fmem, where: FB0H to FBFH (interrupt-related hardware) fmem = FF0H to FFFH (I/O port) Bit indicated by the lower 2 bits of L register of the address indicated by the higher 10 bits of pmem and the higher 2 bits of L register, where: pmem = FC0H to FFFH Bit indicated by bit of the address indicated by MB, H and the lower 4 bits of mem, where: MB = MBE• MBS Address indicated by SP of memory banks 0, 1, 2 and 3 selected by SBS As described in Table 2-1, direct and indirect addressing is possible for each of 1-bit, 4-bit and 8-bit data in µ PD75237 data memory manipulation. Thus, easy-to-understand programs can be created very efficiently. 18 µPD75237 2.2 GENERAL REGISTER BANK CONFIGURATION The µPD75237 incorporates four register banks, each bank consisting of eight general registers, X, A, B, C, D, E, H and L. This general register area is mapped at addresses 00H to 1FH of the memory bank 0 of the data memory (refer to Fig. 2-2 General Register Configuration (4-Bit Processing)). A register bank enable flag (RBE) and a register bank select register (RBS) are incorporated to specify the above general register banks. RBS is a register to select a register bank and RBE is a flag to determine whether the register bank selected by RBS should be validated or not. The register bank (RB) which is validated for instruction execution is given as RB = RBE• RBS. As described above, with the µPD75237 having four register banks, programs can be created very efficiently by using different register banks for normal processing and interrupt service as described in Table 2-2. (RBE is automatically saved and set for interrupt service and automatically reset upon termination of the interrupt service.) Table 2-2 Recommended Use of Register Banks in Normal and Interrupt Routines Normal processing Use register banks 2 and 3 with RBE = 1. Single interrupt service Use register bank 0 with RBE = 0. Double interrupt service Use register bank 1 with RBE = 1. (It is necessary to save/reset RBS.) Triple or more interrupt service Save/reset registers by PUSH and POP. Not only in 4-bit units, a register pair of XA, HL, DE or BC can transfer, compare, operate, increment or decrement data in 8-bit units. In this case, register pairs with the reversed bit 0 of the register bank specified by RBE•RBS can be specified as XA’, HL’, DE’ and BC’. Thus, the µPD75237 has eight 8-bit registers (refer to Fig. 2-3 General Register Configuration (8-Bit Processing)). 19 µPD75237 Fig. 2-2 General Register Configuration (4-Bit Processing) X H 01H 03H D A L X H D 07H 09H 0BH 0DH B C A L E 13H 15H 0CH L E 12H Register Bank 2 (RBE·RBS = 2) 14H C 19H 1BH 1DH B 16H A L E 18H 1AH Register Bank 3 (RBE·RBS = 3) 1CH C 1FH 20 Register Bank 1 (RBE·RBS = 1) 10H 17H D 0AH A B H 08H 0EH 11H X 06H C X D Register Bank 0 (RBE·RBS = 0) 04H 0FH H 02H E 05H B 00H 1EH µPD75237 Fig. 2-3 General Register Configuration (8-Bit Processing) XA HL XA' 00H HL' 02H DE XA' HL' DE' 06H 04H BC' When RBE·RBS = 0 HL 0AH DE 0CH XA' 10H HL' 12H HL' DE' 0CH 10H 12H DE' 14H XA' 0AH 0EH DE BC 08H BC 0EH HL 06H When RBE·RBS = 1 XA 08H BC' XA 02H DE' 04H BC 00H 16H 18H 1AH 1CH BC' 14H BC' When RBE·RBS = 2 16H When RBE·RBS = 3 XA HL DE 18H 1AH 1CH BC 1EH 1EH 21 µPD75237 2.3 MEMORY MAPPED I/O As shown in Fig. 2-1, the µPD75237 employs the memory mapped I/O with the peripheral hardware including input/output ports and timers mapped at addresses F80H to FFFH in the data memory space. Thus, there are no special instructions to control the peripheral hardware and all operations are controlled by memory manipulation instructions. (Some hardware control mnemonics are available to make the program easy to understand.) When operating the peripheral hardware, the addressing modes listed in Table 2-3 can be used. Manipulate the display data memory, key scan register and port H mapped at addresses 1A0H to 1FFH by specifying memory bank 1. Table 2-3 Addressing Modes Applicable when Operating the Peripheral Hardware at Addresses F80H to FFFH Applicable Hardware Applicable Addressing Mode Bit manipulation Specify by direct addressing mem.bit with MBE = 0 or (MBE = 1, MBS = 15) All hardware devices enabled for bit manipulation Specify by direct addressing fmem.bit irrespective of MBE and MBS IST0, IST1, MBE, RBE, IE×××, IRQ×××, PORTn. 0 to 3 Specify by indirect addressing pmem.@L irrespective of MBE and MBS PORTn. Specify by direct addressing mem with MBE = 0 or (MBE = 1, MBS = 15) 4-bit manipulation Specify by register indirect addressing @HL with (MBE = 1, MBS = 15) Specify by direct addressing mem with MBE = 0 or (MBE = 1, MBS = 15) (mem is an even address.) 8-bit manipulation Specify by register indirect addressing @HL with MBE = 1 and MBS = 15 (L register contents are even.) All hardware devices enabled for 4-bit manipulation All hardware devices enabled for 8-bit manipulation Table 2-4 shows the µPD75237 I/O map. In the table, each item has the following meanings: • Symbol ............. Name indicating the on-chip hardware address. Can be described in the instruction operand column. • R/W ................... Indicates whether the corresponding hardware is enabled for read/write. R/W : Read/write enable R : Read only W : Write only • No. of manipulatable bits ........ Indicates the number of applicable bits before operating the corresponding hardware. • Bit manipulated addressing .... Indicates the applicable bit manipulated addressing before operating the applicable hardware. 22 µPD75237 Table 2-4 µPD75237 I/O Map (1/5) Hardware Name (Symbol) Address R/W b3 b2 b1 b0 No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits F80H Stack pointer (SP) F82H R/W — — ● — ● R/W — ● — Register bank select register (RBS) Be sure to write 0 to bit 0. ● — ● R*1 F83H Memory bank select register (MBS) F84H Stack bank select register (SBS) F85H Basic interval timer mode register (BTM) W ▲ ● — Basic interval timer (BT) R — — ● F88H Display mode register (DSPM) W — ● — F89H Dimmer select register (DIMS) W — ● — R/W ▲ ● W ▲ Timer pulse generator modulo register L (MODL) R/W Timer pulse generator modulo register H (MODH) Remarks ★ *2 Be sure to write 0 to bits 3 and 2. mem.bit Only bit 3 is bit-manipulatable. — mem.bit Only bit 3 is bittestable. ▲ ● mem.bit — — ● R/W — — ● W — — ● F86H F8AH F90H F94H F96H KSF Digit select register (DIGS) Timer pulse generator mode register (TPGM) Only bit 3 is bit-manipulatable. F98H Watch mode register (WM) * 1. 2. Can be read/written by the SEL instruction. Individually manipulatable as RBS and MBS by 4-bit manipulation. Manipulatable as BS by 8-bit manipulation. 23 µPD75237 Table 2-4 µPD75237 I/O Map (2/5) Hardware Name (Symbol) Address FA0H R/W b3 b2 b1 b0 ▲ Timer/event counter 0 mode register (TM0) W FA2H TOE0 FA4H FA6H FA8H FABH — Remarks Only bit 3 is bit-manipulatable. ● — — W ● — — Timer/event counter 0 count register (T0) R — — ● Timer/event counter 0 modulo register (TMOD0) W — — ● Event counter mode register (TM1) ▲ — W Gate control register (GATEC) Counter register (T1) FACH 24 No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits Only bit 3 is bit-manipulatable. ● — — W — ● — R — — ● µPD75237 Table 2-4 µPD75237 I/O Map (3/5) Hardware Name (Symbol) Address R/W b3 b2 b1 b0 IST1 IST0 MBE RBE FB0H R/W Program status word (PSW) FB2H Interrupt priority select register (IPS) W No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits ● ● — — ● ● Remarks ● fmem.bit ★ — FB3H Processor clock control register (PCC) W ● ● FB4H INT0 mode register (IM0) W — ● FB5H FB7H FB8H INT1 mode register (IM1) W IRQ4 IEBT ● W ● — IRQBT R/W ● ● EOT R/W ● ● IRQW R/W ● ● IRQTPG R/W ● ● IRQT0 R/W ● ● R/W ● ● System clock control register (SCC) IE4 — Be sure to write 0 to bit 2. — Be sure to write 0 to bits 3, 2 and 1. — Only bits 3 and 0 are bit-manipulatable. ★ — FB9H IEW FBAH — FBBH IEKS IRQKS IETPG fmem.bit IRQT1 FBCH IET0 — IECSI0 IRQCSI0 FBDH FBEH IE1 FBFH IRQ1 IE0 IRQ0 R/W ● ● IE2 IRQ2 R/W ● ● FC0H Bit sequential buffer 0 (BSB0) R/W ● ● FC1H Bit sequential buffer 1 (BSB1) R/W ● ● FC2H Bit sequential buffer 2 (BSB2) R/W ● ● FC3H Bit sequential buffer 3 (BSB3) R/W ● ● W — — W ● — R/W — — — ● ● FC8H FC9H CSIM11 CSIM10 CSIE1 ● ★ FCCH Serial I/O shift register (SIO1) ● 25 µPD75237 Table 2-4 µPD75237 I/O Map (4/5) Hardware Name (Symbol) Address FD0H FD4H FD6H ★ FD8H R/W b3 b2 b1 b0 No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits Clock output mode register (CLOM) W — ● — Static mode register B (STATB) W — — ● Static mode register A (STATA) W — — ● ▲ — SOC EOC A/D conversion mode register (ADM) Write only in 8-bit manipulation ● R/W — — Remarks FDAH FDCH FE0H SA register (SA) R — — ● Pull-up register specification register group A (POGA) W — — ● Serial operating mode register (CSIM0) W — — ● FE2H CSIE0 COI WUP CMDD RELD CMDT FE4H FE6H FE8H FECH 26 ACKD ACKE ● ● R/W ● — — R/W — — ● W — — ● W — — ● W — — ● mem.bit RELT SBI control register (SBIC) BSYE R/W ACKT Serial I/O shift register 0 (SIO0) Slave address register (SVA) PM33 PM32 PM31 PM30 Port mode register group A (PMGA) PM63 PM62 PM61 PM60 — PM2 — — Port mode register group B (PMGB) PM7 — PM5 PM4 mem.bit Write only in 8-bit manipulation µPD75237 Table 2-4 µPD75237 I/O Map (5/5) Hardware Name (Symbol) Address R/W b3 b2 b1 b0 No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits FF0H Port 0 (PORT0) R ● ● FF1H Port 1 (PORT1) R ● ● FF2H Port 2 (PORT2) R/W ● ● FF3H Port 3 (PORT3) R/W ● ● FF4H Port 4 (PORT4) R/W ● ● FF5H Port 5 (PORT5) R/W ● ● FF6H Port 6 (PORT6) R/W ● ● FF7H Port 7 (PORT7) R/W ● ● FF8H Port 8 (PORT8) R ● ● FF9H Port 9 (PORT9) R ● ● FFAH Port 10 (PORT10) W ● ● FFBH Port 11 (PORT11) W ● ● FFCH Port 12 (PORT12) W ● ● FFDH Port 13 (PORT13) W ● ● FFEH Port 14 (PORT14) W ● ● FFFH Port 15 (PORT15) W ● ● R/W ● ● R/W ● ● R/W ● ● R/W ● ● Display data memory: S0 to S7 (n = 0 to 15) R/W ● ● R/W ● ● Display data memory: S8 to S15 (n = 0 to 15) R/W ● ● R/W ● ● R/W ● ● R/W ● ● Remarks — — ● ● fmem.bit pmem.@L — ● ● ● 1A0H+4n 1A1H+4n Display data memory: S16 to S23 (n = 0 to 15) 1BEH ● ● Key scan register (KS2) 1BFH 1C0H+4n 1C1H+4n ● mem.bit 1C2H+4n 1C3H+4n 1FCH ● ● Key scan register (KS0) 1FDH 1FEH Key scan register (KS1) R/W ● ● 1FFH Port H (PORTH) R/W ● ● ● 27 µPD75237 3. INTERNAL CPU FUNCTIONS 3.1 PROGRAM COUNTER (PC): 15 BITS This is a 15-bit binary counter to hold the program memory address information. Fig. 3-1 Program Counter Configuration PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 When RESET is input, the lower 6 bits at address 0000H and the contents at address 0001H of the program memory are set to PC13 to PC8 and PC7 to PC0, respectively, and the PC is initialized. The reset start address should therefore be located in the 16K space (0000H to 3FFFH). 3.2 PROGRAM MEMORY (ROM): 24448 WORDS × 8 BITS This is a mask programmable ROM having a configuration of 24448 words × 8 bits to store programs, table data, etc. The program memory is addressed by the program counter. Table data can be referred to by the table reference instruction (MOVT). The branch range enabled by the branch and subroutine call instructions is shown in Fig. 3-2. The entire space branch instruction (BRA !addr1) and the entire space call instruction (CALLA !addr1) allow direct branching to the entire space from 0000H to 5F7FH. The relative branch instruction (BR $addr) enables branch to the [PC contents –15 to –1, +2 to +16] address irrespective of the block boundary. The program memory addresses are 0000H to 5F7FH and the following addresses are especially assigned. (All areas except 0000H and 0001H can be used as the normal program memory.) • Addresses 0000 and 0001H Vector address table for writing the program start address to be set upon RESET input and the RBE and MBE set values. Can be reset and started at any address in a 16K space (0000H to 3FFFH). • Addresses 0002 to 000FH Vector address table for writing the program start address to be set by each vectored interrupt and the RBE and MBE set values. Interrupt service can be started at any address in a 16K space (0000H to 3FFFH). • Addresses 0020 to 007FH Table area to be referred to by GETI instruction*. * GETI instruction is an instruction to realize any 2-byte/3-byte instruction or two 1-byte instructions with one byte. It is used to decrease the number of program bytes. (Refer to 8.1 CHARACTERISTIC INSTRUCTIONS OF µPD75237.) 28 µPD75237 Fig. 3-2 Program Memory Map 0000H MBE RBE Internal Reset Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address 0004H MBE RBE INT0 Start Address 0006H MBE RBE INT1 Start Address 0008H MBE RBE INTCSI0 Start Address 000AH MBE RBE INTT0 Start Address 000CH MBE RBE INTTPG Start Address 000EH MBE RBE INTKS Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) BRA !addr1 Instruction Branch Address BRCB !caddr Instruction Branch Address GETI Instruction Reference Table CALLA !addr1 Instruction Branch Address BR $addr1 Instruction Relative Branch Address (-15 to -1 and +2 to +16) (Most Significant 6 Bits) (Least Significant 8 Bits) 0020H 007FH CALLF !faddr Instruction Entry Address BR !addr Instruction Branch Address CALL !addr Instruction Branch Address 0080H 07FFH Branch/call Address by GETI 0800H 0FFFH 1000H BRCB !caddr Instruction Branch Address 1FFFH 2000H BRCB !caddr Instruction Branch Address 2FFFH 3000H BRCB !caddr Instruction Branch Address 3FFFH 4000H BRCB !caddr Instruction Branch Address 4FFFH 5000H BRCB !caddr Instruction Branch Address 5F7FH Note As stated above, the interrupt vector start address is 14 bits in length, and should therefore be set in the 16K space (0000H to 3FFFH). Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed is enabled by BR PCDE and BR PCXA instructions. 29 µPD75237 3.3 DATA MEMORY The data memory consists of a static RAM and peripheral hardware. The static RAM incorporates 160 words × 4 bits of memory banks 0, 2 and 3, 768 words × 4 bits of memory bank 1 and 96 words × 4 bits of memory bank 1 which also serves as a display data memory. It is used to store process data and to serve as a stack memory for interrupt execution. General registers, display data memory and various registers of peripheral hardware are mapped at particular addresses of the data memory and such data is manipulated by the general register and memory manipulation instructions. (Refer to Fig. 2-1 Data Memory Configuration and Addressing Range in Each Addressing Mode.) All addresses (000H to 3FFH) of memory banks 0, 1, 2 and 3 can be used as a stack area. Although the data memory consists of one address and 4 bits, it can be manipulated in 8-bit units by the 8-bit memory mainipulation instruction or in bit units by the bit manipulation instruction. Specify an even address by the 8-bit manipulation instruction. The display data memory area (1A0H to 1FFH) is made up as shown in Fig. 3-4. Fig. 3-3 Data Memory Map Data Memory General Register Area Memory Bank 000H 01FH (32 × 4) 0 020H 256 × 4 0FFH 100H 256 × 4 Stack Area Data Area Static RAM (1024 × 4) 19FH Display Data Memory, etc. 1 1A0H (96 × 4) 1FFH 200H 256 × 4 2 256 × 4 3 2FFH 300H 3FFH Not Incorporated F80H Peripheral Hardware Area 128 × 4 FFFH 30 15 µPD75237 Fig. 3-4 Display Data Memory Configuration 1 A 1 H 1 A 0 H 1 A 3 H 1 A 2 H 1 C 7 H 1 C 6 H 1 C 5 H 1 C 4 H 1 A 5 H 1 A 4 H 1 C B H 1 C A H 1 C 9 H 1 C 8 H 1 A 7 H 1 A 6 H 1 C F H 1 C E H 1 C D H 1 C C H 1 A 9 H 1 A 8 H 1 D 3 H 1 D 2 H 1 D 1 H 1 D 0 H 1 A B H 1 A A H 1 D 7 H 1 D 6 H 1 D 5 H 1 D 4 H 1 A D H 1 A C H 1 D B H 1 D A H 1 D 9 H 1 D 8 H 1 A F H 1 A E H 1 D F H 1 D E H 1 D D H 1 D C H 1 B 1 H 1 B 0 H 1 E 3 H 1 E 2 H 1 E 1 H 1 E 0 H 1 B 3 H 1 B 2 H 1 E 7 H 1 E 6 H 1 E 5 H 1 E 4 H 1 B 5 H 1 B 4 H 1 E B H 1 E A H 1 E 9 H 1 E 8 H 1 B 7 H 1 B 6 H 1 E F H 1 E E H 1 E D H 1 E C H 1 B 9 H 1 B 8 H 1 F 3 H 1 F 2 H 1 F 1 H 1 F 0 H 1 B B H 1 B A H 1 F 7 H 1 F 6 H 1 F 5 H 1 F 4 H 1 B D H 1 B C H 1 F B H 1 F A H 1 F 9 H 1 F 8 H No. of manipulatable bits 1 B F H Remarks 1. 2. 1 C 3 H 1BEH (KS2) IFFH (PORTH) 1 C 2 H 1FEH (KS1) 1 C 1 H 1 F D H 1 C 0 H 1FCH (KS0) 1 bit 4 bits 8 bits KS0, KS1 and KS2: Key scan register PORTH: High-voltage, high-current output port which also serves as digit output port 31 µPD75237 3.4 GENERAL REGISTER: 8 × 4 BITS × 4 BANKS The general registers are mapped at the special addresses of the data memory. There are 4-bank registers, each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A). The register bank (RB) which becomes valid for instruction is given as RB = RBE• RBS (RBS = 0 to 3). Each general register is operated in 4-bit units. BC, DE, HL and XA form register pairs and are used for 8-bit manipulation. In addition to DE and HL, DL also makes up a pair and these three pairs can be used as a data pointer. The general register area can be accessed by address specification as a normal RAM whether or not it is used as a register. Fig. 3-5 General Register Configuraton Address 3 Data Memory 000H A Register 001H X Register 002H L Register 003H H Register Fig. 3-6 Register Pair Configuration 3 0 0 3 C B 3 0 3 Register Bank 0 004H E Register 005H D Register 006H C Register 007H B Register 0 ......... Same Configuration as Bank 0 Register Bank 1 Same Configuration as Bank 0 Register Bank 2 Same Configuration as Bank 0 Register Bank 3 00FH 010H ......... 017H 018H ......... 01FH 32 0 L 0 X 008H 3 H 3 0 E D 3 0 3 0 A 1 Bank µPD75237 3.5 ACCUMULATOR In the µPD75237, A register and XA register pair function as an accumulator. The 4-bit data processing instruction is executed mainly by A register and the 8-bit data processing instruction is executed mainly by XA register pair. For execution of the bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Fig. 3-7 Accumulator CY X 3.6 Bit Accumulator A 4-Bit Accumulator A 8-Bit Accumulator STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) In the µPD75237, the static RAM is used as a static memory (LIFO type) and the 8-bit register which holds the start address information in the stack area is a stack pointer (SP). The stack area is located at addresses 000H to 3FFH of memory banks 0, 1, 2 and 3. Specify one memory bank by a 4-bit SBS. The SP is decremented prior to a write (save) to the stack memory and incremented after a read (restore) from the stack memory. Set SBS by the 4-bit memory manipulation instruction. In this case, set the higher 2-bits to 00. The data to be saved/restored by each stack operation is shown in Figs. 3-9 and 3-10. The SP initial value is set by the 8-bit memory manipulation instruction and the SBS initial value is set by the 4-bit memory manipulation instruction and then the stack area is determined. The SP and SBS contents can also be read. Table 3-1 Stack Areas to be Selected by SBS SBS 0 0 1 1 ------------------------------- SBS1 Stack Area SBS0 0 Memory bank 0 1 Memory bank 1 0 Memory bank 2 1 Memory bank 3 When the SP initial value is set to 00H, stack starts with the most significant address (nFFH) of the memory bank (n: n = 0, 1, 2, 3) specified by SBS. The stack area is limited to the memory bank specified by SBS. When stack operation is further carried out at address n00H, the address is reset to nFFH in the same bank. Linear stack past the memory bank boundary is not possible without rewriting SBS. Since RESET input makes the SP and SBS undefined, be sure to initialize the SP and SBS to any desired value at the beginning of the program. 33 µPD75237 Fig. 3-8 Stack Bank Select Register Configuration Address F80H Symbol SP7 SP6 SP5 SP4 SP3 SP2 F84H SP1 SP Fixed to 0 SBS1 SBS0 SBS 000H Memory Bank 0 SBS SP 0FFH 100H Memory Bank 1 SP Memory Bank 2 SP Memory Bank 3 SP 1FFH 200H 2FFH 300H 3FFH 34 µPD75237 Fig. 3-9 Data to be Saved into Stack Memory PUSH Instruction CALL, CALLA and CALLF Instructions Interrupt Stack Stack Stack PC11-PC8 SP - 6 SP - 5 0 PC11-PC8 SP - 6 SP - 5 PC14PC13PC12 0 PC14PC13PC12 SP - 2 Lower Half of Register Pair SP - 4 PC3-PC0 SP - 4 PC3-PC0 SP - 1 Upper Half of Register Pair SP - 3 PC7-PC4 SP - 3 PC7-PC4 SP - 2 SP ∗ ∗ SP - 2 MBE RBE * SP - 1 ∗ ∗ ∗ ∗ SP - 1 SP IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0 SP Fig. 3-10 Data to be Restored from Stack Memory POP Instruction RET and RETS Instruction Stack Stack SP Lower Half of Register Pair SP SP + 1 Upper Half of Register Pair SP + 1 SP + 2 RETI Instruction Stack PC11-PC8 0 SP + 1 PC14PC13PC12 0 PC14PC13PC12 SP + 2 PC3-PC0 SP + 2 PC3-PC0 SP + 3 PC7-PC4 SP + 3 PC7-PC4 SP + 4 ∗ ∗ SP + 4 MBE RBE * SP + 5 ∗ ∗ SP + 6 * PC11-PC8 SP ∗ ∗ SP + 5 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0 SP + 6 PSW except MBE and RBE are not saved/restored. Remarks ∗ means undefined. 35 µPD75237 3.7 PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various types of flags closely related to processor operation. The PSW is mapped at addresses FB0H and FB1H in the data memory space and 4 bits at address FB0H can be operated by the memory manipulation instruction. Normal data memory manipulation instructions cannot be used at address FB1H. Fig. 3-11 Program Status Word Configuration Address FB1H CY SK2 SK1 FB0H SK0 Non-Manipulatable IST1 IST0 MBE Symbol RBE PSW Manipulatable Manipulatable by a Dedicated Instruction Table 3-2 PSW Flag to be Saved/Restored in Stack Operation Flag to be Saved/Restored During CALL/CALLA/CALLF instruction execution MBE and RBE saved Upon hardware interruption All PSW bits saved During RET/RETS instruction execution MBE and RBE restored During RETI instruction execution All PSW bits restored Save Restore 36 µPD75237 (1) Carry flag (CY) The carry flag is a 1-bit flag to store the overflow and underflow generate information when a carry operation instruction (ADDC, SUBC) is executed. It has the bit accumulator function to execute Boolean algebraic operations with the data memory specified by the bit address and to store the result. Carry flag manipulation is carried out using a dedicated instruction irrespective of other PSW bits. When RESET signal is generated, the carry flag becomes undefined. Table 3-3 Carry Flag Manipulation Instructions Instruction (Mnemonic) Carry flag manipulation dedicated instruction SET1 CLR1 NOT1 SKT Bit transfer instruction MOV1 mem* .bit CY MOV1 CY, mem* .bit CY contents transfer to the specified bit Specified bit contents transfer to CY Bit Boolean instruction AND1 CY, mem* .bit OR1 CY, mem* .bit XOR1 CY, mem* .bit Specified bit contents ANDed/ORed/XORed with CY contents and the results set to CY Interrupt service CY CY CY CY Carry Flag Operation and Processing During interrupt execution Parallel save of other PSW bits and 8 bits to the stack memory --------------------------------------------------------------------------------------------------------------------------------------------------RETI Remarks CY set (1) CY clear (0) CY contents invert SKip if CY contents are 1 Restore from the stack memory in parallel to other PSW bits mem*.bit indicates the following three bit manipulated addressing operations. • fmem.bit • pmem.@L • @H + mem.bit (2) Skip flags (SK2, SK1, SK0) The skip flag is used to store the skipped state and is automatically set/reset when the CPU executes an instruction. The user cannot directly operate the skip flags as operands. 37 µPD75237 (3) Interrupt status flags (IST1, IST0) The interrupt status flag is a 2-bit flag to store the status of the processing currently being executed. (Refer to Table 5-3 IST1 and IST0 Interrupt Servicing Statuses for details.) Table 3-4 Interrupt Status Flag Directive Contents IST1 IST0 Status of Processing being Executed 0 0 Status 0 Normal program being executed. All interrupts acknowledgeable. 0 1 Status 1 Low or high interrupt being executed. Only high interrupt acknowledgeable. 1 0 Status 2 High interrupt being executed. All interrupts non-acknowledgeable. 1 1 — Servicing Contents and Interrupt Control Setting disable The interrupt priority control circuit (see Fig. 5-1 Interrupt Control Circuit Block Diagram) identifies the interrupt status flag contents and executes multiple interrupt control. If the interrupt is acknowledged, the IST1 and IST0 contents are saved to the stack memory as part of PSW and are automatically changed to the status higher by one level and the values prior to interruption by RETI instruction are restored. The interrupt status flag can be operated by the memory manipulation instruction and the processing status being executed can be changed by program control. Note 38 Before operating this flag, be sure to disable interruption by executing DI instruction and enable interruption by execution EI instruction after operation. µPD75237 (4) Memory bank enable flag (MBE) This is a 1-bit flag to specify the mode to generate the address information of the most significant 4 bits of the 12 bits of the data memory address. When this flag is set (1), the data memory address space is expanded and all data memory spaces become addressible. When this flag is reset (0), the data memory address space is fixed irrespectively of MBS setting. (See Fig. 2-1 Data Memory Configuration and Addressing Range in Each Addressing Mode.) When RESET input is applied, the bit 7 contents at address 0 of the program memory are set and the MBE is automatically initialized. In vectored interrupt service, the bit 7 contents of the corresponding vector address table are set and the MBE status in the interrupt service is automatically set. Normally, set MBE = 0 for interrupt service and use the static RAM of memory bank 0. (5) Register bank enable flag (RBE) This is a 1-bit flag to determine whether or not the general register bank configuration should be expanded. When this flag is set (1), one general register can be selected from register banks 0 to 3 depending on the register bank select register (RBS) contents. When this flag is reset (0), register bank 0 is selected as a general register irrespective of the register bank select register (RBS) contents. Upon RESET input, the bit 6 contents at address 0 of the program memory are set and the flag is automatically initialized. When a vectored interrupt is generated, the bit 6 contents of the corresponding vector address table are set and the RBE status in interrupt service is automatically set. Normally, set RBE = 0 for interrupt service. Use register bank 0 for 4-bit operation and register banks 0 and 1 for 8-bit operation. 39 µPD75237 3.8 BANK SELECT REGISTER (BS) The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS). The RBS and MBS are used to specify the register bank and the memory bank to be used, respectively. The RBS and MBS are set by SEL RBn and SEL MBn instructions, respectively. The BS can be saved/restored the stack area in 8-bit units by PUSH BS/POP BS instruction. Fig. 3-12 Bank Select Register Configuration Address F82H MBS RBS MBS3 MBS2 MBS1 MBS0 0 0 RBS1 RBS0 Symbol BS (1) Memory bank select register (MBS) The memory bank select register in a 4-bit register to store the most significant 4-bit address information of the data memory address (12 bits) and the memory bank to be accessed is specified by the MBS contents. Banks 0, 1, 2, 3 and 15 can be specified. The MBS is set by SEL MBn instruction. (n = 0, 1, 2, 3, 15) The address range for MBE and MBS setting is shown in Fig. 2-1. Upon RESET input, the MBS is initialized to “0”. (2) Register bank select register (RBS) The register bank select register is used to specify the register bank for use as a general register and can set banks 0 to 3. The RBS is set by SEL RBn instruction. (n = 0 to 3) Upon RESET input, the RBS is initialized to “0”. Table 3-5 RBE, RBS and Register Banks to be Selected RBS Register Bank RBE 0 1 3 2 1 0 0 0 × × Fixed to bank 0 0 0 Bank 0 selected 0 1 Bank 1 selected 1 0 Bank 2 selected 1 1 Bank 3 selected 0 0 Fixed to 0 Remarks 40 × : Don’t care µPD75237 4. PERIPHERAL HARDWARE FUNCTIONS 4.1 DIGITAL INPUT/OUTPUT PORTS The µPD75237 employs the memory mapped I/O and all input/output ports are mapped in the data memory space. Fig. 4-1 Digital Port Data Memory Address Address 3 2 1 0 Symbol FF0H P03 P02 P01 P00 PORT0 FF1H P13 P12 P11 P10 PORT1 FF2H P23 P22 P21 P20 PORT2 FF3H P33 P32 P31 P30 PORT3 FF4H P43 P42 P41 P40 PORT4 FF5H P53 P52 P51 P50 PORT5 FF6H P63 P62 P61 P60 PORT6 FF7H P73 P72 P71 P70 PORT7 FF8H P83 P82 P81 P80 PORT8 FF9H P93 P92 P91 P90 PORT9 FFAH P103 P102 P101 P100 PORT10 FFBH P113 P112 P111 P110 PORT11 FFCH P123 P122 P121 P120 PORT12 FFDH P133 P132 P131 P130 PORT13 FFEH P143 P142 P141 P140 PORT14 FFFH P153 P152 P151 P150 PORT15 41 µPD75237 (1) Digital input/output port configuration The digital input/output port configurations are shown in Figs. 4-2 to 4-11. (2) Input/output mode setting The input/output mode of each input/output port is set by the port mode register as shown in Fig. 4-12. Each port acts as an input when the corresponding port mode register bit is “0” and as an output port when the bit is “1”. Port mode register groups A and B each are set by the 8-bit memory manipulation instruction. Upon RESET input, all bits of each port mode register are cleared to “0”. Thus, the output buffer is turned OFF and all the ports are set to the input mode. (3) Digital input/output port operation The operations of the port and pin for instruction execution vary, depending on the input/output mode setting as shown in Table 4-1. Table 4-1 Input/Output Port Operations for Input/Output Instruction Execution * 42 Input Mode (Corresponding Bit 0 of Mode Register) [Output Buffer OFF] Output Mode (Corresponding Bit 1 of Mode Register) [Output Buffer ON] When 1-bit test instruction, 1-bit input instruction, 4-bit or 8-bit instruction is executed Each pin data input Output latch contents input When 4-bit or 8-bit output instruction is executed Accumulator data transfer to output latch Accumulator data output to output pin When 1-bit output instruction* is executed Output latch contents become undefined Output pin status change according to instruction SET1/CLR1/MOV1 PORTn.bit, CY, etc. µPD75237 Fig. 4-2 Configurations of Port 0, 1 and 8 SI0 SCK0 INT4 SO0 8 CSIM0 P01 Output Latch Selector Internal SCK0 VDD Pull-Up Resistor Selector P-ch Bit 0 of POGA P00/INT4 P01/ SCK0 P02/SO0/SB0 P03/SI0/SB1 Output buffer capable of switching between push-pull output and N-ch open drain output Input Buffer VDD Pull-Up Resistor P-ch Internal Bus Bit 1 of POGA Input Buffer ø or fX/64 Noise Eliminator P10/INT0 P11/INT1 P12/INT2 P13/TI0 TI0 INT2INT1 INT0 Input buffer having hysteresis characteristics Internal 8 SCK1 PPO CSIM1 SI1 SO1 SCK1 P80/PPO P81/ SCK1 P82/SO1 P83/SI1 Input Buffer 43 µPD75237 Fig. 4-3 Port 3n and Port 6n Configurations (n = 0 to 3) VDD PMm n=0 Input Buffer Pull-Up Resistor M Internal Bus P X PMm n=1 Bit m of POGA P-ch Output Buffer Output Latch Pm n PMm n Corresponding Bit of Port Mode Register Group A m = 3, 6 n = 0 to 3 ) ( Fig. 4-4 Port 2 Configuration VDD Pull-Up Resistor P-ch Bit m of POGA Input Buffer PMm=0 M P PMm=1 Internal Bus X Pm0 Pm1 Output Latch Pm2 Pm3 Output Buffer PMm Corresponding Bit of Port Mode Register Group B (m = 2) 44 µPD75237 Fig. 4-5 Configurations of Ports 4 and 5 VDD Pull-Up Resistor Input Buffer PMm=0 Mask Option M PMm=1 Internal Bus P X Pm0 Pm1 Output Latch Pm2 Pm3 N-ch Open Drain Output Buffer PMm Corresponding Bit of Port Mode Register Group B (m = 4, 5) 45 µPD75237 Fig. 4-6 Port 7 Configuration Input Buffer PMm=0 M Internal Bus P X PMm=1 Pm0 Pm1 Output Latch Pm2 Pm3 Output Buffer Mask Option PMm Corresponding Bit of Port Mode Register Group B (m = 7) Pull-Down Resistor Fig. 4-7 Port 9 Configuration Input Instruction Input Buffer Internal Bus P90/AN4 P91/AN5 P92/AN6 P93/AN7 To A/D Converter 46 µPD75237 Fig. 4-8 Configurations of Ports 10 and 11 SK SK /Pm0 P-ch Open Drain Output Buffer SK+1 SK+1 /Pm1 SK+2 SK+2 /Pm2 SK+3 Internal Bus SK+3 /Pm3 Mask Option Pull-Down Resistor Mask Option DSPM 4 VLOAD (Simultaneously specified for S16 to S23) 8 Remarks 1. 2. STATB Port 10: K = 16, m = 10 Port 11: K = 20, m = 11 Fig. 4-9 Configurations of Ports 12 and 13 SK SK /Pm0 P-ch Open Drain Output Buffer SK+1 SK+1 /Pm1 SK+2 SK+2 /Pm2 SK+3 Internal Bus SK+3 /Pm3 Mask Option Pull-Down Resistor 4 DSPM VLOAD 8 Remarks 1. 2. STATA Port 12: K = 0, m = 12 Port 13: K = 4, m = 13 47 µPD75237 Fig. 4-10 Port 14 Configuration P-ch Open Drain Output Buffer Output Buffer S8/P140 M Internal Bus S9/P141 S8 P S9 X S10 S11 S11/T14/P143 * S15 S14 DSPM.3 4 Mask Option (for Each Pin) Pull-Down Resistor STATA 8 DIGS 4 * S10/T15/P142 * VLOAD Selector Fig. 4-11 Configurations of Ports 15 and H Output Buffer P-ch Open Drain Output Buffer * M * P S12 Internal Bus S12/T13/P150/PH0 S13/T12/P151/PH1 * S13 X * S14 S14/T11/P152/PH2 * * S15 * S15/T10/P153/PH3 * PH1PH3 PH0PH2 T12T10 T13T11 Mask Option (for Each Pin) DSPM.3 4 Pull-Down Resistor STATA 8 VLOAD 4 * 48 Selector DIGS µPD75237 Fig. 4-12 Port Mode Register Format Port mode register group A Address FE8H 7 6 5 PM63 PM62 PM61 Symbol PM60 3 PM33 2 1 PM32 PM31 0 PM30 Symbol PMGA P3n and P6n Pin Input/Output Specification (n = 0 to 3) PM3n, PM6n PMGA 4 0 Input mode (output buffer OFF) 1 Output mode (output buffer ON) Port mode register group B Address FECH 7 6 PM7 5 4 PM5 PM4 Symbol Remarks 2 1 0 PM2 Symbol PMGB Port n Input/Output Specification (n = 2, 4, 5, 7) PMn PMGB 3 0 Input mode (output buffer OFF) 1 Output mode (output buffer ON) –––– : 0 or 1 (4) Pull-up resistor register group A (POGA) Pull-up resistor register group A is intended to specify pull-up resistors to be built in ports 0 to 3 and port 6 (except P00). Fig. 4-13 shows the format. Set “1” when a pull-up resistor is incorporated or “0” when it is not incorporated. Fig. 4-13 Pull-Up Resistor Register Group A Format Address FDCH 7 6 PO6 5 4 3 PO3 2 1 PO2 PO1 0 Symbol PO0 POGA Port 0 (P01 to P03) Port 1 (P10 to P13) Port 2 (P20 to P23) Port 3 (P30 to P33) Port 6 (P60 to P63) Note Mask option by which pull-up resistors at ports 4 and 5 and pull-down resistors at port 7 and ports 10 to 15 can be incorporated bit-wise. Remarks –––– : 0 or 1 49 µPD75237 4.2 CLOCK GENERATOR (1) Clock generator configuration The clock generator is a circuit to generate clocks to be supplied to the CPU and the peripheral hardware. Its configuration is shown in Fig. 4-14. Fig. 4-14 Clock Generator Block Diagram • FIP Controller/Driver • Basic Interval Timer • Timer/Event Counter • Serial Interface • Watch Timer • Clock Output Circuit • INT0 Noise Eliminator XT1 XT2 Subsystem Clock Generator f XT Watch Timer Timer/Pulse Generator X1 X2 Mainsystem Clock Generator fX 1/8~1/4096 Frequency Divider Oscillation Stop SCC3 SCC0 Internal Bus Frequency Divider Selector SCC Selector 1/ 1/ 1/ 2 4 16 1/4 Φ • CPU • INT0 Noise Eliminator • Clock Output Circuit PCC PCC0 PCC1 4 HALT F/F HALT * STOP * PCC2 S PCC3 R PCC2 and PCC3 Clear STOP F/F Q Q Wait Release Signal from BT S RESET Signal R * Instruction execution Remarks ★ 50 Standby Release Signal from Interrupt Control Circuit 1. 2. 3. fX = Main system clock frequency fXT = Subsystem clock frequency Φ = CPU clock 4. 5. 6. PCC: Processor clock control register SCC: System clock control register 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in 11. ELECTRICAL SPECIFICATIONS. µPD75237 (2) Clock generator functions The clock generator generates the following clocks and controls the CPU operating modes including the standby mode. • Main system clock : fX • Subsystem clock : fXT • CUP CLOCK : Φ • Clocks for peripheral hardware The following clock generator operations are determined by the processor clock control register (PCC) and the system clock control register (SCC): (a) Upon RESET input, the lowest speed mode (10.7 µ s : at 6.0 MHz operation)*1 of the main system clock is selected. (PCC = 0, SCC = 0) (b) One of the four-level CPU clocks can be selected by setting the PCC with the main system clock selected. (0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs : at 6.0 MHz operation)*2 (c) Two standby modes, the STOP and HALT modes, are available with the main system clock selected. (d) The clock generator can be operated at an ultra-low speed and with low-level power consumption (122 µs : at 32.768 KHz operation) by selecting the subsystem clock with SCC. (e) Main system clock oscilloation can be stopped by SCC with the subsystem clock selected. The HALT mode can also be used but the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.) (f) Divided system clocks are supplied to the peripheral hardware. Subsystem clocks can be directly supplied to the watch timer to that the timer function can be continued. (g) When the subsystem clock is selected, the watch timer can operate normally. However, other hardware cannot be used if the main system clock is stopped. * 1. 2. 15.3 µs : at 4.19 MHz operation 0.95 µs, 1.91 µs, 3.82 µs, 15.3 µs : at 4.19 MHz operation 51 µPD75237 (3) Processor clock control register (PCC) The PCC is a 4-bit register to select the CPU clock Φ with the lower 2 bits and to control the CPU operating mode with the higher 2 bits. (See Fig. 4-15 Processor Clock Control Register Format.) When bit 3 or 2 is set (1), the standby mode is set. If the standby mode is released by the standby release signal, both bits are automatically cleared and the normal operating mode is set. (For details, refer to 6. STANDBY FUNCTIONS.) The lower 2 bits of the PCC are set by the 4-bit memory manipulation instruction (with the higher 2 bits set to “0”). Bits 3 and 2 are reset “1” by the STOP and HALT instructions, respectively. The STOP and HALT instructions can always be executed irrespective of the MBE contents. The CPU clock selection is possible only when operated on the main system clock. When operated on the subsystem clock, the lower 2 bits of PCC are invalidated and fXT/4 is set. The STOP instruction is also enabled only when in operation with the main system clock. RESET input clears PCC to “0”. 52 µPD75237 Fig. 4-15 Processor Clock Control Register Format Address FB3H Symbol 3 2 1 0 PCC3 PCC2 PCC1 PCC0 PCC CPU Clock Select Bit (When fX = 6.0 MHz) SCC = 0 SCC = 1 Values in parentheses are when fx = 6.0 MHz Values in parentheses are when fXT = 32.768 kHz CPU Clock Frequency 1 Machine Cycle CPU Clock Frequency 1 Machine Cycle Φ = fXT/4 (8.192 kHz) 122 µs 0 0 Φ = fX/64 (93.7 kHz) 10.7 µs 0 1 Φ = fX/16 (375 kHz) 2.67 µs 1 0 Φ = fX/8 (750 kHz) 1.33 µs 1 Φ = fX/4 (1.5 MHz) 0.67 µs 1 Setting prohibited Φ = f XT/4 (8.192 kHz) 122 µs (When fX = 4.19 MHz) SCC = 0 Values in parentheses are when fx = 4.19 MHz CPU Clock Frequency 1 Machine Cycle CPU Clock Frequency 1 Machine Cycle Φ = fXT/4 (8.192 kHz) 122 µs 0 0 Φ = fX/64 (65.5 kHz) 15.3 µs 0 1 Φ = fX/16 (262 kHz) 3.81 µs 1 0 Φ = fX/8 (524 kHz) 1.91 µs 1 1 Φ = fX/4 (1.05 MHz) 0.95 µs Remarks SCC = 1 Values in parentheses are when fXT = 32.768 kHz 1. 2. Setting prohibited Φ = fXT/4 (8.192 kHz) 122 µs fX : Main system clock oscillator output frequency fXT : Subsystem clock oscillator output frequency CPU Operating Mode Control Bit 0 0 Normal operating mode 0 1 HALT mode 1 0 STOP mode 1 1 Setting prohibited 53 µPD75237 (4) System clock control register (SCC) The SCC is a 4-bit register to select the CPU clock Φ with the least significant bit and to control main system clock oscillation stop with the most significant bit (refer to Fig. 4-16). Although SCC.0 and SCC.3 are located at the same data memory address, both bits cannot be changed simultaneously. Thus, SCC.0 and SCC.3 are set by the bit manipulation instruction. SCC.0 and SCC.3 can always be bit manipulated irrespective of the MBE contents. Main system clock oscillation can be stopped by setting SCC.3 only when in operation with the subsystem clock. Oscillation when in operation with the main system clock is stopped by the STOP instruction. RESET input clears SCC to “0”. Fig. 4-16 System Clock Control Register Format Address Symbol 3 FB7H SCC3 2 1 0 SCC0 SCC System Clock Selection SCC3 SCC0 0 0 Main system clock 0 1 Subsystem clock 1 0 1 1 Main System Clock Oscillation Oscillation enabled Note Setting prohibited Subsystem clock Oscillation stop 1. A maximum of 1/fXT is required to change the system clock. Thus, when stopping the main system clock oscillation, change the clock to the subsystem clock and set SCC.3 following the passage of more than the machine cycles described in Table 4-2. 2. The normal STOP mode cannot be set if oscillation is stopped by setting SCC.3 while in operation with the main system clock. 3. If SCC.3 is set to “1”, X1 input is internally short-circuited to VSS (GND potential) to suppress crystal oscillator leakage. Thus, when using an external clock for the main system clock do not set SCC.3 to “1”. 4. When PCC = 0001B (Φ = f X/16 selected), do not set SCC.0 to “1”. When switching from the main system clock to the subsystem clock, do so after setting PCC to another value (PCC ≠ 0001B). Do not set PCC = 0001B while in operation with the subsystem clock. 54 µPD75237 (5) System clock oscillator The main system clock oscillator oscillates with a crystal resonator (with a standard frequency of 6.0 MHz) or a ceramic resonator connected to the X1 and X2 pins. External clocks can be input to this oscillator. Fig. 4-17 External Circuit of Main System Clock Oscillator (a) Crystal/ceramic Oscillation (b) External clock µPD75237 µPD75237 External Clock X1 X1 X2 X2 Crystal or Ceramic Resonator Note The STOP mode cannot be set while an external clock is input because the X1 pin is short-circuited to VSS in the STOP mode. The subsystem clock oscillator oscillates with a crystal resonator (with a standard frequency of 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to this oscillator. Fig. 4-18 External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock µPD75237 XT1 µPD75237 External Clock XT1 32.768 kHz Leave open XT2 XT2 Note When using a main system clock and subsystem clock oscillator, wire the crosshatched section in Figs. 4-17 and 4-18 as follows to prevent any effect of the wiring capacity. • Make the wiring as short as possible. • Do not allow wiring to intersect with other signal conductors. Do not allow wiring to be near a line through which varying high current flows. • Set the oscillator capacitor grounding point to the same potential as that of VSS. Do not ground to a ground pattern through which high current flows. • Do not fetch signals from the oscillator. The subsystem clock oscillator has a low amplification factor to maintain low current consumption and is more likely to malfunciton due to noise than the main system clock oscillator. Thus, take extra care when using a subsystem clock. 55 µPD75237 (6) Time required for system clock and CPU clock switching The system clock and the CPU clock can be switched to each other with the least significant bit of the SCC and the lower 2 bits of the PCC. This switching is not executed just after register rewrite and operation continues with the previous clock during the specified machine cycle. Thus, to stop main system clock oscillation, it is necessary to execute the STOP instruction or to set SCC.3 after the specified switching time. Table 4-2 Maximum Time Required for System Clock and CPU Clock Switching Set Value before Switching Set Value after Switching SCC PCC PCC 0 1 0 0 0 0 1 4 machine cycle 1 0 8 machine cycle 8 machine cycle 1 1 16 machine cycle 16 machine cycle 16 machine cycle × × 1 machine cycle Setting prohibited 1 machine cycle SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 0 0 0 0 0 1 1 machine cycle 0 1 0 0 1 1 1 machine cycle 1 machine cycle 4 machine cycle 4 machine cycle Setting prohibited 8 machine cycle fX machine cycle 8fXT (23 machine cycle) 0 1 Remarks Note fX machine cycle 4fXT (64 machine cycle) 1 machine cycle 1. CPU clock Φ is a clock to be supplied to the internal CPU of µPD75237 and its inverse number is the minimum instruction time (defined as “one machine cycle” in this manual). 2. Values in parentheses are when fX = 6.0 MHz and fXT = 32.768 kHz. When PCC = 0001B (Φ = fX/16 selected), do not set SCC.0 to “1”. When switching from the main system clock to the subsystem clock, do so after setting PCC to another value (PCC ≠ 0001B). Do not set PCC = 0001B while in operation with the subsystem clock. 56 1 × × fX machine cycle 64fXT (3 machine cycle) µPD75237 (7) System clock and CPU clock switching procedure System clock and CPU clock switching is described referring to Fig. 4-19. Fig. 4-19 System Clock and CPU Clock Switching ON Commercial Power Supply OFF VDD Pin Voltage RES Signal Wait 21.8 ms [31.3 ms] System Clock CPU Clock fX fX 10.7 µs [15.3 µs] 0.67 µs [0.95 µs] fXT 122 µs fX 0.67 µs [0.95 µs] Internal Reset Operation Remarks MHz , values in brackets are when f ( ff =6.0 =32.768 kHz ) X X = 4.19 MHz. XT ➀ RESET input starts the CPU at the lowest speed (21.8 ms : at 6.0 MHz operation)*1 of the main system clock after the wait time (10.7 µ s : at 6.0 MHz operation)*2 for maintaining the oscillation stabilize time. ➁ The CPU rewrites the PCC and operates at its maximum available speed after the lapse of sufficient time for the VDD pin voltage to increase to a voltage allowing the highest speed operation. ➂ The CPU detects commercial power-off from the interrupt input (INT4 is effective), sets SCC.0 and operates with the subsystem clock. (At this time, subsystem clock oscillation must have started beforehand. ) After the passage of time required for the CPU clock to switch to the subsystem clock (32 machine cycles), the CPU sets SCC.3 to stop main system clock oscillation. 4 After the CPU detects the commercial power restored from the interrupt, it clears SCC.3 and starts main system clock oscillation. Following the passage of time required for oscillation stabilization, the CPU clears SCC.0 and operates at its highest speed. * 1. 2. 31.3 ms at 4.19 MHz operation 15.3 µs at 4.19 MHz operation 57 µPD75237 4.3 CLOCK OUTPUT CIRCUIT (1) Clock output circuit configuration The clock output circuit is configured as shown in Fig. 4-20. (2) Clock output circuit functions The clock output circuit is intended to generate clock pulses from the P22/PCL pin. It is used for remotecontrolled output or clock pulse supply to the peripheral LSI. Follow the procedure below to generate clock pulses. (a) Select the clock output frequency. Do not output clocks. (b) Write 0 to P22 output latch. (c) Set the port 2 input/output mode to ‘output’. (d) Enable clock output. Fig. 4-20 Clock Output Circuit Configuration From Clock Generator Φ Output Buffer f x /23 Selector f x /24 PCL/P22 6 f x /2 PORT2.2 CLOM 3 CLOM CLOM CLOM 1 0 0 P22 Output Latch PMGB Bit 2 Port 2 Input/ Output Mode Specification Bit 4 Internal Bus Remarks 58 The clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable. µPD75237 (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. Data cannot be read from the CLOM. CPU clock Φ output from PCL/P22 pin SEL MB15 ; Or CLR1 MBE MOV A, #1000B Example MOV CLOM, A RESET input clears the CLOM to 0 and disables clock output. Fig. 4-21 Clock Output Mode Register Format Address FD0H Symbol 3 2 CLOM3 0 1 0 CLOM 1 CLOM0 CLOM Clock Output Frequency Select Bit (When fX = 6.0 MHz) 0 0 Φ output* (1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz) 0 1 fX/23 output (750 kHz) 1 0 fX/24 output (375 kHz) 1 1 fX/26 output (93.7 kHz) (When fX = 4.19 MHz) 0 0 Φ output* (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz) 0 1 fX/23 output (524 kHz) 1 0 fX/24 output (262 kHz) 1 1 fX/26 output (65.5 kHz) * Φ is a CPU clock to be selected by PCC. Clock Output Enable/Disable Bit Note 0 Output disabled 1 Output enabled Be sure to write “0” to bit 2 of CLOM. 59 µPD75237 (4) Example of application to remote-controlled output The clock output function of the µPD75237 can be applied to remote-controlled output. The carrier frequency of remote-controlled output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled/disabled by controlling the clock output enable/disable bit by software. The clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable. Fig. 4-22 Remote-Controlled Output Application Example CLOM.3 PCL Pin Output 60 µPD75237 4.4 BASIC INTERVAL TIMER (1) Basic interval timer configuration The basic interval timer configuration is shown in Fig. 4-23. (2) Basic interval timer functions The basic interval timer has the following functions: (a) Interval timer operation to generate reference time (at any of four time intervals) (b) Watchdog timer application to detect inadvertent program loop (c) Wait time select and count upon standby mode release (d) Count contents read Fig. 4-23 Basic Interval Timer Configuration From Clock Generator Clear Clear f x /25 f x /27 Set Basic Interval Timer (8-Bit Freqency Divider) MPX 9 f x /2 BT f x /212 BT Interrupt Request Flag IRQBT Vectored Interrupt Request Signal 3 BTM3 SET1* BTM2 BTM1 4 BTM0 Wait Release Signal upon Standby Mode Release BTM 8 Internal Bus * Instruction execution 61 µPD75237 (3) Basic interval timer mode register (BTM) The BTM is a 4-bit register to control basic interval timer operations. The BTM is set by a 4-bit memory manipulation instruction. Bit 3 can be set independently by a bit manipulation instruction. When bit 3 is set “1”, the basic interval timer contents and the basic interval timer interrupt request flag (IRQBT) are simultaneously cleared (basic interval timer start). RESET input clears the contents to “0” and sets the interrupt request signal generation interval time to its maximum value. Fig. 4-24 Basic Interval Timer Mode Register Format Address F85H Symbol 3 2 1 0 BTM3 BTM2 BTM1 BTM0 BTM (When f X = 6.0 MHz) Input Clock Specification Interrupt Interval Time (Wait time upon standby mode release) 0 0 0 fX /212 (1.46 kHz) 220/fX (175 ms) 0 1 1 fX/29 (11.7 kHz) 217/fX (21.8 ms) 1 0 1 fX/27 (46.9 kHz) 215/fX (5.46 ms) 1 1 1 fX/25 (188 kHz) 213/fX (1.37 ms) In all other cases Setting prohibited (When fX = 4.19 MHz) Input Clock Specification Interrupt Interval Time (Wait time upon standby mode release) 0 0 0 fX /212 (1.02 kHz) 220/fX (250 ms) 0 1 1 fX/29 (8.18 kHz) 217/fX (31.3 ms) 1 0 1 fX/27 (32.768 kHz) 215/fX (7.82 ms) 1 1 1 fX/25 (131 kHz) 213/fX (1.95 ms) In all other cases Setting prohibited Basic Interval Timer Start Control Bit The basic interval timer is started (counter and interrupt request flag clear) by writing “1”. When the timer starts operating, it is automatically reset to “0”. 62 µPD75237 (4) Basic interval timer operation The basic interval timer (BT) is always incremented by clocks from the clock generator and sets the interrupt request flag (IRQBT) due to an overflow. BT count operation cannot be stopped. Four interrupt generate intervals are available by setting the BTM (refer to Fig. 4-24 Basic Interval Timer Mode Register Format). The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of the BTM (1) (interval timer start instruction). The count state can be read from the basic interval timer (BT) by the 8-bit manipulation instruction. Data cannot be written to the BT. Note When reading the basic interval timer count contents, execute the read instruction twice and compare the two read contents so as not to read unstable data undergoing count update. If the two values are both acceptable, use the second read value as the correct one. If they differ completely, execute reading again from the beginning. To obtain the oscillation stabilize time from STOP mode release to system clock oscillation stabilization, the wait function is available to stop CPU operation until the basic interval timer overflows. Wait time after RESET input is fixed, however, if the STOP mode has been released by interrupt generation, the wait time can be selected by BTM setting. In that case, the wait time is equal to the interval time shown in Fig. 4-24. BTM setting must be done before STOP mode setting. (For details, refer to 6 . STANDBY FUNCTIONS.) 4.5 TIMER/EVENT COUNTER (1) Timer/event counter functions The timer/event counter has the following functions. (a) (b) (c) (d) Program interval timer operation Output of square wave with any frequency to PTO0 pin Event counter operation Output of N-divided TI0 pin input to PTO0 pin (frequency divider operation) (e) Serial shift clock supply to the serial interface circuit (f) Count state read function 63 64 Fig. 4-25 Timer/Event Counter Block Diagram Internal Bus 8 SET1*1 TM07TM06 TM05 TM04 TM03TM02 — TM0 8 8 TMOD0 TOE0 TO Enable Flag Modulo Register (8) — PORT2.0 P20 Output Latch PGMB Bit 2 Port 2 Input /Output Mode 8 PORT1.3 To Serial Interface Match Comparator (8) Input Buffer TOUT F/F Reset 8 T0 *2 P13/TI0 From Clock Generator Count Register (8) CP MPX Output Buffer ( INTT0 IRQT0 Set Signal ) Clear Timer Operation Start Event Counter #1 (Refer to Fig. 4-26) * 1. 2. P20/PTO0 RESET IRQT0 IRQT0 Clear Signal Instruction execution P13/TI0 pin is an external event pulse input pin which serves as timer/event counter and event counter. µPD75237 µPD75237 (2) Timer/event counter mode register (TMO) and timer/event counter output enable flag (TOE0) The timer/event counter mode register (TM0) is an 8-bit register to control the timer/event counter and is set by an 8-bit memory manipulation instruction. Fig. 4-27 shows the timer/event counter mode register format. Bit 3 is a timer start command bit which can be set independently. When the timer starts operating, this bit is automatically reset to “0”. RESET input clears all bits of the TM0 to 0. The timer/event counter output enable flag (TOE0) controls enable/disable for output to the PTO0 pin in the timer out F/F (TOUT F/F) state. Fig. 4-26 shows the timer/event counter output enable flag format. The timer out F/F (TOUT F/F) is an F/F which is reversed by a match signal transmitted from the comparator. The timer out F/F is reset by an instruction which sets bit 3 of the TM0. RESET input clears TOE0 and TOUT F/F to 0. Fig. 4-26 Timer/Event Counter Output Enable Flag Format Address FA2H 3 TOE0 Timer/Event Counter Output Enable Flag 0 Disabled 1 Enabled 65 µPD75237 Fig. 4-27 Timer/Event Counter Mode Register Format Address FA0H 7 6 5 TM06 TM05 4 TM04 3 TM03 2 1 Symbol 0 TM02 TM0 Operating Mode Count operation 0 Stop (with count contents held) 1 Count operation Timer Start Command Bit Writing “1” clears the counter and IRQT0 flag. If bit 2 has been set to "1", the counter operation starts. Count Pulse (CP) Select Bit (When fX = 6.0 MHz) TM06 TM05 TM04 Count Pulse (CP) 0 0 0 TI0 input rising edge 0 0 1 TI0 input falling edge 1 0 0 fX/210 (5.86 kHz) 1 0 1 fX/28 (23.4 kHz) 1 1 0 fX/26 (93.8 kHz) 1 1 1 fX/24 (375 kHz) In all other cases Setting prohibited (When fX = 4.19 MHz) TM06 TM05 TM04 Count Pulse (CP) 0 0 0 TI0 input rising edge 0 0 1 TI0 input falling edge 1 0 0 fX/210 (4.09 kHz) 1 0 1 fX/28 (16.4 kHz) 1 1 0 fX/26 (65.5 kHz) 1 1 1 fX/24 (262 kHz) In all other cases 66 Setting prohibited µPD75237 (3) Timer/event counter operating modes The count operation stop mode and the count operating mode are available by setting the mode register for the timer/event counter operation. The following operations are enabled irrespective of the mode register setting: (a) (b) (c) (d) TI0 pin signal input and test (Dual-function pin P13 input testable) Output of the timer out F/F state to PTO0 Modulo register (TMOD0) setting Count register (T0) read (e) Interrupt request flag (IRQT0) set/clear/test (a) Count operation stop mode When TM0 bit 2 is 0, this mode is set. In this mode, count operation is not carried out because count pulse (CP) supply to the count register is stopped. (b) Count operating mode When TM0 bit 2 is 1, this mode is set. The count pulse selected by bits 4 to 6 is supplied to the count register and the count operation shown in Fig. 4-28 is carried out. The timer operation is normally started by the following operations in the described order. ➀ Set the number of counts to the modulo register (TMOD0). ➁ Set the operating mode, count clock and start command to the mode register (TM0). Set the modulo register by an 8-bit data transfer instruction. Fig. 4-28 Operation in Count Operating Mode TI0 Internal Clock INTT0 (IRQT0 Set Signal) { MPX CP Count Register (T0) Clear Comparator Match TOUT F/F PTO0 Modulo Register (TMOD0) To Serial Interface (Channel 0) 67 µPD75237 (4) Timer/event counter time setting [Timer set time] (cycle) is obtained by dividing [Modulo register contents + 1] by [Count pulse frequency] selected by timer mode register setting. T (sec) = n+1 fCP (n + 1) • (Resolution) = T (sec) : Timer set time (sec) fCP (Hz) : Count pulse frequency (Hz) n : Modulo register value (n ≠ 0) Once the timer is set, an interrupt request signal (IRQT0) is generated at the set intervals. Table 4-3 shows the resolutions with each count pulse of the timer/event counter and the maximum set time (with FFH set to the modulo register). Table 4-3 Resolution and Maximum Set Time (When f X = 6.0 MHz) Mode Register TM06 TM05 TM04 Timer Channel 0 Resolution Maximum Set Time 1 0 0 171 µs 43.7 ms 1 0 1 42.7 µs 10.9 ms 1 1 0 10.7 µs 2.73 ms 1 1 1 2.67 µs 683 µs (When fX = 4.19 MHz) Mode Register TM06 TM05 TM04 68 Timer Channel 0 Resolution Maximum Set Time 1 0 0 244 µs 62.5 ms 1 0 1 61.1 µs 15.6 ms 1 1 0 15.3 µs 3.91 ms 1 1 1 3.81 µs 977 µs µPD75237 4.6 (1) WATCH TIMER Watch timer The µPD75237 incorporates one channel of watch timer having a configuration shown in Fig. 4-29. (2) Watch timer functions (a) Sets the test flag (IRQW) at 0.5-sec intervals. The standby mode can be released by IRQW. (b) (c) (d) (e) 0.5-second interval can be set with the main system clock (4.19 MHz) or subsystem clock (32.768 kHz). The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. The fixed frequencies (2.048 kHz, 4.096 kHz and 32.768 kHz) can be output to the P23/ BUZ pin for use to generate buzzer sound and trim the system clock oscillator frequency. Since the frequency divider can be cleared, the watch can be started from zero second. Fig. 4-29 Watch Timer Block Diagram fW (256 Hz : 3.91 ms) 27 From Clock Generator fX 128 (32.768 kHz) Selector fW (32.768 kHz) fW 8 fXT (32.768 kHz) Frequency Divider fW 16 (4.096 kHz) fW 214 ( Selector INTW IRQW Set Signal ) ( 20.5Hzsec) Clear Selector Output Buffer P23/BUZ WM WM7 Bit 2 of PMGB PORT2.3 0 WM5 WM4 0 WM2 WM1 WM0 P23 Output Latch Port 2 Input/ Output Mode 8 Internal Bus Remarks Note Values at fX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses. In the main system clock 6.0 MHz operation, 0.5-second interval can be generated. Therefore, after switching to the subsystem clock, 0.5-second interval should be generated. 69 µPD75237 (3) Watch mode register (WM) The watch mode register (WM) is an 8-bit register to control the watch timer. Its format is shown in Fig. 4-30. The watch mode register is set by an 8-bit memory manipulation instruction. RESET input clears all bits to “0”. Fig. 4-30 Watch Mode Register Format 7 6 5 4 3 WM7 0 WM5 WM4 0 Address F98H 2 WM2 1 0 WM1 WM0 Count Clock (fW) Select Bit fX selected 128 0 System clock divided output: 1 Subsystem clock: fXT selected WM0 Operating Mode Select Bit 0 Normal watch mode ( 1 Fast watch mode ( fW 27 WM1 fW 214 : IRQW set at 0.5 sec : IRQW set at 3.91 ms ) Watch Operation Enable/Disable Bit 0 Watch operation stopped (frequency divider clear) 1 Watch operation enabled WM2 BUZ Output Frequency Select Bit BUZ Output Frequency WM5 WM4 0 0 fW/24 (2.048 kHz) 0 1 fW/23 (4.096 kHz) * 1 0 Setting prohibited 1 1 fW (32.768 kHz) * * Not supported with IE-75000-R BUZ Output Enable/Disable Bit 0 BUZ output disabled 1 BUZ output enabled WM7 70 ) Symbol WM µPD75237 4.7 TIMER/PULSE GENERATOR (1) Timer/pulse generator functions The µPD75237 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. The timer/pulse generator has the following functions. * (a) Functions available in the timer mode • 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels • Square wave output to PPO pin (b) Functions available in the PWM pulse generate mode • 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) 15 • Interrupt generation of fixed time interval ( 2 = 5.46 ms : at 6.0 MHz operation) * fX 7.81 ms at 4.19 MHz operation If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. 71 µPD75237 (2) Timer/pulse generator mode register (TPGM) The timer/pulse generator mode register (TPGM) is an 8-bit register to control timer/pulse generator operations. Its format is shown in Fig. 4-31. The TPGM is set by the 8-bit memory manipulation instruction. Bit 3 enables or disables the timer/pulse generator modulo register (MODH, MODL) contents to be transferred (reloaded) to the modulo latch and can be manipulated individually. The timer/pulse generator operation can be stopped and current consumption can be decreased by setting the TPGM1 to “0”. RESET input clears all bits to “0”. Fig. 4-31 Timer/Pulse Generator Mode Register Format Address F90H 7 6 5 TPGM7 — TPGM5 4 3 2 TPGM4 TPGM3 0 Timer/Pulse Generator Operating Mode Select Bit 0 PWM pulse generate mode selected 1 Timer mode selected TPGM0 Timer/Pulse Generator Operation Enable/Disable Bit 0 Timer/pulse generator operation stopped 1 Timer/pulse generator operation enabled TPGM1 Modulo Register Reload Enable/Disable Bit 0 Modulo register reload disabled 1 Modulo register reload enabled TPGM3 PPO Output Latch Data 0 Output 0 to PPO output latch 1 Output 1 to PPO output latch TPGM4 PPO Pin Output Select Bit Static/Pulse 0 Static output from PPO pin 1 Pulse (square wave/PWM) output from PPO pin TPGM5 PPO Pin Output Enable/Disable Bit 0 PPO pin output disabled (high impedance) 1 PPO pin output enabled TPGM7 72 1 0 TPGM1 TPGM0 Symbol TPGM µPD75237 (3) Configuration and operation for use in the timer mode The timer/pulse generator configuration for use in the timer mode is shown in Fig. 4-32. The timer mode is selected by setting TPGM bit 0 to “1”. In the timer mode, enable modulo register reload by setting TPGM3 to “1”. In the timer mode, select the prescalar with modulo register L (MODL) and set the frequency or interrupt interval set value to modulo register H (MODH). Start the timer by resetting the TPGM1 from 0 to 1. The operation timing for MODH setting is shown in Fig. 4-33 and the frequency or interrupt interval setting is shown in Table 4-4. Square wave output or static output to the PPO pin can be switched. In the case of square wave output, set TPGM5 to “1” and TPGM7 to “1”. Fig. 4-32 Block Diagram of Timer/Pulse Generator (Timer Mode) Internal Bus 8 8 MODL Modulo Register L (8) MODH Modulo Register H (8) TPGM3 (Set to "1") ( Modulo Latch H (8) 8 ) Output Buffer Match Comparator (8) INTTPG IRQTPG Set Signal T F/F Selector PPO Frequency Divider fX 1/2 TPGM1 CP Prescalar Select Latch (5) Clear Note Set 8 Count Register (8) TPGM4TPGM5 TPGM7 Clear If the timer is stopped in the timer operating mode, the IRQTPG may be set because the T F/F is set. Thus, when stopping the timer, do so with interruption disabled, and after the timer has stopped, clear the IRQTPG. 73 µPD75237 Fig. 4-33 Timer Mode Operation Timing CP MODH N Count Register 0 1 2 N-1 N 0 N 0 N 0 T F/F (PPO) TPGM1 Set IRQTPG Generated Table 4-4 Modulo Register Setting (When fX = 6.0 MHz) MODL Bits 2 to 6 Interrupt Generate Interval Square Wave Output Frequency (fX = 6.0 MHz) (fX = 6.0 MHz) 6 5 4 3 2 0 0 0 0 1 256( N+1) = 85.3 µs to 10.9 ms fX fX 256( N+1) 0 0 0 1 0 128( N+1) = 42.7 µs to 5.45 ms fX fX = 183 Hz to 23.4 kHz 128( N+1) 0 0 1 0 0 64( N+1) fX = 21.3 µs to 2.73 ms fX 64( N+1) 0 1 0 0 0 32( N+1) fX = 10.7 µs to 1.37 ms 1 0 0 0 0 16( N+1) fX = 5.33 µs to 683 µs fX 32( N+1) fX 16( N+1) = 91.6 Hz to 11.7 kHz = 366 Hz to 46.9 kHz = 732 Hz to 93.8 kHz = 1465 Hz to 188 kHz (When fX = 4.19 MHz) MODL Bits 2 to 6 Note Interrupt Generate Interval (fX = 4.19 MHz) 6 5 4 3 2 0 0 0 0 1 256( N+1) = 122 µs to 15.6 ms fX fX 256( N+1) 0 0 0 1 0 128( N+1) = 61.0 µs to 7.81 ms fX fX = 128 Hz to 16 kHz 128( N+1) 0 0 1 0 0 64( N+1) fX = 30.5 µs to 3.91 ms fX 64( N+1) 0 1 0 0 0 32( N+1) fX = 15.3 µs to 1.95 ms 1 0 0 0 0 16( N+1) fX = 7.63 µs to 977 µs fX 32( N+1) fX 16( N+1) = 64 Hz to 8 kHz = 256 Hz to 32 kHz = 512 Hz to 65 kHz = 1024 Hz to 131 kHz 1. Only the above values can be set to MODL. Be sure to set “0” to bits 0, 1 and 7. 2. N is the MODH set value. “0” cannot be set to N. Be sure to set a value in the range from 1 to 255 to N. 74 Square Wave Output Frequency (fX = 4.19 MHz) µPD75237 (4) Configuration and operation for use in the PWM pulse generate mode The timer/pulse generator for use in the PWM pulse generate mode is shown in Fig. 4-34. The PWM pulse generate mode is selected by setting TPGM0 to “0”. Pulse output is enabled by setting TPGM5 and TPGM7 to “1”. In the PWM mode, PWM pulse can be output from the PPO pin and the IRQTPG can be set at the fixed interval (215/fX = 5.46 ms : at 6.0 MHz operation)*1. The PWM pulse generated by the µPD75237 is an active-low, 14-bit accuracy pulse. This pulse is converted to an analog voltage by integrating it using an external low-pass filter and can be applied for electronic tuning and DC motor control. (Refer to Fig. 4-35 Example of D/A Conversion Configuration with µPD75237.) The PWM pulse is generated by combining the fundamental period determined by 210/fX (171 µs: at 6.0 MHz operation)*2 and the sub period of 215/fX (5.46 ms: at 6.0 MHz operation)*1 and the time constant of the external low-pass filter can be shortened. The low-level width of the PWM pulse is determined by the 14-bit modulo latch value. The modulo latch value is determined as a result of transfer of MODH 8 bits to the most significant 8 bits of the modulo latch and MODL most significant 6 bits to the least significant 6 bits of the modulo latch. The digital-to analog converted output voltage is given as VAN = Vref × Modulo latch value 2 14 where Vref : External switching circuit reference voltage In the µPD75237, all 14 bits can be transferred simultaneously to the modulo latch after correct data has been written to MODH and MODL by the 8-bit manipulation instruction. This aims at preventing the PWM from being generated with an unstable value in the process of modulo latch rewrite. This transfer is called “reload” and is controlled by TPGM3. Note 1. Setting “0” to modulo register H (MODH) disables the PWM pulse generator to operate normally. Be sure to set to MODH a value in the range from 1 to 255. 2. When the least significant 2 bits of modulo register L (MODL) are read, an undefined value is read. 3. The fundamental period of the PWM pulse is 210/fX (171 µs: at 6.0 MHz operation)*2. If the module latch is changed with a shorter period, the PWM pulse remains unchanged. * 1. 2. 7.81 ms at 4.19 MHz operation 244 µs at 4.19 MHz operation (5) Static output to the PPO pin If pulse output is not necessary, the PPO pin can be used for normal static output. In this case, set output data to TPGM4 with TPGM5 and TPGM7 set to “0” and “1”, respectively. 75 µPD75237 Fig. 4-34 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode) Internal Bus 8 8 MODH MODL Modulo Register L (6) Modulo Register H (8) (2) TPGM3 MODH (8) MODL7-2 (6) Modulo Latch (14) Output Buffer TPGM1 fx PWM Pulse Generator Selector PPO 1/2 Frequency Divider INTTPG (IRQTPG Set Signal) ( * 7.81 ms at 4.19 MHz operation TPGM5 TPGM7 215 =5.46 ms : at 6.0 MHz operation) * fX Fig. 4-35 Example of D/A Conversion Configuration with µPD75237 µPD75237 V ref PWM PPO 76 Signal Switching Circuit Low-Pass Filter V AN (Analog Voltage) µPD75237 4.8 EVENT COUNTER (1) Event counter configuration The event counter of the µPD75237 incorporates a noise eliminator and has a configuration shown in Fig. 4-36. Fig. 4-36 Event Counter Block Diagram Selector TI0/P13 TM1.4 Noise Eliminator Selector GATEC.0 Timer/Counter #0 fx 4 8-Bit Counter TM1.2 Overflow Flag T1 IRQT1 Internal Bus Note (2) TI0/P13 pin is an external event pulse input pin which serves as timer/event counter #0 and event counter #1. Event counter functions The event counter has the following functions. (a) Event counter operation (b) (c) (d) Count state read function Count pulse edge specification Noise eliminating function 77 µPD75237 (3) Event counter mode register The event counter mode register (TM1) is an 8-bit register to control the event counter. Its format is shown in Fig. 4-37. TM1 is set by an 8-bit memory manipulation instruction. Bit 3 is an event counter start bit and can be set independently. When the counter starts operating, bit 3 is automatically reset to “0”. Fig. 4-37 Event Counter Mode Register Format Address 7 6 5 4 3 2 FA8H 0 0 0 TM14 TM13 TM12 1 0 Symbol 0 0 TM1 Event Count Operation Enable/Disable Bit 0 Count operation stopped (with count value held) 1 Count operation enabled TM12 Event Counter Start Command Bit TM13 Writing "1" clears the counter and IRQT1 flag. operation starts. If TM12 is "1", count Count Pulse Edge Specification 0 TI0 input rising edge 1 TI0 input falling edge TM14 (4) Overflow flag (IRQT1) The overflow flag is a flag which is set (1) by an overflow of the event counter count register and is cleared (0) by a count operation start command. (5) Event counter control register (GATEC) This is a register to select sampling with a sampling clock (fX/4). A pulse having a smaller width than that of two sampling clock cycles (8/fX) is eliminated as noise by a noise eliminator and a pulse having a width larger than that of the sampling clock is securely acknowledged as an interrupt signal. Its format is shown in Fig. 4-38. Fig. 4-38 Event Counter Control Register Format 78 Address 3 2 1 0 Symbol FABH 0 0 0 GATEC0 GATEC 0 No sampling 1 Sampling by fX/4 µPD75237 4.9 SERIAL INTERFACE The µPD75237 incorporates two channels of clocked 8-bit serial interfaces. Table 4-5 gives differences between channel 0 and channel 1. Table 4-5 Differences between Channels 0 and 1 Serial Transfer Mode and Function Clock selection Channel 0 fX/24 , fX/23 , TOUT F/F, external clock 3-wire serial I/O Transfer mode MSB first/LSB first switchable Transfer end flag 2-wire serial I/O Serial transfer end interrupt request flag (IRQCSI0) Use enabled Channel 1 fX/24, fX/23, external clock MSB first Serial transfer end flag (EOT) None Serial bus interface 79 µPD75237 (1) Serial interface (channel 0) functions The following four modes are available for the µPD75237 serial interface (channel 0). The functions of each mode are outlined below. • Operation stop mode This is the mode used when no serial transfer is performed. Low power consumption operation is possible in this mode. • 3-wire serial I/O mode 8-bit data is transferred using three lines of serial clock (SCK0), serial output (SO0) and serial input (SI0). The 3-wire serial I/O mode enables simultaneous transmission/reception, thus shortening the data transfer processing time. Since the start bit of 8-bit data for serial transfer can be switched between MSB and LSB, channel 0 can be connected to a device having either start bit. In the 3-wire serial I/O mode, channel 0 can be connected to the 75X series, 78K series and various types of peripheral I/O devices. • 2-wire serial I/O mode 8-bit data is transferred using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). Communication is possible with two or more devices by controlling the level of output to the two lines by software. Since the output level of SCK0 and SB0 (or SB1) can be controlled by software, any transfer format is applicable. Thus, the number of handshake lines previously required to connect two or more devices can be decreased and so the input/output ports can be used efficiently. • SBI mode (serial bus interface mode) This mode enables communication with two or more devices with two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode is compliant with the NEC serial bus format. In the SBI mode, the transmitter can output an “address” for selection of a serial communication target device on the serial data bus, a “command” to provide instructions to the target device and actual “data”. The receiver can distinguish between “address”, “command” and “data” by hardware. As in the 2wire serial I/O mode, this function enables the input/output ports to be used efficiently and the serial interface control portions of any applied program to be simplified. (2) 80 Serial interface (channel 0) configuration Fig. 4-39 is a block diagram of serial interface (channel 0). Fig. 4-39 Serial Interface (Channel 0) Block Diagram Internal Bus CSIM0 8 8 8 Slave Address Register (SVA) Address Comparator Bit Manipulation SBIC (8) Match Signal (8) RELT CMDT SO0 SET CLR Latch P03/SI0/SB1 Shift Register 0 (SIO0) (8) D Q ACKT Selector Bit Test Selector P02/SO0/SB0 ACKE BSYE 8/4 Bit Test Busy /Acknowledge Output Circuit Bus Release /Command /Acknowledge Detector RELD CMDD ACKD INTCSI0 P01/SCK0 Serial Clock Counter INTCSI0 INTCSI0 Control Circuit ( P01 P01 Output Latch IRQCSI0 Set Signal ) 3 Serial Clock Control Circuit Serial Clock Selector fx/2 4 fx/2 6 fx/2 TOUT F/F (from Timer/Event Counter) External SCK0 µPD75237 81 µPD75237 (3) Serial interface (channel 0) register functions (a) Serial operating mode register 0 (CSIM0) Fig. 4-40 shows a serial operating mode register 0 (CSIM0) format. CSIM0 is an 8-bit register to specify the serial interface (channel 0) operating mode, serial clock and the wake-up function. An 8-bit memory manipulation instruction is used for CSIM0 operations. The higher 3 bits can be manipulated in 1-bit units. Use each bit name for bit manipulation. Read/write operation is enabled/disabled depending on the bit (refer to Fig. 4-40). Bit 6 is only enabled for test and the written data is invalidated. RESET input clears all bits to 0. Fig. 4-40 Serial Operating Mode Register 0 (CSIM0) Format (1/3) Address FE0H 7 6 5 CSIE0 COI WUP 4 3 2 1 0 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Symbol CSIM0 Serial Clock Select Bit (W) Serial Interface Operating Mode Select Bit (W) Wake-Up Function Specify Bit (w) Signal (R) from Address Comparator Serial Interface Operation Enable/Disable Specify Bit (W) Remarks 82 1. 2. (R) : (W) : Read only Write only µPD75237 Fig. 4-40 Serial Operating Mode Register 0 (CSIM0) Format (2/3) Serial Clock Select Bit (W) Serial Clock CSIM01 CSIM00 3-Wire Serial I/O Mode * 0 0 0 1 SBI Mode 2-Wire Serial I/O Mode SCK0 Pin Mode Input Input clock to SCK0 pin from outside. Timer/event counter output (T0) 4 1 0 fX/2 (375 kHz, or 262 kHz) * 1 1 fX/23(750 kHz, or 524 kHz) * Output fX/26(93.8 kHz, or 65.5 kHz) * Values in parentheses are when fX = 6.0 MHz or when fX = 4.19 MHz. Serial Interface Operating Mode Select Bit (W) CSIM04 CSIM03 CSIM02 0 × 0 1 Operating Mode 3-wire serial I/O mode Bit Order of Shift Register 0 SIO07–0↔XA (transferred with MSB first) SIO00–7↔XA (transferred with LSB first) 0 1 0 SBI mode SIO07–0↔XA (transferred with MSB first) ( SO0 Pin Function SI0 Pin Function SO0/P02 (CMOS output) SI0/P03 (input) SB0/P02 N-ch open drain input/output 1 P02 input 0 SB0/P02 N-ch open drain input/output 1 1 2-wire serial I/O mode SIO07–0↔XA (transferred with MSB first) 1 Remarks ( P02 input P03 input ) ( SB1/P03 N-ch open drain input/output ) P03 input ) ( SB1/P03 N-ch open drain input/output ) × : Don’t care Wake-Up Function Specify Bit (W) 0 IRQCSI0 is set upon termination of serial transfer in each mode. 1 Used in SBI mode only. IRQCSI0 is set only when the address received after bus release matches the slave address register data (wake-up state). SB0/SB1 is high impedance. WUP Note When WUP = 1 is set during BUSY signal output, BUSY is not released. In SBI, BUSY signal continues to be output up to the falling edge of the next serial clock (SCK0) after BUSY release. Ensure to set WUP = 1 after releasing BUSY and confirming that the SB0 (or SB1) pin has become high level. 83 µPD75237 Fig. 4-40 Serial Operating Mode Register 0 (CSIMO) Format (3/3) Signal (R) from Address Comparator Clear Condition (COI = 0) COI* * When the slave address register (SVA) data unmatches the shift register 0 data. Set Condition (COI = 1) When the slave address register (SVA) data matches the shift register 0 data. COI read is only valid before serial transfer and after its completion. Only undefined value is read during transfer. The COI data written by an 8-bit manipulation instruction is ignored. Serial Interface Operation Enable/Disable Specify Bit (W) Shift Register 0 Operation CSIE0 Remarks CSIE0 Shift operation disabled Clear Hold Dedicated to port 0 functions 1 Shift operation enabled Count operation Settable Functions in each mode and operations with port 0 1. Each mode can be selected by setting CSIE0, CSIM03 and CSIM02. CSIM03 CSIM02 Operating Mode 0 × × Operation stop mode 1 0 × 3-wire serial I/O mode 1 1 0 SBI mode 1 1 1 2-wire serial I/O mode CSIE0 SO0/SB0, SI0/SB1 Pins IRQCSI0 Flag 0 2. 84 Serial Clock Counter P01/SCK0 pin becomes as follows depending on the settings of CSIE0, CSIM01 and CSIM00. CSIM01 CSIM00 P01/SCK0 Pin Status 0 0 0 Input port 1 0 0 High impedance 0 0 1 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 High-level output Serial clock output (high-level output) µPD75237 Remarks 3. Clear CSIE0 during serial transfer using the following procedure. ➀ Disable interrupt by clearing the interrupt enable flag. ➁ Clear CSIE0. ③ Example 1. Clear the interrupt request flag. Select fx/24 for serial clock and generate serial interrupt IRQCSI0 upon termination of each serial transfer and select a serial transfer mode in the SBI mode using the SB0 pin as serial data bus. SEL MB15 ; Or CLR1 MBE MOV MOV 2. XA, #10001010B CSIM0, XA ; CSIM0 ← 10001010B Enable serial transfer in accordance with the CSIM0 contents. SEL MB15 ; Or CLR1 MBE SET1 CSIE0 85 µPD75237 (b) Serial bus interface control register (SBIC) Fig. 4-41 shows a serial bus interface control register (SBIC) format. SBIC is an 8-bit register which consists of a serial bus control bit and flags indicating various statuses of input data received from the serial bus. SBIC is manipulated using a bit manipulation instruction. It cannot be manipulated using a 4-bit or 8-bit manipulation instruction. Read/write operation enable/disable depends on the bit (refer to Fig. 4-41). RESET input clears all bits to 0. Note Only the following bits can be used in the 3-wire and 2-wire serial I/O modes. • Bus release trigger bit (RELT) ........ SO0 latch set • Command trigger bit (CMDT) ........ SO0 latch clear Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (1/3) Address FE2H 7 6 5 4 3 2 1 0 BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Symbol SBIC Bus Release Trigger Bit (W) Command Trigger Bit (W) Bus Release Detect Flag (R) Command Detect Flag (R) Acknowledge Trigger Bit (W) Acknowledge Enable Bit (R/W) Acknowledge Detect Flag (R) Busy Enable Flag (R/W) Remarks 86 1. 2. 3. (R) Only read (W) Only write (R/W) Read/write enabled µPD75237 Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (2/3) Bus Release Trigger Bit (W) RELT Note Bus release signal (REL) trigger output control bit. When set (RELT = 1), SO0 latch is set (1) and then the RELT bit is automatically cleared (0). Do not clear SB0 (or SB1) during serial transfer. Be sure to do so before transfer start or after transfer end. Command Trigger Bit (W) CMDT Note Command signal (CMD) trigger output control bit. When set (CMDT = 1), SO0 latch is cleared (0) and then the CMDT bit is automatically cleared (0). Do not clear SB0 (or SB1) during serial transfer. Be sure to do so before transfer start or after transfer end. Bus Release Detect Flag (R) Clearing Conditions (RELD = 0) RELD ➀ Transfer start instruction execution ➁ RESET input ➂ CSIE0 = 0 (refer to Fig. 4-40) 4 SVA and SIO0 mismatch upon address reception. Setting Conditions (RELD = 1) Bus release signal (REL) detection Command Detect Flag (R) Clearing Conditions (CMDD = 0) CMDD ➀ Transfer start instruction execution ➁ Bus release signal (REL) detection ➂ RESET input 4 CSIE0 = 0 (refer to Fig. 4-40) Setting Conditions (CMDD = 1) Command signal (CMD) detection Acknowledge Trigger Bit (W) ACKT Note Setting this bit after termination of transfer outputs ACK in synchronization with the next SCK0. After output of ACK signal, this bit is automatically cleared (0). 1. Do not set (1) this bit during serial transfer. 2. ACKT cannot be cleared by software. 3. When setting ACKT, set ACKE = 0. Acknowledge Enable Bit (R/W) 0 ACKE Automatic output of acknowledge signal (ACK) is disabled (output by ACKT enabled). When set before termination of transfer ACK is output in synchronization with the 9th clock of SCK0. 1 When set after termination of transfer ACK is output in synchronization with SCK0 just after execution of a set instruction. 87 µPD75237 Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (3/3) Acknowledge Detect Flag (R) Clearing Conditions (ACKD = 0) ACKD Setting Conditions (ACKD = 1) Acknowledge signal (ACK) detection (at the rising edge of SCK0) ➀ Transfer start instruction execution ➁ RESET input Busy Enable Bit (R/W) BSYE Example 0 ➀ Busy signal automatic output disabled ➁ Busy signal output stopped at the falling edge of SCK0 just after clear instruction execution. 1 Busy signal output at the falling edge of SCK0 following the acknowledge signal. 1. 2. Output the command signal. SEL MB15 ; Or CLR1 MBE SET1 CMDT Identify the receive data type by testing RELD and CMDD for proper processing. Set WUP = 1 for this interruput routine so that processing is carried out only in the case of a match address. SEL SKF BR SKT MB15 RELD !ADRS CMDD ; RELD test ; CMDD test BR !DATA CMD : ....................................... ; Command interpret DATE : ....................................... ; Data processing ADRS : ....................................... ; Address decode 88 µPD75237 (c) Shift register 0 (SIO0) Fig. 4-42 shows a shift register 0 peripheral configuration. SIO0 is an 8-bit register which executes parallel-to-serial conversion and carries out serial transmission/reception (shift operation) in synchronization with a serial clock. Serial transfer is started by writing data to SIO0. In transmission, the data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. This register can be read/written by an 8-bit manipulation instruction. RESET input during operation makes the SIO0 value undefined. RESET input in the standby mode holds the SIO0 value. Shift operation stops after 8-bit transmission /reception. Fig. 4-42 Shift Register 0 peripheral Configuration Internal Bus Address Comparator RELT CMDT Shift Register 0 SO0 Latch CLR SET D Q CLK CSIM0 Shift Clock BUSY/ACK N-ch Open Drain Output SIO0 read and serial transfer start (write) are enabled at the following timings. • Serial interface operation enable/disable bit (CSIE0) = 1 except when CSIE0 is set to “1” after data write to the shift register. • When the serial clock is masked after 8-bit serial transfer. • When SCK0 is at a high level Be sure to write/read data to SIO0 when SCK0 is at a high level. In the 2-wire serial I/O or SBI mode, the data bus has a configuration that the input pins serve as output pins and vice versa. Each output pin has an N-ch open drain configuration. Thus, set FFH to SIO0 for the device for data reception. 89 µPD75237 (d) Slave address register (SVA) The slave address register (SVA) has the following two functions. Only write is enabled for the SVA by an 8-bit manipulation instruction. RESET input makes the SVA value undefined. RESET input in the standby mode holds the SVA value. • Slave address detection [SBI mode] Use this mode to connect the µPD75237 as a slave device to the serial bus. The SVA is an 8-bit register for the slave to set the slave address value (own specification number). The master outputs a slave address for particular slave selection to the connected slave. These two date (salve address and SVA values output from the master) are compared by an address comparator. When they match, the slave has been selected. In this case, bit 6 (COI) of the serial operating mode register 0 (CSIM0) is set to “1”. Note 1. The slave selection or non-selection status is checked by detecting the matching of the slave address received after bus release (RELD = 1). Use the address match interrupt (IRQCSI0) to be normally generated with WUP = 1 to detect the matching. Thus, detect selection or non-selection by slave address when WUP = 1. 2. If selection or non-selection is to be detected without using an interrupt when WUP = 0, do so by transmitting/receiving the command preset by a program without using the method of detecting address matching. • Error detection [2-wire serial I/O and SBI modes] When an address, a command and data are to be transmitted using the µPD75237 as the master device or data is to be transmitted using the µPD75237 as the slave device, the SVA detects errors. (4) Various types of signals Table 4-6 gives a list of various types of signals. Figs. 4-43 to 4-48 show the various types of signals and flag operation. 90 Table 4-6 Various Types of Signals in SBI Mode (1/2) Signal Name Output Device Output Condition Timing Chart Definition Rising edge of SB0/SB1 when SCK0 = 1 Bus release signal • RELT set • RELD set CMD signal is output to is an address. SB0/SB1 (REL) Falling edge of SB0/SB1 when • CMDT set • CMDD set SCK0 = 1 Command signal Meaning of Signal • CMDD clear indicate that transmit data "H" SCK0 Master Effect on Flag dress after REL signal "H" SCK0 Master (CMD) i) Transmit data is an ad- output ii) No REL signal output. SB0/SB1 Transmit data is a command. Acknowledge signal (ACK) Master/ slave Low–level signal to be output ➀ ACKE = 1 to SB0/SB1 during one-clock ➁ ACKT set [Synchronous Busy Output] [Synchronous busy signal] Slave (BUSY) Low–level signal to be output • BSYE = 1 SCK0 to SB0/SB1 following the acknowledge signal ACK to before serial transfer start or after its compleltion Slave (READY) Serial reception disabled because of processing BUSY READY ACK SB0/SB1 D0 — 9 SB0/SB1 D0 High- level signal to be output Ready signal Completion of reception period of SCK0 after completion of serial reception Busy signal • ACKD set BUSY ➀ BSYE = 0 READY Serial reception enabed 91 µPD75237 ➁ Execution of an instruction for data write to SIO0 (transfer start command) — 92 Table 4-6 Various Types of Signals in SBI Mode (2/2) Signal Name Serial clock (SCK0) Address (A7 to 0) Command (C7 to 0) Output Device Master Master Master Synchronous clock to ouput address, command, data, ACK signal and synchronous BUSY signal. Address, command and data are transferred by the first eight clocks. 8-bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals 8-bit data to be transferred in synchronization with SCK0 after output of CMD signal only without REL signal output Output Condition Timing Chart Definition SCK0 1 2 7 8 9 10 SB0/SB1 SCK0 1 2 7 8 1 2 7 8 1 2 7 8 Execution of an instruction for data write to SIO0 when CSIE0 = 1 (serial transfer start command)*2 Effect on Flag Meaning of Signal IRQCSI0 set Timing of signal output (rising edge to the serial data bus of 9th clock) *1 Address value of slave device on the serial bus SB0/SB1 REL CMD SCK0 Command and message for the slave device SB0/SB1 CMD Data (D7 to 0) * 1. SCK0 Numeric value to be processed by a slave or master device SB0/SB1 When WUP = 0, IRQCSI0 is always set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the received address matches the slave adress register (SVA) value, IRQCSI0 is set at the rising edge of the 9th clock of SCK0. Transfer starts after the BUSY state is changed to the READY state. µPD75237 2. Master/ slave 8-bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals µPD75237 Fig. 4-43 RELT, CMDT, RELD and CMDD (Master) Operations Transfer Start Directive SIO0 SCK0 "H" SO0 Latch RELT CMDT RELD CMDD Fig. 4-44 RELT, CMDT, RELD and CMDD (Slave) Operations Transfer Start Directive Write to SIO0 SIO0 SCK0 1 D7 SO0 Latch 2 D6 7 D1 8 D0 RELT (Master) CMDT (Master) When the address matches RELD When the address does not match CMDD FIg. 4-45 ACKT Operations Set after completion of transfer SCK0 SB0/SB1 6 7 D2 8 D1 9 D0 ACK ACK signal is output during 1-clock period just after setting ACKT When set during this period Note Do not set ACKT just before termination of transfer. 93 µPD75237 Fig. 4-46 ACKE Operation (a) When ACKE = 1 upon completion of transfer 1 SCK0 2 D7 SB0/SB1 7 D6 D2 8 D1 9 D0 ACK ACK signal is output at the 9th clock ACKE When ACKE=1 at this point (b) When set after completion of transfer SCK0 SB0/SB1 6 7 D2 8 D1 9 ACK D0 ACK signal is output during 1-clock period just after setting ACKE When set during this period and ACKE=1 at the falling edge of the next SCK0. (c) When ACKE = 0 upon completion of transfer SCK0 SB0/SB1 1 2 D7 7 D6 D2 D1 8 D0 9 ACK signal is not output ACKE When ACKE = 0 at this point (d) When the ACKE = 1 period is short SCK0 SB0/SB1 ACK signal is not output ACKE When set and cleared during this period and ACKE=0 at the falling edge of ACK0 94 µPD75237 Fig. 4-47 ACKD Operations (a) When ACK signal is output during the 9th clock period of SCK0. Transfer Start Directive SIO0 Transfer Start SCK0 6 7 8 D2 SB0/SB1 D1 9 D0 ACK ACKD (b) Transfer Start Directive When ACK signal is output after the 9th clock of SCK0 SIO0 Transfer Start SCK0 6 SB0/SB1 7 D2 8 D1 9 ACK D0 ACKD (c) Clear timing with transfer start command during BUSY Transfer Start Directive SIO0 SCK0 SB0/SB1 6 7 D2 8 D1 9 ACK D0 BUSY D7 D6 ACKD Fig. 4-48 BSYE Operation SCK0 SB0/SB1 6 7 8 9 ACK BUSY BSYE When BSYE=1 at this point When reset during this period and BSYE=0 at the falling edge of SCK0 95 µPD75237 (5) Serial interface (channel 0) operations (a) Operation stop mode The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. In this mode, shift register 0 does not carry out shift operation and thus can be used as a normal 8bit register. RESET input sets the operation stop mode. The P02/SO0/SB0 pin and P03/SI0/SB1 pins are fixed to the input port. P01/SCK0 can be used as an input port by setting serial operating mode register 0. (b) 3-wire serial I/O mode operations The 3-wire serial I/O mode allows connection with the methods employed with another 75X series and 78K series. Communication is carried out using three lines of serial clock (SCK0), serial output (SO0) and serial input (SI0). (i) Communication The 3-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0). Transmit data is held at the SO0 latch and output from the SO0 pin. Receive data input to the SI0 pin is latched to the shift register 0 at the rising edge of SCK0. Shift register 0 operation automatically stops upon termination of 8-bit transfer and the interrupt request flag (IRQCSI0) is set. Fig. 4-49 3-Wire Serial I/O Mode Timing SCK0 1 2 3 4 5 6 7 8 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 IRQCSI0 Transfer start at the falling edge of SCK0 Execution of data write instruction to SIO0 (Transfer Start Directive) 96 End of Transfer µPD75237 The SO0 pin serves as CMOS output to output the SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. The SCK0 pin can control the output status by manipulating the P01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) SCK0 pin output manipulation). (ii) MSB/LSB first switching The 3-wire serial I/O mode has a function which allows MSB-first or LSB-first transfer to be selected. Fig. 4-50 shows shift register 0 (SIO0) and internal bus configurations. As shown in Fig. 4-50, MSB/ LSB can be reversed and read/written. MSB/LSB first switching can be specified by bit 2 of serial operating mode register 0 (CSIM0). Fig. 4-50 Transfer Bit Switching Circuit 7 6 Internal Bus 1 0 LSB First MSB First SI0 Read/Write Gate Shift Register 0 (SIO0) Read/Write Gate D Q SO0 Latch SO0 SCK0 First bit switching is realized by switching the bit order of data write to the shift register 0 (SIO0). The SIO0 shift order remains the same. Thus, switch the MSB/LSB first bit before writing data to the shift register 0. 97 µPD75237 (c) 2-wire serial I/O mode operations The 2-wire serial I/O mode can be applied to any communication format by program. Communication is basically carried out using two lines of serial clock (SCK0) and serial data input/ output (SB0 or SB1). (i) Communication The 2-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0). Transmit data is held at the SO0 latch and output from the SB0/P02 (or SB1/P03) pin with MSB set as the first bit. Receive data input from the SB0 (or SB1) pin at the SCK0 rising edge is latched to the shift register 0. Upon termination of 8-bit transfer, the shift register 0 operation automatically stops and the interrupt request flag (IRQCSI0) is set. Fig. 4-51 2-Wire Serial I/O Mode Timing SCK0 SB0/SB1 1 2 D7 3 D6 4 D5 5 D4 6 D3 7 D2 8 D1 D0 IRQCSI0 End of Transfer Transfer start at the falling edge of SCK0 Execution of data write instruction to SIO0 (Transfer Start Directive) Since the pin specified for the serial data bus of the SB0 (or SB1) pin becomes an N-ch open drain input/ output, it must be pulled up externally. Since the SB0 (or SB1) pin outputs the SO0 latch status, the SB0 (or SB1) pin status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this operation during serial transfer. The SCK0 pin can control the output status by manipulating the P01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) SCK0 pin output manipulation). 98 µPD75237 (d) SBI mode operations SBI (serial bus interface) is a high-speed serial interface method compliant with the NEC serial bus format. SBI is a single master high-speed serial bus based on the format with bus configuration functions added to the clocked serial synchronization I/O method so that communication can be carried out with two or more devices using two signal conductors. Thus, the number of ports used and that of wires on the board can be decreased for serial bus configuration with two or more microcomputers and peripheral ICs. Fig. 4-52 shows the SBI system configuration example. Fig. 4-52 SBI System Configuration Example Master CPU µPD75237 SB0 (AB1) SCK0 Slave CPU µPD75237 SB0 (SB1) Address 1 SCK0 Slave CPU SB0 (SB1) Address 2 SCK0 Slave IC SB0 (SB1) Address N SCK0 Note 1. 2. Because in the SBI the serial data bus pin SB0 (or SB1) is an open drain output, the serial data bus line is wired-OR. A pull-up resistor is necessary for the serial data bus line. For master/slave replacement, a pull-up resistor is necessary for SCK0 because serial clock line (SCK0) input/output switching is executed asynchronously between the master and slave. 99 µPD75237 (i) SBI functions • Address/command/data identification SBI distinguishes serial data between address, command and data. • Chip select function by address The master executes slave chip selection by address transmission. • Wake-up function The slave can easily make an address receive judgment (chip select judgment) using the wake- up function (which can be set/cancelled by software). When the wake-up function is set, an interrupt (IRQCSI0) is generated upon reception of a match address. Thus, when communication is carried out with two or more devices, CPUs except the selected slave can operate irrespective of serial communication. • Acknowledge signal (ACK) control function Acknowledge signal is controlled to confirm serial data reception. • Busy signal (BUSY) control function The busy signal is controlled to inform the slave busy status. Fig. 4-53 SBI Transfer Timing Address Transfer 8 SCK0 SB0/SB1 A7 9 ACK A0 BUSY Bus Release Signal Command Transfer Command Signal 9 SCK0 SB0/SB1 C7 C0 ACK BUSY READY ACK BUSY READY Data Transfer 8 SCK0 SB0/SB1 100 D7 D0 9 µPD75237 (ii) Communication In the SBI, the master normally selects one slave device for communication target from among two or more devices by outputting an “address” to the serial bus. After the communication target device has been determined, serial communication is achieved through command and data transmission/reception between the master and slave devices. Figs. 4-54 to 4-57 show the timing charts of data communication. In the SBI mode, shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0) and transmit data is output from the SB0/P02 or SB1/P03 pin with MSB as the first bit. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched to the shift register 0. 101 102 Fig. 4-54 Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter Side) Program Processing CMDT RELT CMDT Set Set Set Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation SCK0 Stop ACKD Set Serial Transmission Hardware Operation Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9 SB0 Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSY READY Address Slave Device Processing (Receiver Side) Hardware Operation ACKT Set WUP ← 0 Program Processing CMDD CMDD CMDD Set Clear RELD Set Set ACK Output Serial Reception IRQCSI0 Generation BUSY Clear BUSY Output BUSY Clear (When SVA = SIO0) µPD75237 Fig. 4-55 Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter Side) Program Processing CMDT Set Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation ACKD Set Serial Transmission Hardware Operation SCK0 Stop Transfer Line SCK0 Pin 1 SB0 Pin C7 2 C6 3 C5 4 5 C4 C3 6 C2 7 C1 8 9 C0 ACK READY BUSY Command Slave Device Processing (Receiver Side) SIO0 Read Program Processing Hardware Operation CMDD Set Command Analysis ACKT Set ACK Output Serial Reception BUSY Output BUSY Clear 103 µPD75237 IRQCSI0 Generation BUSY Clear 104 Fig. 4-56 Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter Side) Program Processing Write to SIO0 Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation ACKD Set Serial Transmission Hardware Operation SCK0 Set Transfer Line SCK0 Pin SB0 Pin 1 D7 2 D6 3 D5 4 5 D4 D3 6 D2 7 D1 8 9 D0 ACK READY BUSY Data Slave Device Processing (Receiver Side) SIO0 Read Program Processing Hardware Operation ACKT Set ACK Output Serial Reception BUSY Output BUSY Clear µPD75237 IRQCSI0 Generation BUSY Clear Fig. 4-57 Data Transmission from Slave Device to Master Device★ Master Device Processing (Receiver Side) FFH Write to SIO0 Program Processing SIO0 Read SCK0 Stop Hardware Operation ACKT Set FFH Write to SIO0 Receive Data Processing Serial Reception ACK Output Serial Reception IRQCSI0 Generation Transfer Line 1 SCK0 Pin SB0 Pin BUSY READY D7 2 3 D6 4 D5 5 D4 6 D3 7 D2 8 D1 9 1 D0 ACK BUSY READY 2 D7D6 Data Slave Device Processing (Transmitter Side) Program Processing Write to SIO0 Hardware Operation BUSY Clear Write to SIO0 ACKD BUSY Output Output Serial Transmission 105 µPD75237 IRQCSI0 Generation BUSY Clear µPD75237 (6) Transfer start in each mode In each of the 3-wire and 2-wire serial I/O modes and the SBI mode, serial transfer is started by setting transfer data to the shift register 0 (SIO0) under the following two conditions. • Serial interface operation enable/disable bit (CSIE0) = 1 • The internal serial clock has stopped or SCK0 is at high level after 8-bit serial transfer. Note Transfer does not start if CSIE0 is set to “1” after data is written to the shift register 0. Serial transfer automatically stops and the interrupt request flag (IRQCSI0) is set upon termination of 8-bit transfer. [2-wire serial I/O mode transfer start precautions] Note Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in advance. [SBI mode transfer start precautions] Note 1. Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in advance. However, in the case of wake-up function specify bit (WUP) = 1, the N-ch transistor remains OFF. Thus, it is not necessary to write FFH to SIO0 before reception. 2. If data is written to SIO0 when the slave is busy, the written data is not lost. Transfer starts when the busy status is cancelled and the SB0 (or SB1) input becomes high level (ready status). Example 106 The RAM data specified by the HL register is transferred to SIO0 and simultaneously the SIO0 data is fetched into the accumulator and serial transfer is started. MOV XA, @HL ; Transmit data is fetched from the RAM. SEL XCH MB15 XA, SIO0 ; Or CLR1 MBE ; Transmit data is exchanged with receive data and transfer is started. µPD75237 (7) SCK0 pin output manipulation Because the SCK0/P01 pin incorporates an output latch, static output is possible by software in addition to normal serial clocks. P01 output latch manipulation enables to set any number of SCK0 by software (SO0/SB0/SB1 pin is controlled by the RELT and CMDT bits of SBIC). SCK0/P01 pin output manipulation is described below. ➀ Set the serial operating mode register 0 (CSIM0) (SCK0 pin: output mode, serial operation: enabled). While serial transfer is stopped, SCK0 from the serial clock control circuit remains 1. ➁ Manipulate the P01 output latch by a bit manipulation instruction. Example 1 clock SEL MOV MOV output to SCK0/P01 pin by software. MB15 ; Or CLR1 MBE XA,#10000011B ; SCK0(fX/23), output mode CSIM0,XA CLR1 SET1 0FF0H.1 0FF0H.1 ; SCK0/P01←0 ; SCK0/P01←1 Fig. 4-58 SCK0/P01 Pin Configuration Address FF0H.1 To Internal Circuit P01/SCK0 P01 Output Latch SCK0 From Serial Clock Control Circuit CSIE0 = 1 and CSIM01 and CSIM00 ≠ 00 The P01 output latch is mapped at bit 1 of address FF0H. RESET signal generation sets the P01 output latch to “1”. Note 1. It is necessary to set the P01 output latch to 1 during normal serial transfer. 2. The P01 output latch address cannot be set by “PORT0.1” as shown below. Describe address (0FF0H.1) directly for the operand. However, it is necessary to preset MBE = 0 or (MBE = 1 and MBS = 15) for instruction execution. CLR1 PORT0.1 Use disabled SET1 PORT0.1 CLR1 0FF0H.1 Use enabled SET1 0FF0H.1 107 µPD75237 (8) Serial interface (channel 1) functions The following two modes are available to the µPD75237 serial interface (channel 1). The summary of each mode is shown below. • Operation stop mode The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. • 3-wire serial I/O mode 8-bit data transfer is carried out using three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). In the 3-wire serial I/O mode which enables simultaneous transmission and reception, the data transfer rate is improved. The first bit of 8-bit data for serial transfer is fixed to MSB. In the 3-wire serial I/O mode, channel 1 can be connected to the 75X series, 78K series and various types ★ of peripheral I/O devices. (9) 108 Serial interface (channel 1) configuration Fig. 4-59 shows a serial interface (channel 1) block diagram. Fig. 4-59 Serial Interface (Channel 1) Block Diagram Internal Bus 8 bit0 P83/SI1 Bit Manipulation SIO1 Write Signal (Serial Start Signal) 7 bit7 Bit Manipulation 8 0 CSIM1 SIO1 Shift Register 1 (8) Serial Operating Mode Register (8) P82/SO1 Clear Serial Transfer End Flag (EOT) Overflow Serial Clock Counter (3) Set Clear P81/SCK1 R Q S fx/23 fx/24 109 µPD75237 Serial Clock Selector µPD75237 (10) Serial interface (channel 1) register functions (a) Serial operating mode register 1 (CSIM1) Fig. 4-60 shows a serial operating mode register 1 (CSIM1) format. CSIM1 is an 8-bit register to specify the serial interface (channel 1) operating mode and serial clock. It is manipulated by an 8-bit memory manipulation instruction. The higher 1 bit can be manipulated bit-wise. Use each bit name for bit manipulation. RESET input clears all bits to 0. Fig. 4-60 Serial Operating Mode Register 1 Format Address FC8H 7 6 5 4 3 2 CSIE1 0 0 0 0 0 1 0 CSIM11 CSIM10 Symbol CSIM1 Serial Clock Select Bit (W) CSIM11 CSIM10 0 0 External input clock to SCK1 pin 0 1 Setting disabled * Serial Clock 3-Wire Serial I/O Mode SCK Pin Mode Input — 4 1 0 fx/2 (375 kHz, or 262 kHz) * 1 1 fx/23 (750 kHz, or 524 kHz) * Output Values in parentheses are when fX = 6.0 MHz or f X = 4.19 MHz. Serial Interface Operation Enable/Disable Specify Bit (W) Shift Register 1 Operation ★ ★ Serial Clock Counter IRQCSI Flag SO1 and SI1 Pins 0 Shift operation disabled Clear Hold Dedicated to port 8 functions 1 Shift operation enabled Count operation Settable Functions in each mode and operations with port 8 CSIE1 Note 110 Be sure to write “0” to bits 2 to 6 of the serial operating mode register. µPD75237 (b) Shift register 1 (SIO1) SIO1 is an 8-bit register which executes parallel to serial conversion and carries out serial transmission/ reception (shift operation) in synchronization with a serial clock. Serial transfer is started by writing data to SIO1. In transmission, the data written to SIO1 is output to the serial output (SO1). In reception, data is read from the serial input (SI1) to SIO1. This register can be read/written by an 8-bit manipulation instruction. RESET input during operation makes the SIO1 value undefined. RESET input in the standby mode holds the SIO1 value. Shift operation stops after 8-bit transmission/reception. SIO1 read and serial transfer start (write) are enabled at the following timings. • Serial interface operation enable/disable bit (CSIE1) = 1 except when CSIE1 is set to “1” after data write to the shift register. • When the serial clock is masked after 8-bit serial transfer. • When SCK1 is at a high level. 111 µPD75237 (11) Serial interface (channel 1) operations (a) Operation stop mode The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. In this mode, shift register 1 does not carry out shift operation and thus can be used as a normal 8bit register. RESET input sets the operation stop mode. The P82/SO1 pin and P83/SI1 pin are fixed to the input port. P81/SCK1 can be used as an input port by setting serial operating mode register 1. (b) 3-wire serial I/O mode operations The 3-wire serial I/O mode allows connection with the methods employed with another 75X series and 78K series, etc. Communication is carried out using three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). The 3-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 1 is carried out at the falling edge of serial clock (SCK1). Transmit data is held at the SO1 latch and output from the SO1 pin. Receive data input to the SI1 pin is latched to the shift register 1 at the rising edge of SCK1. Shift register 1 operation automatically stops upon termination of 8-bit transfer and the serial transfer end flag (EOT) is set. Fig. 4-61 3-Wire Serial I/O Mode Timing SCK1 1 2 3 4 5 6 7 8 SI1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SO1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 EOT Transfer start at the falling edge of SCK1 Execution of data write instruction to SIO1 (Transfer Start Directive) 112 End of Transfer µPD75237 4.10 A/D CONVERTER The µPD75237 incorporates an 8-bit resolution A/D converter with 8-channel analog inputs (AN0 to AN7). The A/D converter employs successive approximation. (1) A/D converter configuration Fig. 4-62 shows an A/D converter configuration. Fig. 4-62 A/D Converter Block Diagram Internal Bus 8 0 ADM6 ADM5 ADM4 SOC EOC 0 0 8 AN0 Control Circuit Simple & Hold Circuit AN1 AN2 + AN3 Multiplexer SA Register (8) – AN4 Comparator AN5 AN6 8 AN7 Tap Decoder AV REF R/2 R R R R/2 AV ss 113 µPD75237 (2) A/D converter pin functions (a) AN0 to AN7 These are 8-channel analog signal input pins to the A/D converter. An analog signal to undergo A/ D conversion is input to these pins. The A/D converter incorporates a sample hold circuit. The analog input voltage is internally held during A/D conversion. (b) AVREF and AVSS The A/D converter reference voltage is input to these pins. Signals input to AN0 to AN7 are converted to digital signals in accordance with the voltage applied between AVREF and AV SS. AVSS should always be set to the same voltage as VSS. ★ (c) AVDD AVDD is a power supply pin for the A/D converter. It should be set to the same voltage as VDD, even when the A/D converter is not used, or in standby mode. (3) A/D conversion mode register The A/D conversion mode register (ADM) is an 8-bit register for analog input channel selection, conversion start command and conversion end detection (see Fig. 4-63). The ADM is set by an 8-bit manipulation instruction. The bit 2 conversion end detection flag (EOC) and the bit 3 conversion start command bit (SOC) can be manipulated in bit units. RESET input initializes the ADM to 04H (only EOC is set to “1” and all other bits are cleared to “0”). 114 µPD75237 Fig. 4-63 A/D Conversion Mode Register Format Address 7 6 5 4 3 2 1 0 Symbol FD8H 0 ADM6 ADM5 ADM4 SOC EOC 0 0 ADM Conversion End Detection Flag EOC 0 Being converted 1 End of conversion Conversion Start Directive Bit Setting this bit starts A/D conversion. SOC Upon conversion start, this bit is automatically cleared. Analog Channel Select Bit Note * ADM6 ADM5 ADM4 Analog Channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 A/D conversion starts with a maximum delay of 24/fX sec (2.67 µs: at 6.0 MHz operation)* after SOC setting (refer to 4.10 (5) A/D converter operations). 3.81 µ s at 4.19 MHz operation 115 µPD75237 (4) SA register (SA) The SA register (Successive Approximation Register) is an 8-bit register to store the result of A/D conversion by successive approximation. The SA register is read by an 8-bit manipulation instruction. Data cannot be written to this register by software. RESET input sets the SA register undefined. (5) A/D converter operations The analog input signal to undergo A/D conversion is specified by setting bits 6, 5 and 4 (ADM6, 5 and 4) of the A/D conversion mode register. A/D conversion is started by setting (1) ADM bit 3 (SOC). SOC is automatically cleared (0) after the setting. A/D conversion is executed using successive approximation by hardware and the 8-bit conversion result data is stored into the SA register. Upon termination of conversion, bit 2 (EOC) of ADM is set (1). Fig. 4-64 is an A/D conversion timing chart. Use the A/D converter as follows. ➀ ➁ ➂ 4 Note Select the analog input channel (ADM 6, 5 and 4 setting). Instruct A/D conversion start (SOC setting). Wait for A/D conversion to terminate (wait for EOC to be set or wait with a software timer). Read the A/D conversion result (SA register reading). 1. ➀ and ➁ can be carried out simultaneously. 2. A maximum delay of 24/fX sec (2.67 µs: at 6.0 MHz operation)* occurs from A/D conversion start to EOC clear after SOC setting. Thus, test EOC after the passage of time indicated in Table 4-7 after SOC setting. Table 4-7 shows A/D conversion times as well. * 3.81 µ s at 4.19 MHz operation Table 4-7 SCC and PCC Settings SCC and PCC Set Value SCC3 0 SCC0 A/D Conversion Time PCC1 PCC0 0 0 Wait not required 0 1 1 0 1 1 1 machine cycle 168/fx (28 µs : at 6.0 2 machine cycles MHz operation)* 4 machine cycles Wait not required 0 0 1 × × 1 × × × Conversion operation stopped * 40.1 µs at 4.19 MHz operation Remarks x : Don’t care 116 Wait time till EOC test after SOC setting — Wait time till the end of A/D conversion after SOC setting 3 machine cycles 11 machine cycles 21 machine cycles 42 machine cycles Wait not required — µPD75237 Fig. 4-64 A/D Conversion Timing Chart SOC EOC SA Register Previous Data Time until A/D Conversion Start (2 4/fX × sec max.) * (6) Undefined Conversion Result Sampling A/D Conversion 168/f X sec (28 µs: at 6.0 MHz operation)* 40.1 µs at 4.19 MHz operation Standby mode precautions The A/D converter operates with the main system clock. Thus, the converter operation stops in the STOP mode or in the HALT mode with the subsystem clock. In this case also, current flows to the AVREF pin. Thus, it is necessary to cut the current to decrease the power consumption of the whole system. The P21 pin has a more improved driving capacity than any other port and so can directly supply a voltage to the AVREF pin. However, in this case, the actual AVREF voltage have no accuracy. Thus, the conversion value itself has no accuracy and can only be used for relative comparison. In the standby mode, power consumption can be decreased by generating a low level to P21. The AVDD pin should be set to the same voltage as VDD in the standby mode. Fig. 4-65 AVREF Pin Processing in Standby Mode VDD P21 P-ch Large AVREF AVREF REF . AV =. VVDDDD µPD75237 AV ss 117 µPD75237 (7) Others and operating precautions (a) AN0 to AN7 input range Use AN0 to AN7 input voltages in the specified range. If a voltage larger than VDD or smaller than VSS is input (if in the absolute maximum range), the conversion value of the channel becomes undefined and may affect the conversion values of other channels. ★ (b) Countermeasures against noise To maintain 8-bit accuracy, extra attention must be paid to noise in the AVREF and AN0 to AN7 pins. The higher the analog input source output impedance becomes the more the noise effect becomes. To prevent that from occurring, mount C externally as shown in Fig. 4-66. Fig. 4-66 Analog Input Pin Processing VDD If noise larger than VDD or smaller than VSS may be generated, clamp with a diode having a small VF (0.3 V or less). AVREF AN0 - AN7 C = 100 – 1000pF µPD75237 VDD VDD AV DD AV SS VSS (c) AN4/P90 to AN7/P93 pins Analog inputs AN4 to AN7 also serve as the input port (PORT9) pin. Do not execute a PORT9 input instruction during A/D conversion with any one of AN4 to AN7 selected. The conversion accuracy may be deteriorated. If a digital pulse is applied to a pin contiguous to the pin undergoing A/D conversion, the expected A/ D conversion value may not be obtained because of coupling noise. Thus, do not apply pulses to such pins. ★ (d) AVDD pin AVDD pin should be set to the same voltage even when A/D converter is not used, or in standby mode. 118 µPD75237 4.11 BIT SEQUENTIAL BUFFER : 16 BITS The bit sequential buffer (BSB0 to BSB3) is a special data memory for bit manipulation. Since this buffer can easily carry out bit manipulation by sequentially changing address and bit specification, it is useful to process data having long bit lengths in bit units. This data memory consists of 16 bits and can execute the pmem.@L addressing of bit manipulation instructions. Thus, it can indirectly specify bits with the L register. In this case, processing can be carried out by sequentially shifting the specified bit by simply incrementing/decrementing the L register in the program loop. Fig. 4-67 Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L Register 2 1 FC2H 0 3 BSB3 L=F 2 1 FC1H 0 3 BSB2 1 0 3 BSB1 L=8 L=7 L=C L=B 2 FC0H 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks In pmem.@L addressing, the specified bit shifts in accordance with the L register. The bit sequential buffer can be operated irrespective of MBE or MBS specification. Data manipulation is also possible by direct addressing. 1-, 4- and 8-bit direct addressing can be combined with pmem.@L addressing for applications to continuous 1-bit data input/output. In the case of 8-bit manipulation, the most and least significant 8 bits each are manipulated by specifying BSB0 and BSB2, respectively. 4.12 FIP CONTROLLER/DRIVER (1) FIP controller/driver configuration The µPD75237 incorporates a display controller which automatically generates the digit and segment signals by reading the display data memory contents by carrying out DMA operation and a high-voltage output buffer which can directly drive the fluorescent display tube (FIP). The FIP controller/driver configuration is shown in Fig. 4-68. Note The FIP controller/driver can only operate at high and intermediate speeds (PCC = 0011B or 0010B) of the main system clock (SCC.0 = “0”). It may malfunction with any other clock or in the standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = “0”) and then shift the unit to any other clock mode or the standby mode. 119 120 Fig. 4-68 FIP Controller/Driver Block Diagram Internal Bus 8 Static Mode Register B 4/8 Display Data Memory (32 × 4 Bits) Key Scan Register (KS2) 4/8 Display Mode Register Display Data Memory (64 × 4 Bits) Key Scan Registers (KS0, KS1) 8 Segment Data Latch (8) 4 4 Digit Select Register 4 Key Scan Flag (KSF) 8 Dimmer Select Register Static Mode Register A Key Scan Flag (KSF) Port H 12 4 INTKS IRQKS Set Signal Digit Signal Generator Segment Data Latch (16) 4 4 Selector 8 10 2 2 4 4 Selector 2 High-Voltage Output Buffer 8 High-Voltage Output Buffer 10 S0/P120S9/P141 2 S10/T15/P142S11/T14/P143 4 S12/T13/P150/PH0S15/T10/P153/PH3 10 T0-T9 VLOAD µPD75237 S16/P100S23/P113 10 4 µPD75237 (2) FIP controller/driver functions The FIP controller/driver built in the µPD75237 has the following functions: (a) Segment signal output (DMA operation) and automatic digit signal output are possible by automatic read of display data. (b) The FIP with 9 to 24 segments and 9 to 16 digits (up to a total of 34 display outputs) can be controlled using the display mode register (DSPM), digit select register (DIGS), static mode register A (STATA) and static mode register B (STATB). (c) Output not used for dynamic display can be used for static output or output port. (d) 8 brightness levels can be adjusted using the dimmer function. (e) Hardware is incorporated for key scan application. • Key scan interrupt (IRQKS) generation (key scan timing detection) • Key scan data output from segment output is possible with the key scan buffers (KS0, KS1 and KS2). (f) High-voltage output pin (40 V) capable of directly driving FIP. • Segment output pins (S0 to S9, S16 to S23) : VOD = 40 V, IOD= 3 mA • Digit output pins (T0 to T15) : VOD = 40 V, IOD = 15 mA (g) Display output pin mask option • T0 to T9 and S0 to S15 can incorporate a pull-down resistor in bit units to VLOAD. • S16 to S23 can incorporate a pull-down resistor in bit units to VLOAD or VSS. Determine in 8-bit units whether a pull-down resistor should be incorporated to VLOAD or VSS. (3) Display output function differences between µPD75237 and µPD75216A/µPD75217 Table 4-8 shows display output function differences between µPD75237 and µPD75216A/µPD75217. Table 4-8 Display Output Function Differences between µPD75237 and µPD75216A/µPD75217 µPD75237 High-voltage output display µPD75216A, 75217 FIP output total : 34 outputs FIP output total : 26 outputs Segment output : 9 to 24 outputs Segment output : 9 to 16 outputs Digit output Digit output : 9 to 16 outputs : 9 to 16 outputs Display data area 1A0H to 1FFH 1C0H to 1FFH Output dual-function pin S0 to S23 (PORT10 to PORT15) S12 to S15 (PORTH) Key scan register KS0 to KS2 KS0, KS1 121 µPD75237 Fig. 4-69 FIP Controller Operation Timing TCYT TDSP TKS T0 T1 T2 TDIG TN Key Scan Flag (KSF) Changeable any time Segment Data 1 Display Cycle Key Scan Timing IRQKS Generation N : Digit select register set value TDSP : 1 display cycle 2048 1024 = 341 µs: at 6.0 MHz operation*2 = 171 µs: at 6.0 MHz operation*1 or fX fX TCYT : Display period (TCYT = TDSP × (N + 2)) TDIG : Digit signal pulse width variable at 8 levels using a dimmer select register * 1. 2. 122 244 µs at 4.19 MHz operation 489 µs at 4.19 MHz operation µPD75237 (4) Display mode register (DSPM) The display mode register (DSPM) is a 4-bit register to enable/disable display operation and to specify the number of display segments. Its format is shown in Fig. 4-70. The display mode register is set by the 4-bit memory manipulation instruction. When setting the standby mode (STOP mode, HALT mode) or operating the DSPM with the subsystem clock (fXT), stop the display operation by presetting DSPM.3 to “0”. RESET input clears all bits to “0”. Fig. 4-70 Display Mode Register Format Address F88H 3 2 1 0 DSPM3 DSPM2 DSPM1 DSPM0 Symbol DSPM Display Segment Number Specify Bit DSPM2 DSPM1 DSPM0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Remarks Number of Display Segments 9 segments (+ 8 segments) 10 segments (+ 8 segments) 11 segments (+ 8 segments) 12 segments (+ 8 segments) 13 segments (+ 8 segments) 14 segments (+ 8 segments) 15 segments (+ 8 segments) 16 segments (+ 8 segments) Values when S16 to S23 are set to the dynamic mode by STATB are in parentheses. Display Operation Enable/Disable Bit DSPM3 (5) 0 Display stopped 1 Display enabled Digit select register (DIGS) The digit select register (DIGS) is a 4-bit register to specify the number of digits to be displayed. Its format is shown in Fig. 4-71. DIGS is set by the 4-bit memory manipulation instruction. The number of digits to be displayed can be set in the range from 9 to 16 by DIGS setting. The value of 8-digit or less cannot be selected. RESET input initializes DIGS to “1000B” and selects 9-digit display. Fig. 4-71 Digit Select Register Format Address F8AH 3 2 1 0 DIGS3 DIGS2 DIGS1 DIGS0 Symbol DIGS Note 0 to 7 cannot be set in N. DIGS0 to 3 Set Value N ( = 8 to 15) No. of Digits to be Displayed N+1 123 µPD75237 (6) Dimmer select register (DIMS) The dimmer select register (DIMS) is a 4-bit register to specify the digit signal cut width to prevent display light emission from leaking and to maintain the dimmer (brightness adjustment) function. It is also used to select the display cycle (TDSP). The DIMS format is shown in Fig. 4-72. The DIMS is set by the 4-bit memory manipulation instruction. The display cycle of 341 µs: at 6.0 MHz operation*1 is normally selected with DIMS.0 set to “1” to minimize light emission leakage. Because if the number of digits to be displayed increases, the display period becomes equivalent to the commercial power supply frequency and display flickers, select 171 µs: at 6.0 MHZ operation*2. If any light emission leakage occurs, adjust the digit signal cut width with DIMS.1 to DIMS.3. RESET input clears all bits to “0”. * 1. 2. 489 µs at 4.19 MHz operation 244 µs at 4.19 MHz operation Fig. 4-72 Dimmer Select Register Format Address F89H Symbol DIMS3 DIMS2 DIMS1 DIMS0 DIMS Display Cycle Specify Bit 0 Sets 1024 as one display cycle (1 cycle = 171 µs:6.0 MHz)*1 fX 1 Sets 2048 as one display cycle (1 cycle = 341 µs:6.0 MHz)*2 fX DIMS0 Digit Signal Cut Width Specify Bit DIMS3 0 0 0 0 1 1 1 1 * 1. 2. 124 244 µs at 4.19 MHz operation 489 µs at 4.19 MHz operation DIMS2 0 0 1 1 0 0 1 1 DIMS1 0 1 0 1 0 1 0 1 Digit Signal Cut Width 1/16 2/16 4/16 6/16 8/16 10/16 12/16 14/16 µPD75237 (7) Static mode register The static mode register is intended to specify the static output/dynamic output of the segment output pin. There are two types of static mode registers: static mode register A, static mode register B. Figs. 4-73 and 4-74 show their formats, respectively. These two types of static mode registers are set by an 8-bit manipulation instruction. RESET input clears all bits to “0”. (a) Static mode register A (STATA) Static mode register A (STATA) is intended to specify the static output/dynamic output of the S0/P120 to S15/P153/T10/PH3 pins. Fig. 4-73 Static Mode Register A (STATA) Address 7 6 5 4 FD6H 0 0 0 0 3 2 1 0 STATA3 STATA2 STATA1 STATA0 Symbol STATA S0 to S15 Pin Stactic Output/Dynamic Output Select Bit STATA3 STATA2 STATA1 STATA0 0 0 0 0 S0 to S15 become dynamic output. The numbers of segments and digits are set by DSPM and DIGS. 1 S0 to S15 become static output. Perform static data output using an output instruction for ports 12 to 15. These pins are not affected by the DSPM.3 value. 1 Note 1 1 S0 to S15 Pins Output Status It is not possible to set some of the S0 to S15 pins to dynamic output and the remaining pins to static output. 125 µPD75237 (b) Static mode register B (STATB) Static mode register B (STATB) is intended to specify the static output/dynamic output of the S16/P100 to S23/P113 pins. Fig. 4-74 Static Mode Register B (STATB) Address 7 6 FD4H 0 0 5 4 STATB5 STATB4 3 2 1 0 Symbol 0 0 0 0 STATB S16 to S23 Pin Static Output/Dynamic Output Select Bit Note S16 to S23 Pins Output Status STATB5 STATB4 0 0 Dynamic output. Dynamic output is generated in accordance with 1A0H to 1BDH contents. 1 1 Static output. Perform static data output using an output instruction for ports 10 and 11. These pins are not affected by the DSPM.3 value. It is not possible to set some of the S16 to S23 pins to dynamic output and the remaining pins to static output. 126 µPD75237 (8) Display mode selection The numbers of segments and digits which can be displayed using the built-in FIP controller/driver depend on the display mode. Fig. 4-75 shows a display mode selection diagram. Fig. 4-75 Display Mode Selection Diagram Digit Number Selection 0 9 10 11 12 13 14 15 16 9-Segment Mode 9 10-Segment Mode 10 11-Segment Mode 11 12-Segment Mode 12 13-Segment Mode 13 14-Segment Mode Segment Number Selection 14 15-Segment Mode 15 16-Segment Mode 16 17-Segment Mode 17 18-Segment Mode 18 19-Segment Mode 19 20-Segment Mode 20 21-Segment Mode 21 22-Segment Mode 22 23-Segment Mode 23 24-Segment Mode 24 Remarks The circled modes with shading are those expanded from the µPD75216A and µPD75217. 127 µPD75237 (9) Display data memory The display data memory is an area storing the displayed segment data and is mapped at addresses 1A0H to 1FFH of the data memory. Display data is automatically read by a display controller (DMA operation). The areas not used for display can be used as normal data memory. Display data operation is carried out by a data memory manipulation instruction. Data manipulation is possible in 1-, 4- and 8-bit units. Only even addressed can be specified for 8-bit manipulation instruction execution. Addresses 1FCH to 1FFH, 1BEH and 1BFH of the display data memory also serve as key scan registers (KS0, KS1 and KS2). Table 4-9 Data Memories which also Serve as Key Scan Registers Key Scan Register KS0 Note Data Memory which also Serves as Key Scan Register 1FCH, 1FDH KS1 1FEH, 1FFH KS2 1BEH, 1BFH Extra caution is necessary when transferring a program developed for the µPD75237 to one for the µPD75216A and µPD75217 because a maximum of 16 segments are displayed and no data memory is incorporated at addresses (1A0H + 4n and 1A1H + 4n) in the case of the µPD75216A and µPD75217. 128 µPD75237 Fig. 4-76 Display Data Memory Contents and Segment Outputs 24-Segment Mode 23-Segment Mode 22-Segment Mode 21-Segment Mode 20-Segment Mode 19-Segment Mode 18-Segment Mode 17-Segment Mode 16-Segment Mode 15-Segment Mode 14-Segment Mode 13-Segment Mode 12-Segment Mode 11-Segment Mode 10-Segment Mode 9-Segment Mode Display Data Memory Bit Key Scan Data 3 03 03 03 03 03 0 1A1H 1A0H 1C3H 1C2H 1C1H 1C0H T0 1A3H 1A2H 1C7H 1C6H 1C5H 1C4H T1 1A5H 1A4H 1CBH 1CAH 1C9H 1C8H T2 1A7H 1A6H 1CFH 1CEH 1CDH 1CCH T3 1A9H 1A8H 1D3H 1D2H 1D1H 1D0H T4 1ABH 1AAH 1D7H 1D6H 1D5H 1D4H T5 1ADH 1ACH 1DBH 1DAH 1D9H 1D8H T6 1AFH 1AEH 1DFH 1DEH 1DDH 1DCH T7 1B1H 1B0H 1E3H 1E2H 1E1H 1E0H T8 1B3H 1B2H 1E7H 1E6H 1E5H 1E4H T9 1B5H 1B4H 1EBH 1EAH 1E9H 1E8H T10 1B7H 1B6H 1EFH 1EEH 1EDH 1ECH T11 1B9H 1B8H 1F3H 1F2H 1F1H 1F0H T12 1BBH 1BAH 1F7H 1F6H 1F5H 1F4H T13 1BDH 1BCH 1FBH 1FAH 1F9H 1F8H T14 1BFH 1BEH(KS2) 1FFH 1FEH(KS1) 1FDH 1FCH(KS0) T15 KS2 KS1 KS0 Timing Output Tks Segment S23S22 S21 S20 S19S18 S17 S16 S15S14 S13 S12 S11S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Output Timing Output T10T11 T12 T13 T14 T15 Port H Output PH3PH2PH1PH0 (When specified by digit select register) (When none of segment output and timing output are used) 129 µPD75237 (10) Key scan registers (KS0, KS1 and KS2) The key scan registers (KS0, KS1 and KS2) are used to set the segment output data in the key scan timing mapped in the part of the display data memory (addresses 1FCH, 1FDH, 1FEH, 1FFH, 1BEH and 1BFH). KS0, KS1 and KS2 are 8-bit registers and are normally manipulated by an 8-bit manipulation instruction (the lower 4 bits can be manipulated bit-wise or in 4-bit units). Data set to KS0, KS1 and KS2 is output from the segment output pin at the key scan timing. During the key scan timing the segment output data can be immediately changed by rewriting KS0, KS1 and KS2. Key scan can be performed using the segment output. (11) Key scan flag (KSF) The key scan flag is set (“1”) during the key scan timing and is automatically reset (“0”) in all other timings. The KSF is mapped at bit 3 of address F8AH and is bit-wise testable. No write is possible. Whether the KSP is at the key scan timing can be checked by testing it. Thus, it is possible to check whether key input data is correct or not. 130 µPD75237 5. INTERRUPT FUNCTIONS The µPD75237 has eight types of interrupt sources and can generate multiple interrupts with priority order. It is also equipped with two types of test sources. INT2 is an edge detected testable input. Table 5-1 Interrupt Source Types Interrupt Source Internal/ External Interrupt Order *1 Vectored Interrupt Request Signal (Vector Table Address) 1 VRQ1 (0002H) INTBT (Reference timer interval signal from the basic interval timer) Internal INT4 (Rising or falling edge detection) External INT0 External 2 VRQ2 (0004H) INT1 External 3 VRQ3 (0006H) INTCSI0 (Serial data transfer end signal) Internal 4 VRQ4 (0008H) INTT0 (Match signal from timer event/counter 0) Internal 5 VRQ5 (000AH) INTTPG (Match signal from timer/pulse generator) Internal 6 VRQ6 (000CH) INTKS (Key scan timing signal from display controller) Internal 7 VRQ7 (000EH) INT2 *2 (Rising edge detection) External INTW *2 (Signal from watch timer) Internal (Rising and falling detected edge selection) Testable input signal (IRQ2 and IRQW set) * 1. Interrupt order is priority order to be applied when two or more interrupt requests are generated simulta- 2. neously. These are test sources. They are affected by interrupt enable flags as in the case of interrupt sources, but no vectored interrupt is generated. The µPD75237 interrupt control circuit has the following functions: (a) Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IE×××) and the interrupt master enable flag (IME). (b) Function of setting any interrupt start address. (c) Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). (d) Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.) (e) Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.) 5.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION The interrupt control circuit has a configuration shown in Fig. 5-1 and each hardware is mapped in the data memory space. 131 132 Fig. 5-1 Interrupt Control Circuit Block Diagram Internal Bus 2 2 4 IM1 IM0 (IME) 2 IPS IST Interrupt Enable Flag (IE×××) Noise Eliminator INT4 /P00 INT0 /P10 INT1 /P11 INT BT Both Edge Detector Edge Detector Edge Detector INTCSI0 INTT0 INTTPG IRQ4 IRQ0 IRQ1 IRQCSI0 Priority Control Circuit Vector Table Address Generator IRQT0 IRQTPG INTKS IRQKS INTW IRQW Rising Edge Detector VRQn IRQ2 Standby Release Signal µPD75237 INT2 /P12 Decoder IRQBT µPD75237 5.2 INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES (1) Interrupt request flag, interrupt enable flag There are ten interrupt request flags (IRQ×××) corresponding to interrupt sources (interrupt :8, test :2) as ★ shown below. INT0 interrupt request flag (IRQ0) INT1 interrupt request flag (IRQ1) Serial interface interrupt request flag (IRQCSI0) Timer/event counter interrupt request flag (IRQT0) INT2 interrupt request flag (IRQ2) INT4 interrupt request flag (IRQ4) BT interrupt request flag (IRQBT) Timer/pulse generator interrupt request flag (IRQTPG) Key scan interrupt request flag (IRQKS) Watch timer interrupt request flag (IRQW) Interrupt request flag is set to “1” at generation of an interrupt request and is automatically cleared (“0”) upon execution of interrupt service. IRQBT and IRQ4 carry out clear operation differently because they share the vector address. (See 5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING.) ★ There are ten interrupt enable flags (IE×××) corresponding to interrupt request flags as shown below. INT0 interrupt enable flag (IE0) INT1 interrupt enable flag (IE1) INT2 interrupt enable flag (IE2) Serial interface interrupt enable flag (IECSI0) Timer/event counter interrupt enable flag (IET0) Timer/pulse generator interrupt enable flag (IETPG) INT4 interrupt enable flag (IE4) BT interrupt enable flag (IEBT) Key scan interrupt enable flag (IEKS) Watch timer interrupt enable flag (IEW) When the contents of interrupt enable flag is “1”, interrupt is enabled and when it is “0”, interrupt is disabled. When the interrupt request flag is set and the interrupt enable flag has enabled interrupt, the vectored interrupt request (VRQn) is generated. This signal is also used to release the standby mode. Both the interrupt request flag and interrupt enable flag are operated by the bit manipulation instruction and 4-bit memory manipulation instruction. They can be operated directly by the bit manipulation instruction irrespective of MBE setting. The interrupt enable flag is operated by the EI IE××× and DI IE××× instruction. The SKTCLR instruction is normally used to test the interrupt request flag. When the interrupt request flag is set by an instruction even if an interrupt has not been generated, the vectored interrupt is executed in the same way as when an interrupt had been generated. RESET input clears the interrupt request flag and the interrupt enable flag (“0”) and disables all interrupts. 133 µPD75237 Table 5-2 Interrupt Request Flag Set Signals Interrupt Request Flag Interrupt Request Flag Set Signal Interrupt Enable Flag IRQBT Set by the reference time interval signal generated by the basic interval timer. IEBT IRQ4 Set upon detection of the rising or falling edge of the INT4/P00 input signal. IE4 IRQ0 Set upon detection of the INT0/P10 pin input signal edge. The detected edge is selected using the INT0 mode register (IM0). IE0 IRQ1 Set upon detection of the INT1/P11 pin input signal edge. The detected edge is selected using the INT1 mode register (IM1). IE1 IRQCSI0 Set by the serial data transfer operation end signal of the serial interface. IECSI0 IRQT0 Set by the match signal from the timer/event counter #0. IET0 IRQTPG Set by the match signal from the timer/pulse generator. IETPG IRQKS Set by the key scan timing signal from the display controller. IEKS IRQW Set by a signal from the watch timer. IEW IRQ2 Set upon detection of the rising edge of the INT2/P12 pin input signal. IE2 ★ (2) Noise eliminator and edge detection mode register INT0, INT1 and INT2 each have the configuration shown in Figs. 5-2 and 5-3 and serve as the external interrupt input capable of selecting detected edges. INT0 has a function of eliminating noise with sampling clock. Pulses having a shorter width than 2 sampling clock cycles* are eliminated as noise by noise eliminator. However, pulses having a larger width than 1 sampling clock cycle may be acknowledged as an interrupt signal depending on the sampling timing. Pulses having a larger width than 2 sampling clock cycles are securely acknowledged as an interrupt signal. INT0 has two sampling clocks, Φ and fx/64 and can select and use either clock. Selection is made by bit 3 (IM03) of the edge detection mode register (refer to Fig. 5-4). IRQ2 is set by detecting the rising edge of INT2 pin input. Edge detection mode registers (IM0 and IM1) to select detection edge have the format shown in Fig. 5-4. IM0 and IM1 each are set by a 4-bit memory manipulation instruction. RESET input clears all bits to 0 and specifies INT0, INT1 and INT2 for the rising edge. * When sampling clock is Φ : 2tCY When sampling clock is fx/64 : 128/fX Note 1. Since INT0 samples by clock, it is not operated in the standby mode. 2. Pulses are input to the INT0/P10 pin serving as a port via the noise eliminator. Thus, input pulses having two sampling clock cycles or larger. 134 µPD75237 Fig. 5-2 INT0 and INT1 Configuration Noise Eliminator INT0/ P10 INT0 IRQ0 Set Signal Edge Detector IM01, IM00 Selector IM03 2 fX 64 Φ INT1 IRQ1 Set Signal Edge Detector INT1/ P11 IM10 Input Buffer IM1 IM0 4 4 Internal Bus Fig. 5-3 INT2 Configuration Rising Edge Detector INT2/P12 INT2 IRQ2 Set Signal Input Buffer Internal Bus 135 µPD75237 Fig. 5-4 Edge Detection Mode Register Format Address FB4H Symbol 3 2 1 0 IM03 0 IM01 IM00 IM0 Detection Edge Specification 0 0 Rising edge specification 0 1 Falling edge specification 1 0 Rising and falling edge specification 1 1 Ignored (interrupt request flag not set) Sampling Clock ★ FB5 * 1. 2. Note 0 0 IM10 Φ (0.67, 1.33, 2.67, 10.7 µs: at 6.0 MHz operation)*1 1 fx/64 (10.7 µs: at 6.0 MHz operation)*2 0 Rising edge specification 1 Falling edge specification IM1 0.95, 1.91, 3.82, 15.3 µs at 4.19 MHz operation 15.3 µs at 4.19 MHz operation If the edge detection mode register is changed, the interrupt request flag may be set. To prevent that from occurring, disable interrupt and change edge detection mode register first, then enable interruption after clearing the interrupt request flag by the CLR1 instruction. If fx/64 has been selected as sampling clock by changing IM0, it is necessary to clear the interrupt request flag 16 machine cycles after the mode register has been changed. 136 0 0 µPD75237 (3) Interrupt priority select register (IPS) The interrupt priority select register is used to select high interrupt enabled for multiple interrupt and is specified by the least significant 3 bits. Bit 3 is an interrupt master enable flag (IME) to specify whether all interrupts should be disabled or not. The IPS is set by the 4-bit memory manipulation instruction and bit 3 is set/reset by the EI/DI instruction. When changing the low-order 3-bit contents of IPS, it is necessary to do so with interrupt disabled (IME = 0). RESET input clears all bits to “0”. Fig. 5-5 Interrupt Priority Select Register Address FB2H Symbol 3 2 1 0 IPS3 IPS2 IPS1 IPS0 IPS High Interrupt Select 0 0 0 None of interrupts are made high interrupts. 0 0 1 VRQ1 (INTBT/INT4) 0 1 0 VRQ2 (INT0) 0 1 1 VRQ3 (INT1) 1 0 0 VRQ4 (INTCSI0) 1 0 1 VRQ5 (INTT0) 1 1 0 VRQ6 (INTTPG) 1 1 1 VRQ7 (INTKS) Vectored interrupts on the left are taken as high interrupts. Interrupt Mask Enable Flag (IME) 0 All interrupts are disabled and vectored interrupt is not started. 1 Interrupt enable/disable is controlled by the corresponding interrupt enable flag. 137 µPD75237 5.3 INTERRUPT SEQUENCE If interrupt is generated, it is processed using the following procedure: Interrupt (INTXXX) generated IRQXXX set NO Reserved until IEXXX is set IEXXX set? YES Corresponding VRQn generated IME = 1 NO Reserved until IME is set YES Depends on the instruction being executed when IRQn is set. Is VRQn a high interrupt? Reserved until termination of operation being executed NO YES *1 IST 1,0 = 00 or 01 *1 IST 1,0 = 00 NO NO YES YES If two or more VRQn have been generated simultaneously, one VRQn is selected according to the interrupt order shown in Table 5-1. Selected VRQn Remaining VRQn PC and PSW contents are saved into the stack memory and the data *2 in the vector table corresponding to the started VRQn is set to PC, RBE and MBE. 2 Machine Cycles IST0 and IST1 contents are changed from 00 to 01 or from 01 to 10. Acknowledged IRQXXX is reset. (If the interrupt source shares the vector address, refer to 5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING.) Interrupt service program processing start * 1. IST1 and IST0 : Interrupt status flags (PSW bits 3, 2: Refer to Table 5-3 IST1 and IST0 Interrupt Servicing 2. Statuses). The start address of the interrupt service program and the MBE and RBE set values at the start of interrupt are stored in each vector table. 138 µPD75237 5.4 MULTI-INTERRUPT SERVICE CONTROL The following two methods are available for the µPD75237 to generate multi-interrupts. (1) Multi-interruption specifying high interrupt This is a standard multi-interrupt method of the µPD75237 in which one interrupt source is selected and multi-interruption (dual interrupt) is enabled. In other words, the high interrupt specified using the interrupt priority select register (IPS) is enabled when the status of the operation being executed is 0 or 1. All other interrupts (low interrupts) are only enabled when the status is 0. (Refer to Fig. 5-6 and Table 5-3.) Fig. 5-6 Multi-Interruption by High Interrupt Normal Processing (Status 0) Low or High Interrupt Servicing (Status 1) High Interrupt Servicing (Status 2) Interrupt Disable IPS Set Interrupt Enable Low or High Interrupt Generated High Interrupt Generated Table 5-3 IST1 and IST0 Interrupt Servicing Statuses IST1 IST0 Status of Servicing being Executed CPU Processing Contents Interrupt Acknowledgeable Interrupt Request 0 0 Status 0 Normal program being processed All interrupts acknowledgeable 0 1 Status 1 Low or high interrupt being servicing Only high interrupt acknowledgeable 1 0 Status 2 High interrupt being servicing All interrupts not acknowledgeable 1 1 After Interrupt Acknowledgement IST1 IST0 0 1 1 0 – – Setting prohibited When an interrupt is acknowledged, IST1 and IST0 are saved into the stack memory together with other PSW and is changed to a status higher by one level. When RET1 instruction is executed, the original IST1 and IST0 values are reset. 139 µPD75237 (2) Multi-interruption changing the interrupt status flag As is clear from Table 5-3, multi-interrupt is enabled by changing the interrupt status flag using the program. That is, multi-interrupt is enabled by changing IST1 and IST0 each to “0” using the interrupt servicing program and setting status 0. This method is used to enable multi-interrupt with two to more interrupts or multi-interruption with triple or more interrupts. Before changing IST1 and IST0, disable interruption by DI instruction. Fig. 5-7 Multi-Interruption by Changing the Interrupt Status Flag Normal Processing (Status 0) Single Interrupt Dual Interrupt Triple Interrupt Interrupt Disable IPS Set Interrupt Enable Low or High Interrupt Generated Interrupt Disable Status 1 IST Change Interrupt Enable Status 0 Low or High Interrupt Generated High Interrupt Generated Status 0 140 Status 1 Status 2 µPD75237 5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING Since the INTBT and INT4 interrupt sources share the vector table, interrupt source selection is carried out as follows: (1) When only one interrupt source is used Among the two interrupt sources sharing the vector table, set the interrupt enable flag of the necessary interrupt source (“1”) and clear the other interrupt enable flag (“0”). In this case, an interrupt request is generated by the enabled interrupt source (IE×××=1). When the request is acknowledged, the corresponding interrupt request flag is reset (as is the case with an interrupt not sharing the vector address). (2) When both interrupt sources are used Set the interrupt enable flags corresponding to the two interrupt sources (“1”). In this case, the logical sum of the interrupt request flags of the two interrupt sources becomes an interrupt request. And, if an interrupt request by the setting of one or both interrupt request flags is acknowledged, none of the interrupt request flag is reset. Accordingly, it is necessary to check in the interrupt service routing by which interrupt source the interrupt has been generated. It can be done by executing the DI instruction at the beginning of the interrupt service routine and checking the interrupt request flag by the SKTCLR instruction. 141 µPD75237 6. STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the µPD75237 to decrease power consumption in the program standby mode. 6.1 STANDBY MODE SETTING AND OPERATING STATE Table 6-1 Operation Status in Standby Mode STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Setting enabled only with main system clock. Setting enabled with either main system clock or subsystem clock. Oscillator stops only with main system clock. Stops only with CPU clock Φ (Oscillation continued). Serial interface (channel 0) Operation enabled only when external SCK0 input is selected for serial clock. Operation enabled when the main system clock oscillates or with external SCK0. Serial interface (channel 1) Operation enabled only when external SCK1 input is selected for serial clock. Operation enabled only when the main system clock oscillates. Basic interval timer Operation stopped. Operation (IRQBT set at reference time intervals). Operating State Clock oscillator Timer/event counter Operation enabled. input is specified for count clock. Watch timer Operation enabled only fXT is selected for Operation enabled. count clock. Timer/pulse generator Operation stopped. Operation enabled only when the main system clock oscillates. Event counter Operation stopped. Operation enabled only when the main system clock oscillates. A/D converter Operation stopped. Operation enabled only when the main system clock oscillates. FIP controller/driver External interrupt CPU Release signal 142 Operation enabled only when TI0 pin Operation disabled (display off mode set before disabling). INT0 operation disabled. INT1, INT2 and INT4 operation enabled. Operation stopped. Interrupt request signal or RESET input from operational hardware enabled by interrupt enable flag. µPD75237 The STOP and HALT modes are set by STOP and HALT instructions, respectively. (The two instructions are instructions to set PCC bit 3 and bit 2, respectively.) When changing the CPU operation clock with the least significant 2 bits of PCC, a delay may result from PCC rewrite to CPU clock change as shown in Table 4-1. Thus, when changing the operation clock before the standby mode is set or the CPU clock after the standby mode is released, set the standby mode after the passage of the machine cycle required for CPU clock change following PCC rewrite. In the standby mode, the data of all registers and data memories which stop operating is held. Such units include general registers, flag, mode registers and output latches. Note 1. When the STOP mode is set, X1 input is internally short-circuited to VSS (GND potential) to prevent leakage from the crystal resonator unit. Thus, the use of STOP mode is prohibited in a system using external clocks. 2. Because the interrupt request signal is used to release the standby mode, the standby mode is immediately released if there is an interrupt source with both the interrupt request flag and interrupt enable flag set. Thus, the STOP mode is set to the HALT mode just after STOP instruction execution. After waiting for the time period set by the BTM register, the operating mode is reset. 143 µPD75237 6.2 STANDBY MODE RELEASE The STOP and HALT modes each are released upon generation of the interrupt request signal* enabled by the interrupt enable flag or by RESET input. Fig. 6-1 shows release operation in each mode. * Except INT0 to INT2. Fig. 6-1 Standby Mode Release Operation (1/2) (a) Release by RESET input in STOP mode Wait (Approx. 21.8 ms : 6.0 MHz) * STOP Instruction RESET Signal Operating Mode STOP Mode Oscillation Oscillation Stop HALT Mode Operating Mode Oscillation Clock (b) Release by interrupt generation in STOP mode Wait (time set by BTM) STOP Instruction Standby Release Signal Clock Remarks (c) Operating Mode STOP Mode HALT Mode Oscillation Oscillation Stop Oscillation Operating Mode The broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (IME = 1). Release by RESET input in HALT mode Wait (Approx. 21.8 ms : 6.0 MHz) * HALT Instruction RESET Signal Operating Mode Clock * 144 31.3 ms at 4.19 MHz operation HALT Mode Oscillation Operating Mode µPD75237 Fig. 6-1 Standby Mode Release Operation (2/2) (d) Release by interrupt generation in HALT mode HALT Instruction Standby Release Signal Operating Mode HALT Mode Oscillation Clock Remarks Operating Mode The broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (IME = 1). The wait time upon STOP mode release does not include a time from STOP mode release to clock oscillation start (“a” below) whether the STOP mode is released by RESET input or interrupt generation. STOP Mode Release X1 in Voltage Waveform a Vss If the STOP mode has been released by interrupt generation, the wait time is determined by BTM setting. (Refer to Table 6-2.) Table 6-2 Wait Time Selection by BTM (When f X = 6.0 MHz) BTM3 BTM2 BTM1 BTM0 – 0 0 0 Approx. 220/fX (approx. 175 ms) – 0 1 1 Approx. 217/f X (approx. 21.8 ms) – 1 0 1 Approx. 215/f X (approx. 5.46 ms) – 1 1 1 Approx. 213/f X (approx. 1.37 ms) In all other cases Wait Time* (Values at fX = 6.0 MHz are shown in parentheses) Setting prohibited (When fX = 4.19 MHz) BTM3 BTM2 BTM1 BTM0 – 0 0 0 Approx. 220/fX (approx. 250 ms) – 0 1 1 Approx. 217/fX (approx. 31.3 ms) – 1 0 1 Approx. 215/fX (approx. 7.82 ms) – 1 1 1 Approx. 213/fX (approx. 1.95 ms) In all other cases * Wait Time* (Values at fX = 4.19 MHz are shown in parentheses) Setting prohibited Wait time does not include a time from STOP mode release to oscillation start. 145 µPD75237 6.3 OPERATION AFTER STANDBY MODE RELEASE (1) (2) If the STOP mode has been released by RESET input, normal reset operation is carried out. If the STOP mode has been released by interrupt generation, the bit 3 (IME) contents of the IPS determine whether a vectored interrupt should be executed when the CPU resumes instruction execution. (a) When IME = “0” Execution is resumed with the instruction (NOP instruction) following standby mode setting after the standby mode has been released. The interrupt request flag is held. (b) When IME = “1” Vectored interrupt is executed following execution of two instructions after the standby mode has been released. If the standby mode has been released by INTW (testable input), no vectored interrupt is generated; so the same processing as with (a) is carried out. 146 µPD75237 7. RESET FUNCTIONS The reset signal (RES) generator has a configuration shown in Fig. 7-1. Fig. 7-1 Reset Signal Generator Interrupt Reset Signal (RES) RESET Reset operation is shown in Fig. 7-2. The output buffer is turned OFF upon RESET input. Table 7-1 shows each hardware status after reset. Fig. 7-2 Reset Operation by RESET input Wait (21.8 ms : 6.0 MHz) * RESET Input Operating Mode or Standby Mode HALT Mode Operating Mode Internal Reset Operation * 31.3 ms at 4.19 MHz operation Table 7-1 shows each hardware status after reset. 147 µPD75237 Table 7-1 Hardware Statuses after Reset (1/2) Hardware Program counter (PC) Carry flag (CY) PSW RESET Input in Standby Mode RESET Input in Operation Sets the low-order 6 bits of program memory address 0000H to PC13-8 and the contents of address 0001H to PC7-0. Hold Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST1, IST2) 0 0 Bank enable flags (MBE, RBE) Sets bit 6 of program memory address 0000H to RBE and bit 7 to MBE. Data memory (RAM) Hold Undefined General registers (X, A, H, L, D, E, B, C) Hold Undefined Bank select registers (MBS, RBS) 0, 0 0, 0 Stack pointer (SP) Undefined Undefined Stack bank select register (SBS) Undefined Undefined Undefined Undefined Mode register (BTM) 0 0 Counter (T0) 0 0 FFH FFH 0 0 0,0 0, 0 0 0 Hold Hold Mode registet (TPGM) 0 0 Counter (T1) 0 0 Mode register (TM1) 0 0 Gate control register (GATEC) 0 0 Hold Undefined Operating mode register (CSIM0) 0 0 SBI control register (SBIC) 0 0 Hold Undefined 1 1 Hold Undefined Operating mode register (CSIM1) 0 0 Serial transfer end flag (EOT) 0 0 Basic interval timer Timer/event counter Counter (BT) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Watch timer Timer/pulse generator Event counter Mode register (WM) Modulo register (MODH, MODL) Shift register (SIO0) Serial interface (channel 0) Slave address register (SVA) P01/SCK0 output latch Shift register (SIO1) Serial interface (channel 1) 148 µPD75237 Table 7-1 Hardware Statuses after Reset (2/2) RESET Input in Standby Mode RESET Input in Operation 04H (EOC = 1) 04H (EOC = 1) Undefined Undefined Hold Undefined Mode register (DSPM) 0 0 Dimmer select register (DIMS) 0 0 8H 8H Display data memory Hold Hold Output buffer OFF OFF Static mode register (STATA, STATB) 0, 0 0, 0 Processor clock control register (PCC) 0 0 System clock control register (SCC) 0 0 Clock output mode register (CLOM) 0 0 Reset Reset Interrupt enable flag (IE×××) 0 0 Interrupt master enable flag (IME) 0 0 INT0 and INT1 mode registers (IM0, IM1) 0, 0 0, 0 Output buffer (ports 2 to 7) OFF OFF Output latch (ports 2 to 7) Clear Clear Input/output mode register (PMGA, PMGB) 0 0 Pull-up resistor specify register (POGA) 0 0 Output buffer OFF OFF Output latch 0 0 Output latch Hold Undefined Hardware Mode register (ADM), EOC A/D converter SA register Bit sequential buffer (BSB0 to BSB3) FIP controller/ driver Clock generator and clock output circuit Digit select register (DIGS) Interrupt request flag (IRQ×××) Interrupt function Digital port Ports 10 to 15 Port H 149 µPD75237 8. INSTRUCTION SET CHARACTERISTIC INSTRUCTIONS OF µPD75237 8.1 (1) GETI instruction The GETI instruction is a 1-byte instruction to execute the following three types of operations by referring to the 2-byte table in the program memory. It can considerably help to decrease the number of program steps. (a) (b) (c) (d) Subroutine call to 16K-byte space (0000H to 3FFFH) of table data as call instruction call address. Branch to 16K-byte space (0000H to 3FFFH) of table data as branch instruction branch address Execution of table data as 2-byte instruction (except BRCB and CALLF instructions) Execution of table data as 1-byte instruction and 2 operation codes. As shown in Fig. 3-2, the table addressed referred to by GETI instruction as 0020H to 007FH of the program memory and data can be set in 48 tables. When describing table addresses as operands, describe even addresses. Note 1. 2-byte instructions which can be referred to by GETI instruction are limited to 2-machine cycle instructions. 2. When referring to two 1-byte instructions by GETI instruction, combinations are limited as follows. 1st Byte Instruction MOV A, @HL MOV @HL, A XCH A, @HL MOV A, @DE XCH A, @DE MOV A, @DL XCH A, @DL 2nd Byte Instruction INCS DECS INCS DECS INCS L L H H HL INCS DECS INCS DECS INCS E E D D DE INCS DECS INCS DECS L L D D 3. When a branch instruction or subroutine instruction is referenced by a GETI instruction, the relevant branch destination or subroutine call address must be within 16K bytes (0000H to 3FFFH). It is not possible to use a GETI instruction to reference a branch instruction or subroutine call instruction to an address outside this range (4000H to 5F7FH). 150 µPD75237 Since the PC does not increment during execution of GETI instruction, it continues processing with the address following GETI instruction. If an instruction preceding the GETI instruction has the skip function, the GETI instruction is skipped as is the case with all other 1-byte instructions. If the instruction referred to by the GETI instruction has the skip function, an instruction following the GETI instruction is skipped. When instructions having stack effects are referred to by the GETI instruction, the following operations are carried out: • If an instruction preceding GETI instruction also has the stack effects of the same group, the execution of GETI instruction eliminates the stack effects and the instructions referred to are not skipped. • If an instruction following GETI instruction also has the stack effects of the same group, the stack effects derived from the instructions referred to are valid and the following instruction is skipped. (2) Bit manipulation instruction In addition to normal bit manipulation instructions (set and clear instructions), the bit test instruction, bit transfer instruction and bit Boolean instructions (AND, OR, XOR) are available for the µPD75237. Manipulation bits are specified by bit manipulation addressing. Three types of available addressing operations and bits manipulated by each addressing are shown below. Addressing Specifiable Peripheral Hardware Specifiable Bit Address Range RBE/MBE/IST1, IST0/IE×××/IRQ××× FB0H to FBFH PORT0 to PORT15 FF0H to FFFH pmem.@L BSB0 to BSB3, PORT0 to PORT15 FC0H to FFFH @H+mem.bit All peripheral hardware devices enabled for bit manipulation All manipulatable bits of the memory bank specified by MB fmem.bit Remarks 1. 2. ××× : 0, 1, 2, 3, 4, BT, T0, TPG, CSI0, KS, W MB = MBE• MBS 151 µPD75237 (3) Stack instructions If the instructions of the same group of the following three instructions are stacked (set at two or more continuous addresses) in the program, the stack instruction placed at the start point is executed. In the subsequent execution, one stack instruction is replaced with one NOP instruction. Group A: MOV A, #n4, Group B: MOV HL, #n8 MOV XA, #n8 (4) Radix adjustment instructions Radix adjustment instructions to adjust the result of 4-bit data addition or subtraction to any radix is available for the µPD75237. When the radix to be adjusted is m. • ADD ADDS A, #16-m • Subtract ADDC A, @HL ADDS A, #m SUBC A, @HL ADDS A, #m Using the above combinations, the addition/subtraction result with the memory addressed by the accumulator and register pair HL is adjusted to a m-ary radix. In the case of subtraction, m’s complement of the subtraction result is set to the accumulator. The overflow/underflow remains in the carry flag (in these instruction combinations, the "ADDS A, #m" instruction skip function is disabled). 152 µPD75237 8.2 INSTRUCTION SET AND OPERATION (1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (refer to the assembler specifications for details). If more than one description method is available, select one. Capital alphabetic letters, plus and minus signs are keywords. Describe them as they are. In the case of immediate data, describe appropriate numerical values or labels. Symbols in the register and flag format diagrams in chapters 3 to 5 can be described as labels in place of mem, fmem, pmem, bit, etc. (Available labels are limited for fmem and pmem. Refer to 8.1 (2) Bit manipulation instruction.) Identifier * Description Method reg reg 1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp’ rp’1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA’, BC’, DE’, HL’ BC, DE, HL, XA’, BC’, DE’, HL’ rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem pmem FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels addr1 addr caddr faddr 0000H to 5F7FH immediate data or labels 0000H to 3F7FH immediate data or labels 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (bit0 = 0) or label PORTn IE××× RBn MBn PORT0 to PORT15 IEBT, IECSI0, IET0, IETPG, IE0, IE1, IE2, IEKS, IEW, IE4 RB0 to RB3 MB0, MB1, MB2, MB3, MB15 For 8-bit data processing, only even addresses can be specified. 153 µPD75237 (2) 154 Legend for operation description A : A register; 4-bit accumulator B : B register C D E H : : : : C register D register E register H register L X XA BC : : : : L register X register Register pair (XA); 8-bit accumulator Register pair (BC) DE HL XA’ BC’ : : : : Register pair (DE) Register pair (HL) Expanded register pair (XA’) Expanded register pair (BC’) DE’ HL’ PC SP : : : : Expanded register pair (DE’) Expanded register pair (HL’) Program counter Stack pointer SBS CY PSW MBE : : : : Stack bank select register Carry flag; Bit accumulator Program status word Memory bank enable flag RBE PORTn IME IPS : : : : Register bank enable flag Port n (n = 0 to 15) Interrupt master enable flag Interrupt priority select register IE××× RBS MBS PCC : : : : Interrupt enable flag Register bank select register Memory bank select register Processor clock control register • (××) ××H : Address and bit delimiter : Contents addressed by ×× : Hexadecimal data µPD75237 (3) Description of symbols in the addressing area column *1 MB = MBE• MBS (MBS = 0, 1, 2, 3, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 2, 3, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 0000H to 3FFFH *7 addr = (Current PC) – 15 to (Current PC) – 1, (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H 1000H 2000H 3000H 4000H 5000H 0FFFH 1FFFH 2FFFH 3FFFH 4FFFH 5F7FH *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 addr1 = 0000H to 5F7FH Remarks 1. 2. 3. 4. (4) to to to to to to (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 = = = = = = 00B) or 01B) or 10B) or 11B) or 100B) or 101B) Data Memory Addressing Program Memory Addressing MB indicates accessible memory bank. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas. Description of the machine cycle column S indicates the number of machine cycles required for skip operation by an instruction having skip function. The S value varies as follows: • When not skipped .............................................................................. S = 0 • When 1-byte or 2-byte instructions are skipped ............................ S = 1 • When 3-byte instructions are skipped ............................................. S = 2 Note GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock Φ and five time periods are available according to PCC and SCC setting. (Refer to 4.2 (3) Processor clock control register (PCC).) 155 Note µPD75237 Mnemonic Operands No. of Machine Bytes Cycle Operation Addressing Area Skip Condition A, #n4 1 1 A←n4 Stack A reg1, #n4 2 2 reg1←n4 XA, #n8 2 2 XA←n8 Stack A HL, #n8 2 2 HL←n8 Stack B rp2, #n8 2 2 rp2←n8 A, @HL 1 1 A←(HL) *1 A, @HL+ 1 2+S A←(HL), then L←L+1 *1 L=0 A, @HL– 1 2+S A←(HL), then L←L–1 *1 L = FH A, @rpa1 1 1 A←(rpa1) *2 XA, @HL 2 2 XA←(HL) *1 @HL, A 1 1 (HL)←A *1 @HL, XA 2 2 (HL)←XA *1 A, mem 2 2 A←(mem) *3 XA, mem 2 2 XA←(mem) *3 mem, A 2 2 (mem)←A *3 mem, XA 2 2 (mem)←XA *3 A, reg 2 2 A←reg XA, rp' 2 2 XA←rp' reg1, A 2 2 reg1←A rp'1, XA 2 2 rp'1←XA A, @HL 1 1 A↔(HL) *1 A, @HL+ 1 2+S A↔(HL), then L←L+1 *1 L=0 A, @HL– 1 2+S A↔(HL), then L←L–1 *1 L = FH A, @rpa1 1 1 A↔(rpa1) *2 XA, @HL 2 2 XA↔(HL) *1 A, mem 2 2 A↔(mem) *3 XA, mem 2 2 XA↔(mem) *3 A, reg1 1 1 A↔reg1 XA, rp' 2 2 XA↔rp' XA, @PCDE 1 3 XA←(PC14–8+DE)ROM XA, @PCXA 1 3 XA←(PC14–8+XA)ROM XA, @BCDE 1 3 XA←(BCDE)ROM *11 XA, @BCXA 1 3 XA←(BCXA)ROM *11 Transfer MOV Table reference XCH Note 156 MOVT Instruction Group Bit transfer Note 1 µPD75237 Mnemonic No. of Machine Bytes Cycle Operation Addressing Area Skip Condition CY, fmem.bit 2 2 CY←(fmem.bit) *4 CY, pmem.@L 2 2 CY←(pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←(H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit)←CY *4 pmem.@L, CY 2 2 (pmem 7–2+L3–2.bit(L 1–0))←CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit)←CY *1 A, #n4 1 1+S A←A+n4 carry XA, #n8 2 2+S XA←XA+n8 carry A, @HL 1 1+S A←A+(HL) XA, rp' 2 2+S XA←XA+rp' carry rp'1, XA 2 2+S rp'1←rp'1+XA carry A, @HL 1 1 A, CY←A+(HL)+CY XA, rp' 2 2 XA, CY←XA+rp'+CY rp'1, XA 2 2 rp'1, CY←rp'1+XA+CY A, @HL 1 1+S A←A–(HL) XA, rp' 2 2+S XA←XA–rp' borrow rp'1, XA 2 2+S rp'1←rp'1–XA borrow A, @HL 1 1 A, CY←A–(HL)–CY XA, rp' 2 2 XA, CY←XA–rp'–CY rp'1, XA 2 2 rp'1, CY←rp'1–XA–CY A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp' rp'1, XA 2 2 rp'1←rp'1 XA A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp'1, XA 2 2 rp'1←rp'1 A, #n4 2 2 A←A n4 A, @HL 1 1 A←A (HL) XA, rp' 2 2 XA←XA rp'1, XA 2 2 rp'1←rp'1 RORC A 1 1 CY←A0, A 3←CY, An–1←An NOT A 2 2 A←A MOV1 ADDS ADDC SUBS Operation Operand SUBC *1 carry *1 *1 borrow *1 *1 AND *1 OR rp' XA *1 Note 2 XOR Note rp' XA 1. Instruction Group 2. Accumulator manipulation 157 Carry flag manipulation Compare Increment/decrement Note µPD75237 Note 158 Mnemonic Operands No. of Machine Bytes Cycle Operation Addressing Area Skip Condition reg 1 1+S reg←reg+1 reg = 0 rp1 1 1+S rp1←rp1+1 rp1 = 00H @HL 2 2+S (HL)←(HL)+1 *1 (HL) = 0 mem 2 2+S (mem)←(mem)+1 *3 (mem) = 0 reg 1 1+S reg←reg–1 reg = FH rp' 2 2+S rp'←rp'–1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA.rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY←1 CLR1 CY 1 1 CY←0 SKT CY 1 1+S NOT1 CY 1 1 INCS DECS SKE Instruction Group Skip if CY = 1 CY←CY CY = 1 Note µPD75237 Mnemonic SET1 CLR1 Memory bit manipulation SKT SKF SKTCLR AND1 OR1 XOR1 Operands No. of Machine Bytes Cycle Operation Addressing Area Skip Condition mem.bit 2 2 (mem.bit)←1 *3 fmem.bit 2 2 (fmem.bit)←1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0))←1 *5 @H + mem.bit 2 2 (H+mem3–0.bit)←1 *1 mem.bit 2 2 (mem.bit)←0 *3 fmem.bit 2 2 (fmem.bit)←0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0))←0 *5 @H+mem.bit 2 2 (H+mem3–0.bit)←0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit) = 0 *1 (@H+mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L 1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY←CY (fmem.bit) *4 CY, pmem.@L 2 2 CY←CY (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY←CY (H+mem3–0.bit) *1 Branch PC14–0←addr1 Note (Optimum instruction is selected from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 by an assembler.) addr — — $addr1 1 2 PC14–0←addr1 *7 !addr 3 3 PC14←0, PC13–0←!addr *6 PCDE 2 3 PC14–0←PC14–8+DE PCXA 2 3 PC14–0←PC14–8+XA BCDE 2 3 PC14–0←BCDE BCXA 2 3 PC14–0←BCXA BRA !addr1 3 3 PC14–0←!addr1 *11 BRCB !caddr 2 2 PC14–0←PC14, 13,12 +caddr11–0 *8 BR ★ *11 Instruction Group 159 Note µPD75237 Mnemonic Operands No. of Machine Bytes Cycle Operation Addressing Area CALL !addr 3 4 (SP–5) (SP–6) (SP–3) (SP–4)←PC14–0 (SP–2)←×, ×, MBE, RBE PC14←0, PC13–0←addr, SP←SP–6 *6 CALLA !addr1 3 3 (SP–5) (SP–6) (SP–3) (SP–4)←PC14–0 (SP–2)←×, ×, MBE, RBE PC14–0←addr1, SP←SP–6 *11 CALLF !faddr 2 3 1 3 ×, ×, MBE, RBE←(SP+4) PC14–0←(SP+1) (SP) (SP+3) (SP+2) SP←SP+6 ×, ×, MBE, RBE←(SP+4) PC14–0←(SP+1) (SP) (SP+3) (SP+2) SP←SP+6 then skip unconditionally Skip Condition Subroutine stack control (SP–5) (SP–6) (SP–3) (SP–4)←PC14–0 RET (SP–2)←×, ×, MBE, RBE PC14–0←0000, faddr, SP←SP–6 RETS 1 3+S RETI 1 3 ×, PC14, 13, 12←(SP+1) PC11–0←(SP) (SP+3) (SP+2) PSW←(SP+4) (SP+5), SP←SP+6 rp 1 1 (SP–1) (SP–2)←rp, SP←SP–2 BS 2 2 (SP–1)←MBS, (SP–2)←RBS, SP←SP–2 rp 1 1 rp←(SP+1) (SP), SP←SP+2 BS 2 2 MBS←(SP+1), RBS←(SP), SP←SP+2 2 2 IME(IPS.3)←1 2 2 IE×××←1 2 2 IME(IPS.3)←0 IE××× 2 2 IE×××←0 A, PORTn 2 2 A←PORTn XA, PORTn 2 2 XA←PORTn+1, PORTn PORTn, A 2 2 PORTn←A PORTn, XA 2 2 PORTn+1, PORTn←XA HALT 2 2 Set HALT Mode (PCC.2←1) STOP 2 2 Set STOP Mode (PCC.3←1) NOP 1 1 No Operation PUSH CPU control Input/output Interrupt control POP * IE××× DI IN OUT * * MBE = 0 or MBE = 1 and MBE = 15 must be set for execution of IN/OUT instruction Note 160 EI Instruction Group *9 Unconditional Note µPD75237 Mnemonic Special SEL * GET1 * Operands No. of Machine Bytes Cycle Operation RBn 2 2 RBS←n (n = 0 to 3) MBn 2 2 MBS←n (n = 0, 1, 2, 3, 15) 3 • TBR instruction PC13–0←(taddr)5–0+(taddr+1) taddr 1 PC14←0 -----------------------------------------------------------------• TCALL instruction (SP–5)(SP–6)(SP–3)(SP–4)←PC14–0 4 (SP–2)← ×, ×, MBE, RBE PC13–0←(taddr)5–0+(taddr+1) SP←SP–6, PC14←0 -----------------------------------------------------------------• (taddr) (taddr+1) instruction 3 executed in the case of instruction except TBR and TCALL instructions Addressing Area Skip Condition ★ ------------------------ *10 -----------------------Depends on instructions referred to. TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Note Instruction Group 161 µPD75237 8.3 (1) OPERATION CODES Description of operation code symbols R 2 R1 R0 reg P2 P1 P0 reg-pair 0 0 0 A 0 0 0 XA 0 0 1 X 0 0 1 XA' 0 1 0 L 0 1 0 HL 0 1 1 H 0 1 1 HL' 1 0 0 E 1 0 0 DE 1 0 1 D 1 0 1 DE' 1 1 0 C 1 1 0 BC 1 1 1 B 1 1 1 BC' Q2 Q 1 Q 0 reg reg1 addressing P2 P1 reg-pair 0 0 1 @HL 0 0 XA 0 1 0 @HL+ 0 1 HL 0 1 1 @HL– 1 0 DE 1 0 0 @DE 1 1 BC 1 0 1 @DL N 5 N 2 N 1 N0 @rpa @rpa1 rp' rp'1 rp1 rp rp2 IE××× 0 0 0 0 IEBT 0 0 1 0 IEW 0 0 1 1 IETPG 0 1 0 0 IET0 0 1 0 1 IECSI0 0 1 1 0 IE0 0 1 1 1 IE2 1 0 0 0 IE4 1 0 1 1 IEKS 1 1 1 0 IE1 In : Immediate data for n4 and n8 Dn : Bn : Nn : Tn : Immediate Immediate Immediate Immediate data data data data for for for for mem bit n and IE××× taddr × 1/2 An : Immediate data for [Relative address distance from branch destination address (2 to 16)]-1 Sn : Immediate data for one’s complement of [Relative address distance from branch destination address (15 to 1)] 162 µPD75237 (2) Operation codes of bit manipulation addressing *1 in the operand column indicates that the following three addressings are available. • fmem.bit • pmem.@L • @H+mem.bit The 2nd byte *2 of the operation code corresponding to the above addressing is shown below: *1 2nd Byte of Operation Code Accessible Bits 1 0 B1 B0 F3 F2 F1 F0 Manipulatable bits of FB0H to FBFH 1 1 B1 B0 F3 F2 F1 F0 Manipulatable bits of FF0H to FFFH 0 1 0 G3 G2 G1 G0 Manipulatable bits of FC0H to FFFH 0 0 B1 B0 D3 D2 D1 D0 fmem.bit pmem.@L @H+mem.bit 0 Manipulatable bits of accessible memory banks Bn : Immediate data for bit Fn : Immediate data for fmem (indicating the low-order 4-bits of address) Gn : Immediate data for pmem (indicating the bits 5 to 2 of address) Dn : Immediate data for mem (indicating the low-order 4 bits of address) 163 Note 1 µPD75237 Operation Code Mnemonic Transfer MOV Note 2 Table reference XCH Note 164 Operands B1 B2 A, #n4 0 1 1 1 I3 I2 I1 I0 reg1, #n4 1 0 0 1 1 0 1 0 I3 I2 I1 I0 1 R2 R1 R0 rp, #n8 1 0 0 0 1 P2 P1 1 I7 I6 I5 I4 I3 I2 I1 I0 A, @rpa 1 1 1 0 0 Q2 Q 1 Q 0 XA, @HL 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 @HL, A 1 1 1 0 1 0 0 0 @HL, XA 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 A, mem 1 0 1 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 XA, mem 1 0 1 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 0 mem, A 1 0 0 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 mem, XA 1 0 0 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 0 A, reg 1 0 0 1 1 0 0 1 0 1 1 1 1 R2 R1 R0 XA, rp' 1 0 1 0 1 0 1 0 0 1 0 1 1 reg1, A 1 0 0 1 1 0 0 1 0 1 1 1 0 R2 R1 R0 rp'1, XA 1 0 1 0 1 0 1 0 0 1 0 1 0 P2 P1 P0 A, @rpa 1 1 1 0 1 Q2 Q 1 Q 0 XA, @HL 1 0 1 0 1 0 1 0 0 0 0 1 0 0 A, mem 1 0 1 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 XA, mem 1 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 0 A, reg1 1 1 0 1 1 R2 R1 R0 XA, rp' 1 0 1 0 1 0 1 0 XA, @PCDE 1 1 0 1 0 1 0 0 XA, @PCXA 1 1 0 1 0 0 0 0 XA, @BCDE 1 1 0 1 0 1 0 1 XA, @BCXA 1 1 0 1 0 0 0 1 CY, ∗1 1 0 1 1 1 1 0 1 ∗2 ∗1 , CY 1 0 0 1 1 0 1 1 ∗2 0 1 0 0 0 MOVT MOV1 B3 1. Instruction Group 2. Bit transfer P2 P1 P0 0 1 P2 P1 P0 Note 1 µPD75237 Operation Code B1 B2 A, #n4 0 1 1 0 I3 I2 I1 I0 XA, #n8 1 0 1 1 1 0 0 1 A, @HL 1 1 0 1 0 0 1 0 XA, rp' 1 0 1 0 1 0 1 rp'1, XA 1 0 1 0 1 0 A, @HL 1 0 1 0 1 XA, rp' 1 0 1 0 rp'1, XA 1 0 1 A, @HL 1 0 XA, rp' 1 rp'1, XA B3 I7 I6 I5 I4 I3 I2 0 1 1 0 0 1 P2 P1 P0 1 0 1 1 0 0 0 P2 P1 P0 0 0 1 1 0 1 0 1 1 0 1 1 P2 P1 P0 0 1 0 1 0 1 1 0 1 0 P2 P1 P0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 P2 P1 P0 1 0 1 0 1 0 1 0 1 1 1 0 0 P2 P1 P0 A, @HL 1 0 1 1 1 0 0 0 XA, rp' 1 0 1 0 1 0 1 0 1 1 1 1 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 1 1 1 0 P2 P1 P0 A, #n4 1 0 0 1 1 0 0 1 0 0 1 1 I3 I2 A, @HL 1 0 0 1 0 0 0 0 XA, rp' 1 0 1 0 1 0 1 0 1 0 0 1 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 0 0 1 0 P2 P1 P0 A, #n4 1 0 0 1 1 0 0 1 0 1 0 0 I3 I2 A, @HL 1 0 1 0 0 0 0 0 XA, rp' 1 0 1 0 1 0 1 0 1 0 1 0 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 0 1 0 0 P2 P1 P0 A, #n4 1 0 0 1 1 0 0 1 0 1 0 1 I3 I2 A, @HL 1 0 1 1 0 0 0 0 XA, rp' 1 0 1 0 1 0 1 0 1 0 1 1 1 P2 P1 P0 rp'1, XA 1 0 1 0 1 0 1 0 1 0 1 1 0 P2 P1 P0 RORC A 1 0 0 1 1 0 0 0 NOT A 1 0 0 1 1 0 0 1 0 1 0 1 1 1 ADDS ADDC SUBS Operate Operands Mnemonic SUBC I1 I0 I1 I0 AND I1 I0 OR I1 I0 Note 2 XOR Note 1 1 1. Instruction Group 2. Accumulator manipulation 165 Carry flag manipulation Compare Increment/decrement Note µPD75237 Operation Code Memory bit manipulation 166 B1 B2 B3 reg 1 1 0 0 0 R2 R1 R0 rp1 1 0 0 0 1 P2 P1 0 @HL 1 0 0 1 1 0 0 1 mem 1 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 reg 1 1 0 0 1 R2 R1 R0 rp' 1 0 1 0 1 0 1 0 0 1 1 0 1 reg, #n4 1 0 0 1 1 0 1 0 I3 I2 I1 I0 0 R2 R1 R0 @HL, #n4 1 0 0 1 1 0 0 1 0 1 1 0 I3 I2 I1 I0 A, @HL 1 0 0 0 0 0 0 0 XA, @HL 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 A, reg 1 0 0 1 1 0 0 1 0 0 0 0 1 R2 R1 R0 XA, rp' 1 0 1 0 1 0 1 0 0 1 0 0 1 SET1 CY 1 1 1 0 0 1 1 1 CLR1 CY 1 1 1 0 0 1 1 0 SKT CY 1 1 0 1 0 1 1 1 NOT1 CY 1 1 0 1 0 1 1 0 mem.bit 1 0 B1 B0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 ∗1 1 0 0 1 1 0 1 mem.bit 1 0 B1 B0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 ∗1 1 0 0 1 1 0 0 mem.bit 1 0 B1 B0 0 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 ∗1 1 0 1 1 1 1 1 mem.bit 1 0 B1 B0 0 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ∗1 1 0 1 1 1 1 1 0 ∗2 SKTCLR ∗1 1 0 0 1 1 1 1 1 ∗2 AND1 CY, ∗1 1 0 1 0 1 1 0 0 *2 OR1 CY, ∗1 1 0 1 0 1 1 1 0 *2 XOR1 CY, ∗1 1 0 1 1 1 1 0 0 *2 INCS 0 0 0 0 0 0 1 0 DECS P2 P1 P0 SKE SET1 Note Operands Mnemonic CLR1 SKT SKF Instruction Group 1 1 1 1 P2 P1 P0 ∗2 ∗2 ∗2 Note µPD75237 Operation Code Operands Mnemonic B1 !addr BR Branch $addr1 (+16) to (+2) (–1) to (–15) B2 1 0 1 0 1 0 0 0 0 A3 A2 A1 A0 1 1 1 1 S3 S2 S1 S0 1 0 0 1 1 1 0 0 B3 0 addr ★ BRA !addr1 1 0 1 1 0 addr1 BRCB !caddr 0 1 0 1 PCDE 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 PCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 BCDE 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 BCXA 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 CALL !addr 1 0 1 0 1 0 1 1 0 1 CALLA !addr1 1 0 1 1 1 0 1 1 0 CALLF !faddr 0 1 0 0 0 RET 1 1 1 0 1 1 1 0 RETS 1 1 1 0 0 0 0 0 RETI 1 1 1 0 1 1 1 1 rp 0 1 0 0 1 P2 P1 1 BS 1 0 0 1 1 0 0 1 rp 0 1 0 0 1 P2 P1 0 BS 1 0 0 1 1 0 0 A, PORTn 1 0 1 0 0 0 XA, PORTn 1 0 1 0 0 PORTn, A 1 0 0 1 PORTn, XA 1 0 0 1 0 1 caddr Subroutine stack control BR addr addr1 faddr PUSH 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 N3 N2 N1 N 0 0 1 0 1 1 1 1 N3 N2 N1 N 0 0 0 1 1 1 1 1 1 N3 N2 N1 N 0 1 0 0 1 0 1 1 1 1 N3 N2 N1 N 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 N5 1 1 N2 N1 N 0 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 0 0 1 0 N5 1 1 N2 N1 N 0 HALT 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 STOP 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 NOP 0 1 1 0 0 0 0 0 RBn 1 0 0 1 1 0 0 1 0 0 1 0 0 0 N1 N 0 MBn 1 0 0 1 1 0 0 1 0 0 0 1 N3 N2 N1 N 0 taddr 0 0 T5 T4 T3 T2 T1 T0 Special CPU control Interrupt control Input/output POP IN OUT IE××× DI 0 1 0 IE××× 1 0 1 0 SEL GETI Note 0 EI Instruction Group 167 µPD75237 9. MASK OPTION SELECTION The µPD75237 has the following mask options enabling or disabling on-chip components. Pin Mask Option P40 to P43 Pull-up resistor incorporation enabled bit-wise P50 to P53 P70 to P73 Pull-down resistor incorporation enabled bit-wise S0/P120 to S3/P123 S4/P130 to S7/P133 S8/P140, S9/P141 Pull-down resistor incorporation to VLOAD enabled bit-wise S10/T15/P142, S11/T14/P143 S12/T13/P150/PH0 to S15/T10/P153/PH3 S16/P100 to S19/P103 Pull-down resistor incorporation to VLOAD or VSS bit-wise * S20/P110 to S23/P113 XT1, XT2 * Select pull-down resistor incorporation to VLOAD or VSS in 8-bit units. Note 168 Deletion of sybsystem clock oscillator feedback resistor possible In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by removing the feedback resistor from the oscillator. µPD75237 10. APPLICATION BLOCK DIAGRAM Power Failure Detection INT4 T0-T15 S0-S17 Electronic Tuner LPF PPO ANn µPD75237 Hsync Pulse Timer Tuner System Computer Remote Controlled Reception Hsync Detection L ANn Voice Lever Fluorescent Display Panel (FIP) 18 Segments × 16 Digits R Key Matrix (18 × 4) PORT7 µPC1490 LED PORTn INT0 OSD SCK1 SO1 SCK0 SO0 Remote Controlled Signal Servo IC PORTn BUZ X1 4.19/6.0 MHz Remarks X2 XT1 XT2 Mechanism BZ Piozoelectric Buzzer 32.768 kHz LPF : Low Pass Filter OSD : On Screen Display Hsync : Horizontal Synchronous 169 µPD75237 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER Power supply voltage Input voltage Output voltage Output current high SYMBOL TEST CONDITIONS UNIT –0.3 to +7.0 V VDD –40 to VDD +0.3 V –0.3 to V DD +0.3 V –0.3 to V DD +0.3 V –0.3 to +11 V –0.3 to V DD +0.3 V VDD –40 to VDD +0.3 V VDD VLOAD VI1 Except ports 4 and 5 VI2 Ports 4 and 5 VO Open-drain Pins except display output pins VOD Display output pins IOH IOL Pull-up resistor 1 pins except display output pins –15 mA S0 to S9, S16 to S23 1 pin –15 mA T0 to T15 1 pin –30 mA Total of pins except display output pins –30 mA Total of display output pins 1 pin Output current low RATING –120 mA Peak value 30 mA Effective value 15 mA 100 mA 60 mA 100 mA Total of ports Peak value 0, 2, 3 and 4 Effective value Total of ports Peak value 5 to 8 Effective value Plastic QFP 60 mA ( Ta = –40 to +70 °C ) 700 mW ( Ta = –40 to +85 °C ) Total loss PT 510 mW Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C POWER SUPPLY VOLTAGE RANGE (Ta = –40 to +85 °C) PARAMETER MIN. MAX. UNIT CPU *1 *2 6.0 V Display controller 4.5 6.0 V Time/pulse generator 4.5 6.0 V Other hardware *1 2.7 6.0 V * 1. 2. 170 TEST CONDITIONS Except the system clock osccillator, display controller and timer/pulse generator. The power supply voltage range varies, depending on the cycle time. Refer to the description of AC characteristics. µPD75237 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT X1 X2 Ceramic resonator C1 C2 X1 PARAMETER TEST CONDITIONS Oscillator frequency (fX) *1 VDD = Oscillation voltage range Oscillation stabilization time *2 After VDD reaches the minimum value in the oscillation voltage range Oscillator frequency (fX) *1 X2 Crystal resonator MIN. TYP. 2.0 2.0 4.19 VDD = 4.5 to 6.0 V C1 C2 X1 X2 External clock µPD74HCU04 Oscillation stabilization time *2 MAX. UNIT 6.2 MHz 4 ms 6.2 MHz 10 ms 30 ms X1 input frequency (fX) *1 2.0 6.2 MHz X1 high and low level widths (tXH, tXL) 81 250 ns * 1. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 2. Time required for oscillation to become stabilized after VDD application or STOP mode release. SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT XT1 Crystal resonator XT2 PARAMETER Oscillator frequency (f XT) *1 R C3 C4 XT1 XT2 TEST CONDITIONS MIN. TYP. MAX. UNIT 32 32.768 35 kHz 1.0 2 s 10 s VDD = 4.5 to 6.0 V Oscillation stabilization time *2 XT1 input frequency (f XT) *1 32 100 kHz XT1 high and low level widths (t XTH, tXTL) 5 15 µs External clock * 1. 2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time. Time required for oscillation to become stabilized after VDD application or STOP mode release. 171 µPD75237 CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT 15 pF 15 pF Input capacitance CI Output capacitance (except display output) CO Input /output capacitance CIO 15 pF Output capacitance ( display output ) CO 35 pF 172 f = 1 MHz Unmeasured pin returned to 0 V µPD75237 DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD V VIH2 Ports 0, 1, RESET, P81, P83 0.8 V DD VDD V VIH3 X1, X2, XT1 VDD–0.4 VDD V 0.65 VDD VDD V VIH4 Port 7 0.7 V DD VDD V Pull-up resistor incorporated 0.7 V DD VDD V 0.7 V DD 10 V VDD = 4.5 to 6.0 V Ports 4, 5 VIL1 Except below 0 0.3 VDD V VIL2 Ports 0, 1 RESET, P81, P83 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH All output pins V DD = 4.5 to 6.0V IOH = –1 mA VDD–1.0 except ports 4, V DD = 2.7 to 6.0V IOH = –100 µA VDD–0.5 5 and P03 Ports 3, 4, 5 VOL All output pins SB0, SB1 ILIH1 Input leakage current high Input leakage current low Output leakage current high Output leakage current low V 0.4 2.0 V V DD = 4.5 to 6.0V IOL = 1.6 mA 0.4 V V DD = 2.7 to 6.0V IOL = 400 µA 0.5 V 0.2 VDD V 3 µA 20 µA 20 µA –3 µA –20 µA Open-drain pull-up resistance ≥ 1k Ω VIN = VDD ILIH2 X1, X2, XT1 ILIH3 Ports 4, 5 ILIL1 Except below Open-drain VIN = 10 V VIN = 0 V ILIL2 X1, X2, XT1 ILOH1 Except below VOUT = VDD 3 µA ILOH2 Ports 4, 5 (Open-drain) VOUT = 10 V 20 µA ILOL1 Except below VOUT = 0 V –3 µA ILOL2 Display output VOUT = VLOAD = VDD –35 V –10 µA IOD T0 to T15 Built-in pull-down resistor (mask option) V DD = 4.5 to 6.0V IOL = 15 mA V Except below S0 to S9, S16 to S23 Display output current UNIT 0.7 V DD Open-drain Output voltage low MAX. Except below VIH5 Output voltage high TYP. VIH1 Input voltage high Input Voltage low MIN. RP7 Port 7 VIN = VDD VDD = 4.5 to 6.0 V VOD = VDD –2 V –3 –5.5 mA –15 –22 mA VDD = 4.5 to 6.0 V 20 80 20 200 kΩ 1000 kΩ RL Display output VDD –V LOAD = 35 V 25 50 135 kΩ VDD = 5 V ± 10% 15 40 80 kΩ RV1 Ports 0, 1, 2, 3, and 6 (except P00) VIN = 0 V VDD = 3 V ± 10% 30 300 kΩ Ports 4 and 5 VOUT = VDD –2.0 V VDD = 5 V ± 10% 15 70 kΩ RV2 VDD = 3 V ± 10% 10 60 kΩ Built-in pull-up resistor 40 173 µPD75237 DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V) PARAMETER TEST CONDITIONS SYMBOL IDD1 IDD2 IDD1 Supply current *1 IDD2 IDD3 IDD4 TYP. MAX. UNIT 4.5 13.5 mA 0.6 1.8 mA 600 1800 µA 200 600 µA 3 9 mA 0.5 1.5 mA 600 1800 µA 200 600 µA VDD = 3 V ± 10% 40 120 µA HALT mode VDD = 3 V ± 10% 5 15 µA 0.5 20 µA 0.3 10 µA 5 µA MIN. VDD = 5 V ± 10% *2 Operating 6 MHz crystal mode VDD = 3 V ± 10% *3 oscillation C1 = C2 = 22 pF VDD = 5 V ± 10% *4 HALT mode VDD = 3 V ± 10% Operating VDD = 5 V ± 10% *2 4.19 MHz crystal mode oscillation VDD = 3 V ± 10% *3 C1 = C2 = 22 pF VDD = 5 V ± 10% *4 HALT mode VDD = 3 V ± 10% 32 kHz crystal oscillation *5 Operating mode VDD = 5 V ± 10% IDD5 * 1. 2. 3. 4. 5. XT1 = 0 V STOP mode VDD = 3 V ± 10% Ta = 25 °C Current flowing to the built-in pull-down (pull-up) resistor excluded. When operated in the high speed mode with the processor clock control register (PCC) set to 0011. When operated in the low speed mode with PCC = 0000. Subsystem clock oscillation included. When operated with subsystem clock with system clock control register (SCC) set to 1001 and the main system clock stopped. A/D CONVERTER CHARATERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, AVDD = VDD) PARAMETER SYMBOL TEST CONDITIONS Resolution ★ 2.5 V ≤ AVREF ≤ AVDD Absolute accuracy *1 MIN. TYP. MAX. UNIT 8 8 8 bit –10 ≤ Ta ≤ +85 °C ±1.5 –40 ≤ Ta < –10 °C ±2.0 LSB Conversion time tCONV *2 168/fx µs Sampling time tSAMP *3 44/f x µs Analog input voltage VIAN Analog input impedance RAN 1000 AVREF current IAREF 1.0 AVSS AVREF V MΩ 2.0 mA * 1. 2. Absolute accuracy with any quantization error (±1/2 LSB) excluded. Time until EOC = 1 after execution of conversion start instruction (fX = 28.0 µs at 6.0 MHz, fX = 40.1 µs at 4.19 3. MHz). Time until the end of sampling after execution of conversion start instruction (fX = 7.33 µs at 6.0 MHz, fX = 10.5 µs at 4.19 MHz). 174 µPD75237 AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V) (1) Basic Operation PARAMETER SYMBOL CPU clock cycle time (minimum instruction execution time = 1 machine cycle) *1 tCY TI0 input frequency fTI TEST CONDITIONS MIN. VDD = 4.5 to 6.0 V Operation with main system clock Operation with subsystem clock MAX. UNIT 0.67 64 µs 2.6 64 µs 125 µs 0 1 MHZ 0 275 kHz 114 VDD = 4.5 to 6.0 V TI0 input high and lowlevel widths tTIH, Interrupt input high and low-level widths tINTH, tINTL RESET low-level width tRSL * 1. TYP. 122 0.48 µs 1.8 µs INT0 *2 µs INT1, 2, 4 10 µs 10 µs VDD = 4.5 to 6.0 V tTIL CPU clock (Φ) cycle time is determined by the oscillator frequency of the connected resonator, tCY VS VDD (Main System Clock in Operation) 70 the system clock control register (SCC) and the processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is 6 5 Operation Guaranteed Range 4 Cycle Time tCY [µs] shown below. 2. 2tCY or 128/fX is set by interrupt mode register (IM0) setting. 64 60 3 2 1 0.5 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 175 µPD75237 (2) Serial Transfer Operation (a) 2-wire and 3-wire serial I/O mode (SCK...Internal clock output) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT fX = 6.0 MHz 1340 ns fX = 4.19 MHz 1600 ns fX = 6.0 MHz 2680 ns fX = 4.19 MHz 3800 ns (tKCY/2)–50 ns VDD = 4.5 to 6.0 V SCK cycle time tKCY1 tKL1 VDD = 4.5 to 6.0 V SCK high and low level widths tKH1 (tKCY/2)–150 ns SI setup time (to SCK↑) tSIK1 150 ns SI hold time (from SCK↑) tKSI1 400 ns SO output delay time from SCK↓ tKSO1 * VDD = 4.5 to 6.0 V RL = 1 k Ω CL = 100 pF* 250 ns 1000 ns RL and CL are SO output line load resistance and load capacitance, respectively. (b) 2-wire and 3-wire serial I/O mode (SCK...External clock input) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns tKCY2 tKL2 VDD = 4.5 to 6.0 V SCK high and low level widths tKH2 1600 ns SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 * 176 RL = 1 k Ω CL = 100 pF* VDD = 4.5 to 6.0 V RL and CL are SO output line load resistance and load capacitance, respectively. 300 ns 1000 ns µPD75237 (c) SBI mode (SCK...Internal clock output (master)) PARAMETER SYMBOL TEST CONDITIONS MIN. tKCY3 tKL3 MAX. UNIT fX = 6.0 MHz 1340 ns fX = 4.19 MHz 1600 ns fX = 6.0 MHz 2680 ns fX = 4.19 MHz 3800 ns tKCY/2-50 ns VDD = 4.5 to 6.0 V SCK cycle time TYP. VDD = 4.5 to 6.0 V SCK high and low level widths tKH3 tKCY/2-150 ns SB0 and SB1 setup time (to SCK↑) tSIK3 150 ns SB0 and SB1 hold time (from SCK↑) tKSI3 tKCY/2 ns SB0 and SB1 output delay time from SCK↓ tKSO3 SB0, SB1↓ from SCK↑ tKSB tKCY ns SCK from SB0, SB1↓ tSBK tKCY ns SB0 and SB1 low-level widths tSBL tKCY ns SB0 and SB1 high-level widths tSBH tKCY ns * VDD = 4.5 to 6.0 V RL = 1 k Ω CL = 100 pF* 0 250 ns 0 1000 ns RL and CL are SO output line load resistance and load capacitance, respectively. (d) SBI mode (SCK...External clock input (slave)) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns tKCY4 tKL4 VDD = 4.5 to 6.0 V SCK high and low level widths tKH4 1600 ns SB0 and SB1 setup time (to SCK↑) tSIK4 100 ns SB0 and SB1 hold time (from SCK↑) tKSI4 tKCY/2 ns SB0 and SB1 output delay time from SCK↓ tKSO4 SB0, SB1↓ from SCK↑ tKSB tKCY ns SCK↓ from SB0, SB1↓ tSBK tKCY ns SB0 and SB1 low-level widths tSBL tKCY ns SB0 and SB1 high-level widths tSBH tKCY ns * RL = 1 k Ω CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns RL and CL are SO output line load resistance and load capacitance, respectively. 177 µPD75237 AC Timing Test Points (Except X1 and XT1 Inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH X1 Input V DD - 0.5 V 0.4 V 1/fXT tXTL tXTH XT1 Input VDD - 0.5 V 0.4 V TI0 Timing 1/fTI tTIL TI0 178 tTIH µPD75237 Serial Transfer Timing 3-wire serial I/O mode: tKCY1 tKH1 tKL1 SCK tSIK1 SI tKSI1 Input Data tKSO1 SO Output Data 2-wire serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSO2 tKSI2 SB0,1 179 µPD75237 Serial Transfer Timing Bus release signal transfer: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK SB0,1 tKSO3,4 Command signal transfer: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK SB0,1 tKSO3,4 Interrupt Input Timing tINTL INT0,1,2,4 RESET Input Timing tRSL RESET 180 tINTH tKSI3,4 tKSI3,4 µPD75237 DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA HOLD CHARACTERISTICS (Ta = –40 to +85 °C) PARAMETER SYMBOL Data hold power supply voltage VDDDR Data hold power supply current *1 IDDDR Release signal set time tSREL 3. MIN. TYP. MAX. UNIT 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Release by RESET Oscillation stabilization wait time *2 * 1. 2. TEST CONDITIONS 17 2 /fX ms *3 ms tWAIT Release by interrupt request Current to the on-chip pull-up (pull-down) resistor is not included. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (see below). Wait Time BTM3 BTM2 BTM1 BTM0 (Values at fX = 6.0 MHz (Values at fX = 4.19 MHz in parentheses) in parentheses) — 0 0 0 220/fX (approx. 175 ms) 220/fX (approx. 250 ms) — 0 1 1 217/fX (approx. 21.8 ms) 217/fX (approx. 31.3 ms) — 1 0 1 215/fX (approx. 5.46 ms) 215/fX (approx. 7.82 ms) — 1 1 1 213/fX (approx. 1.37 ms) 213/fX (approx. 1.95 ms) Data Hold Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Hold Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT 181 µPD75237 Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Hold Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 182 µPD75237 ★ 12. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (Main System Clock : 6.0 MHz) (Ta=25°C) PCC=0011 5000 PCC=0010 PCC=0001 PCC=0000 Main System Clock HALT Mode + 32 kHz Oscillation 1000 Power Supply Current IDD (µA) 500 Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 Crystal Resonator XT2 6.0MHz Crystal Resonator 32.768kHz 22pF 22pF 330kΩ 5 22pF 22pF 1 0 1 2 3 4 5 6 7 Power Voltage VDD (V) 183 µPD75237 IDD vs VDD (Main System Clock : 4.19 MHz) (Ta=25°C) 5000 PCC=0011 PCC=0010 PCC=0001 PCC=0000 Main System Clock HALT Mode + 32 kHz Oscillation 1000 Power Supply Current IDD (µA) 500 Subsystem Clock Operating Mode 100 50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode 10 X1 X2 XT1 Crystal Resonator XT2 4.19MHz Crystal Resonator 32.768kHz 30pF 22pF 330kΩ 5 30pF 1 0 1 2 3 4 5 Power Voltage VDD (V) 184 6 7 22pF µPD75237 13. PACKAGE INFORMATION 94 PIN PLASTIC QFP ( 20) F2 A B 71 72 48 47 F1 Q R S C D detail of lead end 94 1 G1 24 23 G2 H I M J M P K N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.2±0.4 0.913 +0.017 –0.016 B 20.0±0.2 0.787+0.009 –0.008 C 20.0±0.2 0.787 +0.009 –0.008 D 23.2±0.4 0.913 +0.017 –0.016 F1 1.6 0.063 F2 0.8 0.031 G1 1.6 0.063 G2 0.8 H 0.35±0.10 0.031 0.014 +0.004 –0.005 I 0.15 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P Q 3.7 0.146 R 0.1±0.1 5 °±5° 0.004±0.004 5°±5° S 4.0 MAX. 0.006 0.158 MAX. S94GJ-80-5BG-3 185 µPD75237 ★ 14. RECOMMEDED SOLDERING CONDITIONS The µPD75237 should be soldered and mounted under the conditions recommended in the table below. For soldering methods and conditions other than those recommended below, contact our salesman. Table 14-1 List of Recommended Soldering Conditions Product Name µPD75237GJ-×××-5BG Package Recommended Condition Symbol 94-pin plastic QFP WS60-107-1 IR30-107-1 VP15-107-1 Pin part heating Table 14-2 Soldering Conditions Recommended Condition Symbol Soldering Method Soldering Conditions Wave Soldering Solder bath temperature: 260 °C or less Duration: 10 sec. max. Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 °C) Preheating temperature: 120 °C max. (package surface temperature) Infrared reflow Package peak temperature: 230 °C Duration: 30 sec. max. (at 210 °C or above) Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 °C) VP15-107-1 VPS Package peak temperature: 215 °C Duration: 40 sec. max. (at 200 °C or above) Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 °C) Pin part heating Pin part heating Pin part temperature: 300 °C or less Duration: 3 sec. max. (Per device side) WS60-107-1 IR30-107-1 * For the storage period after dry-pack decompression, storage conditions are max. 25°C, 65% RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). Remarks 186 For details of recommended soldering conditions for the surface mounting type, refer to the document “Semiconductor Device Mount Technology” (IEI-1207). µPD75237 APPENDIX A. Item LIST OF µPD75238 SERIES PRODUCT FUNCTIONS Product Name ROM µPD75217 µPD75236 µPD75237 24448 × 8 16256 × 8 24448 × 8 Main system clock selected Instruction cycle 0.95 µs/1.91 µs/ 15.3 µs (Operation at 4.19 MHz) Subsystem clock selected 0.67 µs/1.33 µs/2.67 µs/10.7 µs (Operation at 6.0 MHz) 122 µs (Operation at 32.768 kHz) 64 Input 8 16 20: 8 for LED drive 24: 12 for LED drive 5 24 None 8: 8-bit resolution 26: 40 V max. 34: 40 V max. 9 to 16 segments 9 to 24 segments Ouptut High-voltage output No. of segments No. of digits 9 to 16 digits Timer 4 channels Serial interface 1 channel 3-wire Interrupt source 10 5 channels 2 channels SBI/3-wire 3-wire 11 –40 to +85 °C Operating temperature range Operating voltage Package 0.95 µs/1.91 µs/ 3.82 µs/15.3 µs (Operation at 4.19 MHz) 33 A/D converter FIP controller/ driver 1024 × 4 Total Input/output µPD75P238 32640 × 8 768 × 4 RAM I/O line FIP dual-function pin included and FIP dedicated pin excluded µPD75238 –40 to +70 °C 2.7 to 6.0 V 64-pin plastic shrink DIP 64-pin plastic QFP 94-pin plastic QFP 94-pin plastic QFP 94-pin ceramic LCC with window 187 ★ µPD75237 APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for the development of systems using the µPD75237. Language Processor Host Machine RA75X relocatable assembler PC-9800 series IBM PC series OS MS-DOS Ver.3.10 to Ver.3.30C PC DOS (Ver.3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13RA75X 5-inch 2HD µS5A10RA75X 5-inch 2HC µS7B10RA75X Hardware PROM Write Tools PG-1500 PROM programmer which can easily program representative 256K-bit to 1M-bit PROMs and single-chip microcomputers with on-chip PROM from the keyboard or by remote control by connecting a board provided and a separately sold socket board. PA-75P238GJ PROM programmer adapter for µPD75P238 used in connection with PG-1500. PG-1500 is connected to the host machine via serial and parallel interfaces to control the PG1500 on the host machine. Software ★ Host Machine PG-1500 controller PC-9800 series IBM PC series 188 OS MS-DOS Ver.3.10 to Ver.3.30C PC DOS (Ver.3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 5-inch 2HC µS7B10PG1500 µPD75237 Debugging Tools IE-75000-R * Hardware IE-75000-R-EM IE-75001-R EP-75238GJ-R IE-9200G-94 The IE-75000-R is an in-circuit emulator corresponding to the 75X series. Use the IE-75000-R and emulation probe in combinations for the development of µPD75237. Debugging can be carried out efficiently by connecting the IE-75000-R to the host machine and the PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R. It is incorporated in the IE-75000-R. Use the IE-75000-R-EM and IE-75000-R or IE-75001-R in combinations for the evaluation of µPD75237. The IE-75001-R is an in-circuit emulator corresponding to the 75X series. Use the IE-75001-R and emulation board IE-75000-R-EM which is sold separately, and emulation probe in combinations for the development of µPD75237. Debugging can be carried out efficiently by connecting the IE-75001-R to the host machine and the PROM programmer. Emulation probe for µPD75237 (94-pin plastic QFP). Used in combination with the IE-75000-R or IE-75001-R. 94-pin conversion socket EV-9200G-94 is also provided to facilitate connection with the user system. Software Controls the IE-75000-R and IE-75001-R on the host machine with the IE-75000-R and IE75001-R, connected to the host machine via RS-232-C. Host Machine IE control program PC-9800 series IBM PC series * OS MS-DOS Ver.3.10 to Ver.3.30C PC DOS (Ver.3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 5-inch 2HC µS7B10IE75X Maintenance product 189 190 Development Tool Configuration In-Circuit Emulator Emulation Probe IE-75000-R Centronics I/F IE-75001-R *1 RS-232-C EP-75238GJ-R IE-75000-R-EM IE Control Program Host Machine PC-9800 Series IBM PC Series Symbolic Debugging Possible *2 User System PG-1500 Controller On-Chip PROM Product PROM Programmer µ PD75P238GJ/KF PG-1500 + Relocatable Assembler Programmer Adapter PA-75P238GJ * 1. EV-9200G-94 µPD75237 2. The IE-75001-R does not incorporate the IE-75000R-EM (sold separately). µPD75237 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. FIP ® is a trademark of NEC Corporation. MS-DOS is a trademark of MicroSoft Corporation. PC DOS is a trademark of IBM Corporation. M4 92.6