DATA SHEET MOS INTEGRATED CIRCUIT µPD75402A(A) 4 BIT SINGLE-CHIP MICROCOMPUTER The µPD75402A(A) is a CMOS single-chip microcomputer which uses the 75X series architecture. It operates at high speed with a minimum instruction execution time of 0.95 µs. The µPD75P402 is also available for system development evaluation. It contains one-time PROM instead of mask ROM used in the µPD75402A(A). The following user's manual describes the details of the functions of the µPD75402A(A). Be sure to read it before designing an application system. µPD75402A User's Manual: IEU-644 FEATURES • More reliable than the µPD75402A • High-speed operation with a minimum instruction execution time of 0.95 µs (when the microcomputer operates at 4.19 MHz) • Low voltage and low-speed instruction execution time of 15.3 µ s (when the microcomputer operates at 4.19 MHz) • • • • Memory mapping by on-chip peripheral hardware NEC standard serial bus interface (SBI) 8-bit basic interval timer (watchdog timer applicable) Interrupt function • Three vectored interrupts (one external and two internal interrupts) • One external test input • Clock output function (remote controller output applicable) • Capable of specifying the incorporation of 16 pull-up resistors by software APPLICATIONS Electronic units for automobiles, and suchlike ORDERING INFORMATION Part number Package µPD75402AC(A)-××× Quality grade 28-pin plastic DIP (600 mil) Special µPD75402ACT(A)-××× 28-pin plastic shrink DIP (400 mil) Special µPD75402AGB(A)-×××-3B4 44-pin plastic QFP (10 × 10 mm) Special Remark ××× indicates the ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-2841B (O.D.No. IC-8273B) Date Published November 1993 P Printed in Japan Major changes in this revision are indicated by stars ( ) in the margins. 1991 11990 © © NEC CORPORATION µPD75402A(A) DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75402A Product Item Quality grade µPD75402A(A) µPD75402A Special Standard FUNCTIONAL OVERVIEW Item Function Number of basic instructions 37 Minimum instruction execution time • • Built-in memory ROM 1920 × 8 bits RAM 64 × 4 bits 0.95, 1.91, or 15.3 µs (when operating at 4.19 MHz) Switchable among three speeds General register 4 bits × 4 or 8 bits × 2 (memory mapping) I/O line • • • CMOS input ports : 6 lines CMOS I/O ports : 12 lines (8 lines can drive the LED directly.) N-ch open-drain I/O ports : 4 lines (All lines can drive the LED directly.) Pull-up resistor • • Capable of controlling the incorporation of 16 pull-up resistors by software Capable of controlling the incorporation of 4 pull-up resistors by mask option Clock output • • 1.05 MHz, 524 kHz, or 65.5 kHz (when operating at 4.19 MHz) Applicable to remote controller output Timer/counter 8-bit basic interval timer (watchdog timer applicable) Serial interface • • Vectored interrupt One external and two internal interrupts Test input One external input (See Chapter 6 for details.) Standby STOP/HALT mode Instruction set • • • • Bit manipulation instructions (set, clear, test, and Boolean operation) 1-byte relative branch instructions 4-bit operation instructions (add, Boolean operation, and compare) 4- and 8-bit transfer instructions Package • • • 28-pin plastic DIP (600 mil) 28-pin plastic shrink DIP (400 mil) 44-pin plastic QFP (10 × 10 mm) 2 8 bits Two transfer modes (three-wire synchronous mode and SBI mode) µPD75402A(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ...................................................................................... 4 2. BLOCK DIAGRAM ...................................................................................................................... 6 3. PIN FUNCTIONS ....................................................................................................................... 7 3.1 PORT PINS ..................................................................................................................................... 7 3.2 NON-PORT PINS ........................................................................................................................... 8 3.3 PIN INPUT/OUTPUT CIRCUITS .................................................................................................. 8 3.4 SELECTION OF A MASK OPTION ........................................................................................... 10 3.5 HANDLING UNUSED PINS ......................................................................................................... 11 3.6 NOTES ON USING THE P00 AND RESET PINS ................................................................. 11 4. MEMORY CONFIGURATION ................................................................................................... 12 5. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 14 5.1 PORTS .............................................................................................................................................. 14 5.2 CLOCK GENERATOR .................................................................................................................... 15 5.3 CLOCK OUTPUT CIRCUIT ........................................................................................................... 16 5.4 BASIC INTERVAL TIMER ............................................................................................................ 17 5.5 SERIAL INTERFACE ...................................................................................................................... 18 6. INTERRUPT FUNCTION ........................................................................................................... 20 7. STANDBY FUNCTION .............................................................................................................. 22 8. RESET FUNCTION .................................................................................................................... 23 9. INSTRUCTION SET ................................................................................................................... 25 10. ELECTRICAL CHARACTERISTICS ........................................................................................... 29 11. PACKAGE DIMENSIONS .......................................................................................................... 38 12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 42 APPENDIX A DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75P402 ................... 43 APPENDIX B DEVELOPMENT TOOLS ......................................................................................... 44 APPENDIX C RELATED DOCUMENTS ........................................................................................ 45 ★ 3 µPD75402A(A) 1. PIN CONFIGURATION (TOP VIEW) 28-pin plastic DIP (600 mil), 28-pin plastic shrink DIP (400 mil) Note 1 28 VDD RESET 2 27 X1 P00 3 26 X2 P01/SCK 4 25 P12 /INT2 P02/SO/SB0 5 24 P10/INT0 P03/SI 6 23 P23 P50 7 22 P22 /PCL P51 8 21 P21 P52 9 20 P20 P53 10 19 P63 P30 11 18 P62 P31 12 17 P61 P32 13 16 P60 VSS 14 15 P33 : Port 0 µ PD75402AC(A)/CT(A)- ××× P00 - P03 NC SCK : Serial clock I/O P10 and P12: Port 1 SO/SB0 : Serial output/input-output P20 - P23 : Port 2 SI : Serial input P30 - P33 : Port 3 PCL : Clock output P50 - P53 : Port 5 INT0 : External vectored interrupt input P60 - P63 : Port 6 INT2 : External test input X1 and X2 : Oscillating pins RESET : Reset input VDD : Power supply VSS : Ground NC : No connection Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin directly to the VSS pin. 4 µPD75402A(A) NC NC NC P50 P03/SI P02/SO/SB0 40 39 38 37 36 35 NC NC 41 P52 44 43 42 P53 P51 44-pin plastic QFP (10 × 10 mm) P30 1 34 33 P31 2 32 P00 P32 3 31 RESET NC 4 30 NC VSS 5 29 NC NC 6 28 NC NC 7 27 NC P33 8 26 VDD P60 9 25 X1 P61 10 24 X2 NC 11 12 13 14 NC 15 16 17 18 19 20 21 23 22 P21 NC VSS NC P22/PCL P23 P10/INT0 P12/INT2 P20 P63 P62 µ PD75402AGB(A)- ××× -3B4 P01/SCK Note Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin (pin 30) directly to the VSS pin. 5 Program counter (11) CY ALU SCK Serial interface INTCSI INT0 INT2 General register ROM Program memory 1920 × 8 bits Decode and control 4 P00 - P03 Port 1 2 P10, P12 Port 2 4 P20 - P23 Port 3 4 P30 - P33 Port 5 4 P50 - P53 Port 6 4 P60 - P63 SP INTBT SI SO/SB0 Port 0 2. BLOCK DIAGRAM 6 Basic interval timer RAM Data memory 64 × 4 bits Interrupt control fXX/2N Clock output control Clock generator X1 X2 CPU φ Standby control VDD Clock VSS RESET µPD75402A(A) PCL Clock divider µPD75402A(A) 3. 3.1 PIN FUNCTIONS PORT PINS Pin I /O Dualfunction pin P00 Input – P01 I/O SCK P02 I/O SO/SB0 P03 Input SI P10 Input INT0 P12 INT2 P20 I/O – P21 – P22 PCL P23 – Function 4-bit input port (port 0) P01 to P03 allow the connection of built-in pull-up resistors to be specified in units of three bits by software. 2-bit input port (port 1) P10 connects with the built-in noise eliminator using a sampling clock. P12 connects with the built-in noise eliminator using an analog delay. P12 allows the connection of built-in pull-up resistor to be specified by software. 4-bit I/O port (port 2) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. P30 - P33 I/O – Programmable 4-bit I/O port (port 3) Allow I/O specification bit by bit. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED. P50 - P53 I/O – 4-bit N-ch open-drain I/O port (port 5) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified bit by bit by mask option. Can directly drive LED. P60 - P63 I/O – 4-bit I/O port (port 6) Allow I/O specification in units of four bits. Allow the connection of built-in pull-up resistors to be specified in units of four bits by software. Can directly drive LED. Remarks 1. The µPD75402A(A) cannot perform 8-bit I/O with two ports as a pair. 2. See Chapter 8 for each pin status during resetting. 7 µPD75402A(A) 3.2 NON-PORT PINS Pin I /O Dualfunction pin INT0 Input P10 Edge detection vectored interrupt request input pin (A detected edge can be selected by the mode register.) Connects with the built-in noise eliminator using a sampling clock. INT2 Input P12 Edge detection external test input pin (A rising edge is detected.) SI Input P03 Serial data input pin SO I/O P02/SB0 SCK I/O P01 SB0 I/O P02/SO Serial bus I/O pin PCL I/O P22 Clock output pin X1, X2 Input – Pin for connection to a crystal/ceramic resonator for system clock generation. An external clock is applied to X1, and its reverse phase to X2. RESET Input – System reset input pin, which connects with the built-in noise eliminator using an analog delay. VDD – – Positive power supply pin VSS – – Ground potential pin – – No connection NC Note Function Serial data output pin Serial clock I/O pin Remark See Chapter 8 for each pin status during resetting. Note Connect the NC pin directly to the VSS pin when the µPD75402A(A) shares the printed circuit board with the µPD75P402 in emulation. 3.3 PIN INPUT/OUTPUT CIRCUITS The I/O circuits of the µPD75402A(A) are roughly shown on the next and subsequent pages. Table 1-1 I/O Circuit Type of Pin Pin P00 I /O type B Pin I/O type P20, P21, and P23 E-B P01 /SCK F -A P22 /PCL P02 / SO/ SB0 F -B P30 - P33 E-B P03 / SI B -C P50 - P53 M P10 / INT0 B P60 - P63 E-B P12 /INT2 B -C RESET Remark The types in circles have a Schmitt-triggered input. 8 B µPD75402A(A) (1/2) Type A (For type E-B) Type D (For type E-B, F-A) VDD VDD Data P-ch P-ch OUT IN N-ch CMOS input buffer Type B Output disable N-ch Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis Type F-A Type B-C VDD VDD P.U.R. P.U.R. P-ch P.U.R. enable P.U.R. enable P-ch Data IN/OUT Type D Output disable IN Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor 9 µPD75402A(A) (2/2) Type F-B Type M VDD VDD P.U.R. enable (Mask option) P.U.R. P.U.R. enable Output disable (P) P-ch VDD Data P-ch IN/OUT Data Output disable Output disable N-ch (Withstand voltage: +10 V) N-ch Output disable (N) Input buffer with an intermediate withstand voltage of +10 V P.U.R.: Pull-Up Resistor 3.4 IN/OUT P.U.R.: Pull-Up Resistor SELECTION OF A MASK OPTION The following mask options are provided for pins: P50 - P53 10 1 Pull-up resistors connected (Either can be specified bit by bit.) 2 No pull-up resistors connected µPD75402A(A) 3.5 HANDLING UNUSED PINS Pin Recommended connection method P00 Connected to the VSS pin P01 - P03 • P10, P12 • P20 - P23 • P30 - P33 P50 - P53 P60 - P63 NC • When a pull-up resistor is contained Connected to the VDD pin When a pull-up resistor is not contained Connected to the VSS or VDD pin When a pull-up resistor is contained Input mode : Connected to the VDD pin Output mode : Open When a pull-up resistor is not contained Input mode : Connected to the VSS or VDD pin Output mode : Open Open or directly connected to the VSS pin Note Note When the µPD75402A(A) shares the printed circuit board with the µ PD75P402, connect the NC pin directly to VSS pin. 3.6 NOTES ON USING THE P00 AND RESET PINS The P00 and RESET pins have the test mode selecting function for testing the internal operation of the µPD75402A(A) (IC test), besides the functions shown in Sections 3.1 and 3.2. Applying a voltage exceeding VDD to the P00 and/or RESET pin causes the µPD75402A(A) to enter the test mode. When noise exceeding VDD comes in during normal operation, the device is switched to the test mode. For example, when the wiring from the P00 or RESET pin is too long, noise voltage induced on the wiring is applied to the pin, driving the voltage at the pin above VDD, which may cause malfunction. When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise yet arises, use an external part to suppress it as shown below. • Connect a diode with low VF (0.3 V or lower) • Connect a capacitor between the pin and VDD. between the pin and VDD. VDD Diode with low VF VDD VDD P00, RESET VDD P00, RESET 11 µPD75402A(A) 4. MEMORY CONFIGURATION • Program memory (ROM): 1920 × 8 bits (000H to 77FH) • • 000H and 001H : Vector table which contains the program start address after reset • 002H to 009H : Vector table which contains the program start addresses when interrupts occur Data memory • Data area : 64 × 4 bits (000H to 03FH) • Peripheral hardware area: 128 × 4 bits (F80H to FFFH) Fig. 4-1 Program Memory Map 7 6 5 4 3 0 0 0 0 0 0 Address 000H Reset start address (eight low-order bits) 001H 002H 0 0 003H 004H 009H 77FH 12 0 0 0 INTBT start address (three high-order bits) INTBT start address (eight low-order bits) 0 0 0 0 0 0 0 0 0 0 Entry address specified in CALLF !faddr instruction INT0 start address (three high-order bits) INT0 start address (eight low-order bits) 005H 008H Reset start address (three high-order bits) INTCSI start address (three high-order bits) INTCSI start address (eight low-order bits) Branch address specified in BRCB !caddr instruction Relative branch address specified in BR $addr instruction –15 to –1, +2 to +16 µPD75402A(A) Fig. 4-2 Data Memory Map General register area 000H 003H (4 × 4) 004H Data area Static RAM (64 × 4) Bank 0 (64 × 4) 020H Stack area (32 × 4) 03FH No memory F80H Peripheral hardware area 128 × 4 Bank 15 FFFH 13 µPD75402A(A) 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS The µPD75402A(A) has the following three types of I/O port: • 6 CMOS input pins (PORT0 and PORT1) • 12 CMOS I/O pins (PORT2, PORT3, and PORT6) • 4 N-ch open-drain I/O pins (PORT5) Total: 22 pins Table 5-1 Functions of Ports Port name Function Operation and feature PORT0 PORT1 4-bit Input Allows read and test at any time regardless of the operation modes of dual function pins. PORT3 Note 4-bit I/O Allows input or output mode setting bit by bit. PORT2 PORT6 Note PORT5 Note 4-bit I/O (N-ch open-drain I/O with a withstand voltage of 10 V) Also used for SO/SB0, SI, SCK, INT0, and INT2. — Allows input or output mode setting in units of 4 bits. Port 2 is also used for PCL. Allows input or output mode setting in units of 4 bits. This port can incorporate a pull-up resistor as a mask option bit by bit. Note PORT3, PORT5, and PORT6 can directly drive the LED. 14 Remarks µPD75402A(A) 5.2 CLOCK GENERATOR Operation of the clock generator is specified by the processor clock control register (PCC). The instruction execution time is variable. • 0.95 µs, 1.91 µs, 15.3 µs (when fXX is 4.19 MHz.) Fig. 5-1 Block Diagram of the Clock Generator X1 VDD · Basic interval timer (BT) · Clock output circuit · Serial interface · INT0 noise eliminator 1/16 to 1/512 System clock oscillator fXX or fX Frequency divider 1/2 1/16 X2 Frequency divider Selector Oscillation stops. · CPU · INT0 noise eliminator · Clock output circuit PCC PCC0 Internal bus Φ 1/4 PCC1 HALT flipflop 4 PCC2 HALT* S PCC3 STOP* R All bits are cleared. STOP flipflop PCC2 is cleared. Q Q RESET input rising edge detection signal S RESET input falling edge detection signal R Standby release signal from interrupt control circuit Remarks 1. fXX = Crystal/ceramic oscillated frequency 2. fX = External clock frequency 3. Φ = CPU clock 4. An asterisk (*) indicates instruction execution. 5. PCC: Processor clock control register 6. One clock cycle (t CY) of Φ is equal to one machine cycle of an instruction. See AC characteristics of Chapter 10 for details of tCY. 15 µPD75402A(A) 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit, which outputs clock pulses from pin P22/PCL, is used for supplying clock pulses for peripheral LSIs or for remote control output. • Clock output (PCL): 1.05 MHz, 524 kHz, 65.5 kHz (when fXX is 4.19 MHz). Fig. 5-2 shows the configuration of the clock output circuit. Fig. 5-2 Configuration of the Clock Output Circuit From the clock generator Φ Output buffer Selector P22/PCL f XX /26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Remark The clock output circuit is designed not to output high-frequency pulses when clock output is switched between the enable and disable states. 16 µPD75402A(A) 5.4 BASIC INTERVAL TIMER The basic interval timer provides the following functions: • Interval timer operation that generates a reference time interrupt • Can be used as a watchdog timer for detecting program crashes • Reading the count value Fig. 5-3 Configuration of the Basic Interval Timer From the clock generator Clear Clear fXX /25 Set Basic interval timer (8-bit frequency divider) MPX fXX /29 BT BTM3 BTM2 1 4 1 BT interrupt request flag IRQBT Vectored interrupt request signal BTM 8 Internal bus 17 µPD75402A(A) 5.5 SERIAL INTERFACE The serial interface has the following modes: • Three-wire serial I/O mode (MSB is transferred first.) • SBI mode (MSB is transferred first.) The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices. The SBI mode enables communication with two or more devices. 18 Fig. 5-4 Block Diagram of the Serial Interface Internal bus 8 CSIM Bit test 8 Bit manipulation 8 Slave address register (SVA) Address comparator Bit test SBIC (8) Match signal (8) RELT CMDT P03/SI BSYE (8) ACKE Shift register (SIO) SET CLR SO Iatch D Q ACKT Selector P02 /SO/SB0 Bus-release/ command/ acknowledge detector P01/SCK Serial clock counter RELD CMDD ACKD INTCSI IRQCSI Set signal INTCSI control circuit 4 fXX/2 MPX External SCK 19 µPD75402A(A) Serial clock control circuit Busy/ acknowledge output circuit µPD75402A(A) 6. INTERRUPT FUNCTION The µPD75402A(A) has three interrupt sources and each of them has the interrupt vector table. The µPD75402A(A) is also provided with one edge-sensitive testable input signal. When a vectored interrupt request is issued, the PC and PSW are saved in the stack, and the contents of the vector table which corresponds to the issued vectored interrupt are set in the PC as a start address. The program branches to the interrupt service routine. These operations are performed automatically by the hardware. The flag is set by detecting the edge of the testable input signal, but a vectored interrupt request is not issued. During execution of the interrupt service routine, the µPD75402A(A) does not accept the other interrupt requests. Unlike the other 75X series, the µPD75402A(A) cannot handle multiple interrupts. The interrupt control circuit of the µPD75402A(A) has the following functions. • Vectored interrupt function under hardware control which can determine whether to accept an interrupt by an interrupt enable flag (IE×××) and an interrupt master enable flag (IME). • Any interrupt start address can be set. • Test function of an interrupt request flag (IRQ×××) (Software can confirm that an interrupt occurs.) • Release of the standby (HALT) mode (An interrupt to be released by an interrupt enable flag can be selected from interrupts other than INT0.) 20 Fig. 6-1 Block Diagram of Interrupt Control Circuit 3 IME Interrupt enable flag (IE×××) IM0 IST0 Decoder INT BT INT0/ P10 Note 1 Edge detection circuit VRQ1 IRQBT VRQ2 IRQ0 VRQ3 INTCSI INT2/ P12 Note 2 Rising edge detection circuit IRQCSI Priority control circuit Vector table address generator IRQ2 2. Noise eliminator using analog delay Standby release signal 21 µPD75402A(A) Notes 1. Noise eliminator using the sampling clock µPD75402A(A) 7. STANDBY FUNCTION To reduce the power consumption when the program is in the wait state, the µPD75402A(A) has two standby modes, STOP and HALT. Table 7-1 Operation Statuses in the Standby Mode STOP mode HALT mode Instruction to be used to set mode STOP instruction HALT instruction Operation status Clock generator Oscillation of the system clock stops. Only the CPU clock (Φ) stops, but oscillation continues. Basic interval timer Operation stops. Operates. (IRQBT is set at every reference time interval.) Serial interface Operable only when the external SCK input is selected for the serial clock. Operable Clock output circuit Operation stops. Clocks other than CPU clock (Φ) can be output. External interrupt INT2 pin is usable. INT0 pin cannot be used. INT2 pin is usable. INT0 pin cannot be used. CPU Operation stops. Release signal 22 RESET input RESET input or interrupt request signals enabled by the interrupt enable flags µPD75402A(A) 8. RESET FUNCTION When a low level signal is input to the RESET input pin, the state changes to the system reset. Table 8-1 shows the statuses of the hardware. When the RESET signal rises from the low level to the high level, the reset state is released. The three loworder bits of the reset vector table whose address is 000H is set in bits 10 to 8 of the program counter (PC) and the contents of the reset vector table whose address is 001H is set in bits 7 to 0 of the PC. The program branches to that address and starts execution, i.e., the reset start address is programmable. Initialize contents of registers in a program if necessary. The RESET pin connects to the Schmitt-trigger circuit whose threshold level has hysteresis in the chip. This pin is also connected to the noise eliminator using an analog delay to eliminate narrow noise and prevent errors caused by noise. (See Fig. 8-1.) For the power-on reset operation, be sure to allow sufficient time for oscillation to settle between power on and acceptance of the reset signal (see Fig. 8-2). Fig. 8-1 Acceptance of the Reset Signal RESET Analog delay Elimination as noise. The instruction which is stored at the reset branch address is executed. Content of the reset Analog Analog vector table is set delay delay to the PC (the initialization of the PC). This low level The reset is signal is accepted released. as the reset signal. Fig. 8-2 Power-On Reset Operation VDD RESET Oscillation settling time Analog delay Content of the reset vector table is set to the PC (the initialization of the PC). The instruction which is stored at the reset branch address is executed. The reset is released. 23 µPD75402A(A) Table 8-1 Hardware Statuses after Reset Operations Hardware RESET input in standby mode RESET input during operations Set the three low-order bits of address 000H in program memory in PC bits 10 to 8 and set the contents of address 001H in PC bits 7 to 0. Set the three low-order bits of address 000H in program memory in PC bits 10 to 8 and set the contents of address 001H in PC bits 7 to 0. Retained Undefined Skip flag (SK0 - SK2) 0 0 Interrupt status flag (IST0) 0 0 Undefined Undefined Retained Note Undefined Retained Undefined Undefined Undefined 0 0 Retained Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Retained Undefined Program counter (PC) PSW Carry flag (CY) Stack pointer (SP) Data memory (RAM) General register (X, A, H, L) Basic interval timer Counter (BT) Serial interface Shift register (SIO) Mode register (BTM) Slave address register (SVA) Clock generator and clock output circuit Processor clock control register (PCC) 0 0 Clock output mode register (CLOM) 0 0 Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) Interrupt enable flag (IE×××) 0 0 Interrupt master enable flag (IME) 0 0 INT0 mode register (IM0) 0 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode register (PMGA, PMGB) 0 0 Pull-up resistor specification register (POGA) 0 0 Used as inputs Used as inputs Digital I/O port States of pins P00 - P03, P10, P12, P20 - P23, P30 - P33, P60 - P63 P50 - P53 • • High level when pull-up resistor is built in High impedance when open drain is used in the internal circuit • • High level when pull-up resistor is built in High impedance when open drain is used in the internal circuit Note Data in the data memory whose addresses are 38H to 3DH is not defined when the standby mode is released by the RESET input signal. 24 µPD75402A(A) 9. INSTRUCTION SET (1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction refer to "RA75X Assembler Package User's Manual, Language" (EEU-1363) for details. When two or more elements are described in the description method field, select one of them. Upper-case letters, a number sign (#), and at mark (@), an exclamation mark (!), and a dollar sign ($) are keywords, so they can be used without alteration. Specify an appropriate numeric value or label for immediate data. The symbols of registers and flags can be used as labels instead of mem, fmem, and bit (refer to the "µPD75402A User's Manual" (IEU-644) for details). Some labels, however, cannot be specified in fmem. Representation format Description method reg reg1 X, A, H, L X, H, L rp XA, HL n4 4-bit immediate data or label n8 8-bit immediate data or label mem bit 8-bit immediate data or label Note 2-bit immediate data or label fmem FB0H - FBFH/FF0H - FFFH immediate data or label addr caddr faddr 11-bit immediate data or label 11-bit immediate data or label 11-bit immediate data or label PORTn IE××× PORT0 - PORT3, PORT5, PORT6 IEBT, IECSI, IE0, IE2 Note Only an even address can be written in mem when 8-bit data is processed. (2) Legend A : A register, 4-bit accumulator H : H register L : L register X : X register XA : Register pair (XA), 8-bit accumulator HL : Register pair (HL) PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word PORTn: Port n (n = 0 to 3, 5, 6) IME : Interrupt master enable flag IE××× : Interrupt enable flag PCC : Processor clock control register · : Address/bit delimiter (××) : Contents addressed by ×× ××H : Hexadecimal data 25 µPD75402A(A) (3) Explanation of the symbols in the addressing area field *1 MB = 0 *2 MB = 0 (00H - 3FH) MB = 15 (80H - FFH) *3 MB = 15, fmem = FB0H - FBFH or FF0H - FFFH *4 addr = 000H - 77FH *5 addr = (Current PC) – 15 to (Current PC) – 1 or (Current PC) + 16 to (Current PC) + 2 *6 caddr = 000H - 77FH *7 faddr = 000H - 77FH Data memory addressing Program memory addressing Remarks 1. MB indicates an accessible memory bank. 2. *4 to *7 indicate each addressable area. (4) Explanation of the machine cycle field S indicates the number of machine cycles required for a skip instruction to perform skipping. The following shows the values of S. • When the next instruction is not skipped, S is 0. • When the next instruction is skipped, S is 1. A machine cycle is equal to one cycle (= tCY) of CPU clock Φ. A PCC setting determines the machine cycle. It can be set to one of three different periods. 26 µPD75402A(A) Instruction group Transfer instruction Number of bytes Machine cycle A, #n4 1 1 A ← n4 String A XA, #n8 2 2 XA ← n8 String A HL, #n8 2 2 HL ← n8 String B A, @HL 1 1 A ← (HL) *1 @HL, A 1 1 (HL) ← A *1 A, mem 2 2 A ← (mem) *2 XA, mem 2 2 XA ← (mem) *2 mem, A 2 2 (mem) ← A *2 mem, XA 2 2 (mem) ← XA *2 A, @HL 1 1 A ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *2 XA, mem 2 2 XA ↔ (mem) *2 A, reg1 1 1 A ↔ reg1 MOVT XA, @PCXA 1 3 XA ← (PC10-8 + XA)ROM ADDS A, #n4 1 1+S A ← A + n4 A, @HL 1 1+S A ← A + (HL) *1 ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1 AND A, @HL 1 1 A←A OR A, @HL 1 1 Mnemonic MOV XCH Arithmetic/ logical instruction Operand Operation Addressing area Skip condition carry carry XOR A, @HL 1 1 ∧ (HL) A ← A ∨ (HL) A ← A ∨ (HL) Accumulator manipulation instruction RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A Increment/ decrement instruction INCS reg 1 1+S reg ← reg + 1 mem 2 2+S (mem) ← (mem) + 1 DECS reg 1 1+S reg ← reg – 1 reg = FH Comparison instruction SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4 A, @HL 1 1+S Skip if A = (HL) Carry flag manipulation instruction SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Skip if CY = 1 *1 *1 *1 reg = 0 *2 *1 (mem) = 0 A = (HL) CY = 1 CY ← CY 27 µPD75402A(A) Instruction group Memory bit manipulation instruction Number of bytes Machine cycle mem.bit 2 2 (mem.bit) ← 1 *2 fmem.bit 2 2 (fmem.bit) ← 1 *3 mem.bit 2 2 (mem.bit) ← 0 *2 fmem.bit 2 2 (fmem.bit) ← 0 *3 mem.bit 2 2+S Skip if (mem.bit) = 1 *2 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *3 (fmem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *2 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *3 (fmem.bit) = 0 SKTCLR fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *3 (fmem.bit) = 1 AND1 CY, fmem.bit 2 2 OR1 CY, fmem.bit 2 2 XOR1 CY, fmem.bit 2 2 BR addr – – PC10-0 ← addr (The assembler selects an appropriate instruction from the BRCB !caddr and BR $addr instructions.) *4 $addr 1 2 PC10-0 ← addr *5 BRCB !caddr 2 2 PC10-0 ← caddr *6 CALLF !faddr 2 2 (SP – 4)(SP – 1)(SP – 2) ← 0, PC10-0 (SP – 3) ← 0000 PC10-0 ← faddr, SP ← SP – 4 *7 RET 1 3 ×, PC 10-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4 RETS 1 3+S ×, PC 10-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4, then skip unconditionally RETI 1 3 ×, PC 10-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6 Mnemonic SET1 CLR1 SKT SKF Branch instruction Subroutine stack control instruction Interrupt control instruction Operand Operation ∧ (fmem.bit) CY ← CY ∨ (fmem.bit) CY ← CY ∨ (fmem.bit) CY ← CY PUSH rp 1 1 (SP – 1)(SP – 2) ← rp, SP ← SP – 2 POP rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2 2 2 IME (IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME (IPS.3) ← 0 IE××× 2 2 IE××× ← 0 EI IE××× DI Input/ output instruction IN A, PORTn 2 2 A ← PORTn (n = 0 - 3, 5, 6) OUT PORTn, A 2 2 PORT n ← A (n = 2, 3, 5, 6) CPU control instruction HALT 2 2 Set HALT mode (PCC.2 ← 1) STOP 2 2 Set STOP mode (PCC.3 ← 1) NOP 1 1 No operation 28 Addressing area Skip condition *3 *3 *3 Unconditionally µPD75402A(A) 10. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Ta = 25 ˚C) Parameter Symbol Conditions Rated value Unit –0.3 to +7.0 V Supply voltage VDD Input voltage VI1 Ports other than port 5 –0.3 to V DD + 0.3 V VI2 Port 5 –0.3 to V DD + 0.3 V –0.3 to +11.0 V –0.3 to V DD + 0.3 V Each pin –15 mA Total of all output pins –30 mA Peak value 30 mA rms 15 mA Peak value 20 mA rms 10 mA 100 mA 60 mA 100 mA 60 mA Built-in pull-up resistor Open drain Output voltage VO High-level output current IOH Low-level output current IOL Note One pin of port 0, 3, 5, or 6 One pin of port 2 Total of all pins of ports 0, 3, and 5 (excl. P33) Peak value Total of all pins of ports 2, 6, and P33 Peak value rms rms Operating temperature Topt –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Note Calculate rms with [rms] = [peak value] × √duty. Caution Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values. 29 µPD75402A(A) CHARACTERISTICS OF THE OSCILLATION CIRCUIT (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V) Recommended constant Resonator Ceramic resonator X1 Parameter X2 C1 C2 Oscillator frequency (fXX) Note 1 VDD = oscillation voltage range Oscillation settling time After VDD reaches MIN. of the oscillation voltage range Note 2 Crystal X1 Oscillator frequency (fXX) Note 1 X2 C1 Conditions C2 Oscillation settling time Min. Typ. 2.0 2.0 4.19 VDD = 4.5 to 6.0 V Max. Unit 5.0 Note 3 MHz 4 ms 5.0 Note 3 MHz 10 ms Note 2 External clock X1 X2 µ PD74HCU04 X1 input frequency (fX) Note 1 2.0 5.0 Note 3 MHz X1 input high/low level width (tXH, tXL) 100 250 ns Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released. 3. When 4.19 MHz < fX ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When PCC = 0011, one machine cycle falls short of 0.95 µ s, the minimum value for the standard. ★ Caution When the clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS . It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. CAPACITANCE (Ta = 25 ˚C, V Parameter Symbol Input capacitance CIN Output capacitance COUT I/O capacitance CIO 30 DD = 0 V) Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. Unit 15 pF 15 pF 15 pF µPD75402A(A) DC CHARACTERISTICS (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V) Parameter High-level input voltage Conditions Symbol Min. Typ. Max. Unit VIH1 Ports 2, 3, and 6 0.7V DD VDD V VIH2 Ports 0 and 1, and RESET 0.8V DD VDD V VIH3 Port 5 Built-in pull-up resistor 0.7V DD VDD V Open drain 0.7V DD 10 V VDD – 0.5 VDD V VIH4 X1 and X2 VIL1 Ports 2, 3, 5, and 6 0 0.3VDD V VIL2 Ports 0 and 1, and RESET 0 0.2VDD V VIL3 X1 and X2 0 0.4 V High-level output voltage VOH Ports 0, 2, 3, and 6 Low-level output voltage VOL Low-level input voltage High-level input leakage current ILIH1 VDD = 4.5 to 6.0 V, IOH = –1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V Ports 3, 5, and 6 VDD = 4.5 to 6.0 V, IOL = 15 mA Ports 0, 2, 3, 5, and 6 SB0 (Open drain) VIN = VDD ILIH2 2.0 V V DD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V Pull-up resistor : 1 kΩ or more V DD = 4.5 to 6.0 V 0.2VDD V Other than X1 and X2 3 µA X1 and X2 20 µA 0.6 ILIH3 VIN = 10 V Port 5 (open drain) 20 µA Low-level input leakage current ILIL1 VIN = 0 V Other than X1 and X2 –3 µA X1 and X2 – 20 µA High-level output leakage current ILOH1 VOUT = VDD Other than port 5 3 µA ILOH2 VOUT = 10 V Port 5 (open drain) 20 µA Low-level output leakage current ILOL VOUT = 0 V –3 µA Built-in pull-up resistor RL1 Ports 0, 1, 2, 3, and 6 (excl. P00 and P10) VIN = 0 V 80 kΩ 300 kΩ 70 kΩ 60 kΩ ILIL2 RL2 Power supply current Note 1 IDD1 IDD2 IDD3 Port 5 VOUT = VDD – 2.0 V 4.19 MHz crystal resonance C1 = C2 = 22 pF STOP mode VDD = 5.0 V ±10 % 15 VDD = 3.0 V ±10 % 30 VDD = 5.0 V ±10 % 15 VDD = 3.0 V ±10 % 10 40 40 VDD = 5.0 V ±10 % Note 2 2.5 8 mA VDD = 3.0 V ±10 % Note 3 HALT mode 0.5 1.5 mA VDD = 5.0 V ±10 % 500 1500 µA VDD = 3.0 V ±10 % 150 450 µA VDD = 5.0 V ±10 % 0.5 20 µA VDD = 3.0 V ±10 % 0.1 10 µA 0.1 5 µA Ta = 25 ˚C Notes 1. This current excludes the current which flows through the built-in pull-up resistors. 2. Value when the processor clock control resistor (PCC) is set to 0011 and the µPD75402A(A) is operated in the high-speed mode 3. Value when the PCC is set to 0000 and the µ PD75402A(A) is operated in the low-speed mode 31 µPD75402A(A) AC CHARACTERISTICS (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V, VSS = 0 V) Parameter Symbol CPU clock cycle time Note 1 (minimum instruction execution time = one machine cycle) tCY Interrupt input high/low level width RESET low-level width Conditions Max. Unit 0.95 32 µs 3.8 32 µs Min. VDD = 4.5 to 6.0 V tINTH, tINTL INT0 INT2 tRSL Typ. Note 2 µs 10 µs 10 µs tCY vs. VDD 40 (minimum instruction execution time) 32 depends on the connected resonator frequency and the setting of the proc- 7 6 essor clock control register (PCC). 5 The figure on the right side shows 4 the cycle time tCY characteristics for the supply voltage VDD. 2. This value is 2tCY or 128/fXX according to the setting of the interrupt mode register (IM0). Cycle time tCY [ µs] Notes 1. The cycle time of the CPU clock (Φ) Guaranteed operating range 3 2 1 0.5 0 1 2 3 4 5 Supply voltage VDD [V] 32 6 µPD75402A(A) Serial transfer operation Three-wire serial I/O mode (SCK ··· Internal clock output): Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V Min. Typ. Max. Unit 1600 ns 3800 ns tKCY1/2 – 50 ns SCK high/low level width tKL1 tKH1 tKCY1/2 – 150 ns SI setup time (referred to SCK↑) tSIK1 150 ns SI hold time (referred to SCK↑) tKSI1 400 ns Delay from SCK↓ to SO output tKSO1 RL = 1 kΩ, CL = 100 pF Note VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. Three-wire serial I/O mode (SCK ··· External clock input): Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 4.5 to 6.0 V Min. Typ. Max. Unit 800 ns 3200 ns 400 ns SCK high/low level width tKL2 tKH2 1600 ns SI setup time (referred to SCK↑) tSIK2 100 ns SI hold time (referred to SCK↑) tKSI2 400 ns Delay from SCK↓ to SO output tKSO2 VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF Note VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. 33 µPD75402A(A) SBI mode (SCK ··· Internal clock output (master)): Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V Min. Typ. Max. Unit 1600 ns 3800 ns tKCY3/2 – 50 ns SCK high/low level width tKL3 tKH3 t KCY3/2 – 150 ns SB0 setup time (referred to SCK↑) tSIK3 150 ns SB0 hold time (referred to SCK↑) tKSI3 tKCY3/2 ns Delay from SCK↓ to SB0 output tKSO3 Delay from SCK↑ to SB0↓ tKSB tKCY3 ns Delay from SB0↓ to SCK tSBK tKCY3 ns SB0 low-level width tSBL tKCY3 ns SB0 high-level width tSBH tKCY3 ns VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns SBI mode (SCK ··· External clock input (slave)): Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V Min. Typ. Max. Unit 800 ns 3200 ns 400 ns SCK high/low level width tKL4 tKH4 1600 ns SB0 setup time (referred to SCK↑) tSIK4 100 ns SB0 hold time (referred to SCK↑) tKSI4 tKCY4/2 ns Delay from SCK↓ to SB0 output tKSO4 Delay from SCK↑ to SB0↓ tKSB tKCY4 ns Delay from SB0↓ to SCK↓ tSBK tKCY4 ns SB0 low-level width tSBL tKCY4 ns SB0 high-level width tSBH tKCY4 ns VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF Note VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns Note RL and CL are the resistance and capacitance of the SO output line load respectively. 34 µPD75402A(A) AC Timing Measurement Points (Excluding X1 Input) 0.8VDD 0.8VDD Measurement point 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VDD – 0.5 V X1 input 0.4 V Serial Transfer Timing Three-wire serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 Input data SI tKSO1 SO Output data 35 µPD75402A(A) Serial Transfer Timing Bus release signal transfer: tKCY3, 4 tKL3, 4 tKH3, 4 SCK tSIK3, 4 tKSB tSBL tSBH tKSI3, 4 tSBK SB0 tKSO3, 4 Command signal transfer: tKCY3, 4 tKL3, 4 tKH3, 4 SCK tSIK3, 4 tKSB tKSI3, 4 tSBK SB0 tKSO3, 4 Interrupt Input Timing tINTL INT0, INT2 RESET Input Timing tRSL RESET 36 tINTH µPD75402A(A) DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = –40 to +85 ˚C) Parameter Symbol Data hold supply voltage VDDDR Data hold supply current IDDDR RESET setup time tSRS Oscillation settling time tOS Conditions Min. Typ. 2.0 0.1 VDDDR = 2.0 V Max. Unit 6.0 V 10 µA µs 0 After VDD reaches the oscillation voltage range when the ceramic resonator is connected 4 ms After VDD reaches the oscillation voltage range when the crystal is connected 10 ms Data Hold Timing (STOP Mode Release by RESET) HALT mode STOP mode Operating mode Data hold mode VDD VDDDR tSRS STOP instruction execution RESET tOS 37 µPD75402A(A) 11. PACKAGE DIMENSIONS 28 PIN PLASTIC DIP (600 mil) 15 28 14 1 A K H G J I L F D N M C M B R NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 38.10 MAX. 1.500 MAX. B 2.54 MAX. 0.100 MAX. C 2.54 (T.P.) D 0.50±0.10 0.100 (T.P.) +0.004 0.020 –0.005 F 1.2 MIN. 0.047 MIN. G 3.6±0.3 0.142±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.72 MAX. 0.226 MAX. K L 15.24 (T.P.) 13.2 0.600 (T.P.) 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.25 0.01 R 0‘ 15 0‘ 15 P28C-100-600A1-1 38 µPD75402A(A) 28PIN PLASTIC SHRINK DIP (400 mil) 28 15 1 14 A K L I J H F D G C N M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel. M R B ITEM MILLIMETERS INCHES A B 28.46 MAX. 2.67 MAX. 1.121 MAX. 0.106 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G H 3.2±0.3 0.51 MIN. 0.126±0.012 0.020 MIN. I J 4.31 MAX. 5.08 MAX. 0.170 MAX. 0.200 MAX. K 10.16 (T.P.) 0.400 (T.P.) L 8.6 0.339 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15 ° 0~15° P28C-70-400A-1 39 µPD75402A(A) 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F G J H I M K M P N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 40 ITEM MILLIMETERS INCHES A 13.6±0.4 0.535 +0.017 –0.016 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.6±0.4 0.535 +0.017 –0.016 F 1.0 0.039 G 1.0 0.039 H 0.35±0.10 0.014 +0.004 –0.005 0.006 I 0.15 J 0.8 (T.P.) 0.031 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 2.7 0.1±0.1 5°±5° 3.0 MAX. 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3 µPD75402A(A) PACKAGE DIMENSIONS OF THE 44-PIN CERAMIC QFP FOR ES (REF. DWG.) (UNIT: MM) 11.43 8.0 44 34 1 11 11.43 8.0 33 23 12 22 0.15 0.32 2.25 0.8 (Bottom) Cautions 1. Find the location of pin 1 by checking the location of pin 17, which is connected to the metal cap. 2. The metal cap is connected to pin 17. The electrical level of the metal cap is VSS (GND). 3. The lead length has not been specified because leads are cut without any detailed specifications. 41 µPD75402A(A) 12. RECOMMENDED SOLDERING CONDITIONS The following conditions shall be met when soldering the µPD75402A(A). For details of the recommended soldering conditions, refer to our document "SMD Surface Mount Technology Manual" (IEI-1207). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Table 12-1 Soldering Conditions for Surface-Mount Devices µPD75402AGB(A)-×××-3B4: 44-pin plastic QFP (10 × 10 mm) Soldering process Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 230 ˚C Reflow time: 30 seconds or less (210 ˚C or more) Number of reflow processes: 1 IR30-00-1 VPS Peak package’s surface temperature: 215 ˚C Reflow time: 40 seconds or less (200 ˚C or more) Number of reflow processes: 1 VP15-00-1 Wave soldering Solder temperature: 260 ˚C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature: 120 ˚C max. (measured on the package surface) WS60-00-1 Partial heating method Terminal temperature: 300 ˚C or less Flow time: 3 seconds or less (for each side of device) — Caution Do not apply more than a single process at once, except for “Partial heating method.” Table 12-2 Soldering Conditions for Insertion-Mount Devices µPD75402AC(A)-×××: 28-pin plastic DIP (600 mil) µPD75402ACT(A)-×××: 28-pin plastic shrink DIP (400 mil) Soldering process Soldering conditions Wave soldering (Only for leads) Solder temperature: 260 ˚C or less Flow time: 10 seconds or less Partial heating method Terminal temperature: 260 ˚C or less Flow time: 10 seconds or less Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not come in contact with the main body of the package. Notice Other versions of the products are available. For these versions, the recommended reflow soldering conditions have been mitigated as follows: Higher peak temperature (235 °C), two-stage, and longer exposure limit. Contact an NEC representative for details. 42 µPD75402A(A) APPENDIX A DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75P402 Product Item ROM I/O ports Input I/O N-ch I/O VPP, PROM programming pin Electrical characteristics 22 6 12 µPD75402A(A) µPD75P402 Masked ROM One-time PROM 16 (Pull-up resistors can be connected by software.) 4 (Pull-up resistors can be connected by mask option.) 4 (No pull-up resistors can be connected.) Not provided Provided Operating supply voltage 2.7 to 6.0 V 5 V ±10 % Operating tempera- -40 to +85 ˚C -10 to +70 ˚C Special Standard ture Quality grade 43 µPD75402A(A) APPENDIX B DEVELOPMENT TOOLS Hardware The following development tools are provided for developing systems including the µPD75402A(A) IE-75000-RNote 1 IE-75001-R In-circuit emulator for the 75X series IE-75000-R-EMNote 2 Emulation board for the IE-75000-R and IE-75001-R EP-75402C-R Emulation probe for the µPD75402AC(A) and µPD75402ACT(A) EP-75402GB-R Emulation probe for the µPD75402AGB(A). A 44-pin conversion socket, the EV-9200G-44, is attached to the probe. EV-9200G-44 PG-1500 PA-75P402CT PROM programmer PROM programmer adapter for the µPD75P402C and µPD75P402CT. Connected to the Software PG-1500. PA-75P402GB PROM programmer adapter for the µPD75P402GB. Connected to the PG-1500. IE control program Host machine • PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3) • IBM PC/AT TM (PC DOSTM Ver. 3.1) PG-1500 controller RA75X relocatable assembler Notes 1. Maintenance service only 2. Not contained in the IE-75001-R 3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A. Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties. 44 µPD75402A(A) APPENDIX C ★ RELATED DOCUMENTS Documents related to the device Document name Document No. User’s manual IEU-644 Application note IEA-638 75X series selection guide IF-1027 Documents related to development tools Software Hardware Document name Document No. IE-75000-R/IE-75001-R User’s Manual EEU-1416 IE-75000-R-EM User’s Manual EEU-1294 EP-75402C-R User’s Manual EEU-701 EP-75402GB-R User’s Manual EEU-702 PG-1500 User’s Manual EEU-1335 RA75X Assembler Package User’s Manual PG-1500 Controller User’s Manual Operation EEU-1346 Language EEU-1363 EEU-1291 Other related documents Document name Document No. Package Manual IEI-1213 SMD Surface Mount Technology Manual IEI-1207 Quality Grades on NEC Semiconductor Devices IEI-1209 NEC Semiconductor Device Reliability/Quality Control System IEI-1203 Electrostatic Discharge (ESD) Test IEI-1201 Guide to Quality Assurance for Semiconductor Devices MEI-1202 Caution The above documents may be revised without notice. Use the latest versions when you design an application system. 45 µPD75402A(A) Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. 2 CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. 3 Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. 46 µPD75402A(A) [MEMO] 47 µPD75402A(A) [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use “Standard” quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92. 6 MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.