DATA SHEET MOS INTEGRATED CIRCUIT µPD75512(A) 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75512(A) is a 4-bit single-chip microcomputer which employs 75X series architecture, and its performance is comparable to that of an 8-bit microcomputer. In addition to its high-speed processing capabilities, the µPD75512(A) is also capable of processing data in units of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the µPD75512(A) provides the highest performance in its class. Detailed functions are described in the following user‘s manual. Be sure to read it for designing. µPD75516 User‘s Maual: IEM-5049 FEATURES • Higher reliability than µPD75512 • Adequate I/O lines: 64 (can be provided with pull-up/pull-down resistors: 47) • Built-in 8-bit serial interface: 2-ch NEC standard serial bus interface (SBI) internally provided • Built-in 8-bit A/D converter: 8-ch • Variable instruction execution time function which is convenient for high-speed operation and power saving · 0.95 µs/1.95 µs/15.3 µs (at 4.19 MHz operation), · 122 µs (at 32.768 kHz operation) • Program memory (ROM) size: 12,160 × 8 bits • Data memory (RAM) size: 512 × 4 bits • High-performance timer function: 4-ch · 8-bit timer/event counter · Watch timer · 8-bit basic interval timer · Timer/pulse generator: Capable of outputting 14-bit PWM • Clock operation for reduced power consumption possible (5 µA TYP. at 3 V operation) • PROM version (µPD75P516) available APPLICATIONS Switable for automotive and transportation equipments, etc. The information in this document is subject to change without notice. Document No. IC-2815A (O. D. No. IC-8265A) Date Published January 1994 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1991 µPD75512(A) ORDERING INFORMATION Part Number Package Quality Grade µPD75512GF(A)-xxx-3B9 80-pin plastic QFP Special (14 × 20mm) Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Difference between µPD75512(A) and µPD75512 Product Item Quality Grade µPD75512(A) µPD75512 Special Standard Absolute Maximum Ratings Differ in high-level and low-level output current DC Characteristics Differ in low-level output voltage A/D Converter Characteristics Differ in ambient temperature range and absolute accuracy Electrical Specifications 2 µPD75512(A) µPD75512(A) FUNCTIONS ★ Item Internal Memory Size Function ROM 12160 × 8 bits RAM 512 × 4 bits Genearl-Purpose Register (4 bits × 8 or 8 bits × 4) × 4 banks Instruction Cycle • 0.95 µs/1.91 µ s/15.3 µ s (Main system clock: at 4.19 MHz) • 122 µs (Subsystem clock: at 32.768 kHz) Input/ Output Ports Total 64 lines CMOS Inputs 16 lines (also serve as INT, SIO, PPO, analog input; can be pulled up by software: 7 lines) CMOS Input/Outputs 28 lines • Can be pulled up by software: 16 lines • Can be pulled down by mask option: 4 lines N-ch Open-Drain Input/Outputs 20 lines (10 V withstand voltage; pins that can be pulled up by mask option: 20) A/D Converter 8-bit resolution × 8 channels (successive approxmation type) • Operation voltage: VDD = 3.5 to 6.0 V Timer/Counter 4 channels • • • • Serial Interface 2 channels • NEC standard serial bus interface (SBI)/3-line SIO: 1 channel • Normal clock synchronized serial interface (3-line SIO): 1 channel Vector Interrupt External: 3, Internal: 4 Test Input External: 1, Internal: 1 Instruction Set • Bit data set/reset/test/boolean operation instruction • 4-bit data transfer/operation/increment/decrement /compare instructions • 8-bit data transfer/operation/increment/decrement /compare instructions System Clock Generator • Ceramic/crystal oscillator for main system clock: 4.19 MHz • Crystal oscillator for subsystem clock: 32.768 kHz Operation Voltage VDD = 2.7 V to 6.0 V Package 80-pin plastic QFP (14 × 20mm) Timer/event counter Basic interval timer Timer/pulse generator (capable of outputting 14-bit PWM) Watch timer 3 µPD75512(A) CONTENTS 4 1. PIN CONFIGURATION ..................................................................................................................... 6 2. INTERNAL BLOCK DIAGRAM ......................................................................................................... 7 3. PIN FUNCTIONS .............................................................................................................................. 8 3.1 PORT PINS ............................................................................................................................................. 8 3.2 NON-PORT PINS ................................................................................................................................... 10 3.3 PIN INPUT/OUTPUT CIRCUITS ............................................................................................................ 11 3.4 RECOMMENDED CONDITIONS FOR UNUSED PINS .......................................................................... 14 3.5 MASK OPTION SELECTION ................................................................................................................. 15 4. MEMORY CONFIGURATION .......................................................................................................... 16 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 19 5.1 PORT ...................................................................................................................................................... 19 5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................. 20 5.3 CLOCK OUTPUT CIRCUIT ..................................................................................................................... 21 5.4 BASIC INTERVAL TIMER ...................................................................................................................... 22 5.5 WATCH TIMER ...................................................................................................................................... 23 5.6 TIMER/EVENT COUNTER ..................................................................................................................... 23 5.7 TIMER/PULSE GENERATOR ................................................................................................................. 25 5.8 SERIAL INTERFACE ............................................................................................................................... 26 5.9 A/D CONVERTER ................................................................................................................................... 30 5.10 BIT SEQUENTIAL BUFFER ................................................................................................................... 31 6. INTERRUPT FUNCTIONS ................................................................................................................ 31 7. STANDBY FUNCTIONS ................................................................................................................... 33 8. RESET FUNCTIONS ......................................................................................................................... 34 9. INSTRUCTION SET .......................................................................................................................... 36 10. ELECTRICAL SPECIFICATIONS ....................................................................................................... 44 11. PACKAGE DRAWINGS .................................................................................................................... 57 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 58 µPD75512(A) APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD755XX(A) SERIES PRODUCTS ............. 59 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 60 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 61 5 µPD75512(A) 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 AV REF 2 63 P141 V DD 3 62 P142 V DD 4 61 P143 P113 5 60 RESET P112 6 59 X2 P111 7 58 X1 P110 8 57 IC 56 XT2 P103 9 P102 10 P101 11 P100 12 P93 13 P92 14 µ PD75512GF(A) – ×××–3B9 AN0 * P140 55 XT1 54 V SS 53 P00/INT4 52 P01/SCK0 51 P02/SO0/SB0 50 P03/SI0/SB1 49 P10/INT0 22 43 P22/PCL KR5/P71 23 42 P23/BUZ KR4/P70 41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 *: Power must be supplied to both VDD pins. P31 P21 KR6/P72 P32 44 P33 21 P41 P20/PTO0 KR7/P73 P40 45 P42 20 P43 P13/TI0 PPO/P80 V SS 46 P50 19 P51 P12/INT2 SCK1/P81 P52 47 P53 P11/INT1 18 KR0/P60 48 SO1/P82 KR1/P61 SI1/P83 17 KR2/P62 15 16 KR3/P63 P91 P90 IC: Internally Connected (Connect directly to VSS) 6 P133 P132 P131 P130 P123 P122 P120 P121 AV SS AN7/P153 AN6/P152 AN5/P151 AN4/P150 AN2 AN3 PIN CONFIGURATION AN1 1. P30 2. PORT 0 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 PORT 4 4 P40-P43* PORT 5 4 P50-P53* PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 PORT 9 4 P90-P93 PORT10 4 P100-P103 PORT11 4 P110-P113 PORT12 4 P120-P123* PORT13 4 P130-P133* PORT14 4 P140-P143* PORT15 4 P150-P153 INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 PROGRAM CY ALU SP (8) COUNTER (14) INTT0 BANK BUZ/P23 WATCH TIMER INTW GENERAL REG. INTERNAL BLOCK DIAGRAM BASIC INTERVAL TIMER ROM PPO/P80 SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 TIMER/PULSE GENERATOR PROGRAM INTTPG MEMORY AND 12160 × 8 BITS CONTROL DECODE RAM DATA MEMORY SERIAL INTERFACE0 512 x 4 BITS INTCSI SI1/P83 SO1/P82 SCK1/P81 SERIAL INTERFACE1 INT0/P10 f X /2 N INT1/P11 INT2/P12 CLOCK OUTPUT CONTROL PCL/P22 CLOCK DIVIDER SUB XT1 MAIN XT2 X1 X2 STAND BY CONTROL CPU CLOCK Φ RESET BIT SEQ. BUFFER (16) V DD AN0-AN3 AN4/P150-AN7/P15 AV REF AV SS A/D CONVERTER *: PORTs 4, 5, and 12 to 14 are 10 V middle voltage, N-ch open-drain input/output ports. V SS 7 µPD75512(A) INT4/P00 KR0/P60 8 –KR7/P73 INTERRUPT CONTROL CLOCK GENERATOR µPD75512(A) 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name Input/ Output P00 Shared Pin INT4 P01 SCK0 Input Function 4-bit input port (PORT0). For P01 to P03, built-in pull-up resistors can be specified in 3-bit units by software. 8-bit I/O When Reset Input/ Output Circuit Type* B F -A x Input P02 SO0/SB0 F -B P03 SI0/SB1 M -C P10 INT0 P11 INT1 Input P12 INT2 P13 TI0 P20 PTO0 P21 Input/ output — P22 PCL P23 BUZ P30 — P31 Input/ output — P32 — P33 — P40 to P43 With noise elimination function Input/ output — 4-bit input port (PORT1). Built-in pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT2). Built-in pull-up resistors can be specified by software in 4-bit units. Programmable 4-bit input/output port (PORT3). Input/output can be specified in bit units. Built-in pull-up resistors can be specified by software in 4-bit unit. x Input B -C x Input E-B x Input E-C N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. High level (when pull-up resistor is provided) or high impedance M High level (when pull-up resistor is provided) or high impedance M O P50 to P53 Input/ output P60 P61 — KR0 Input/ output KR1 P62 KR2 P63 KR3 N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. Programmable 4-bit input/ output port (PORT6). Input/output can be specified in bit units. Built-in pull-up resistors can be specified by software in 4-bit units. *: The number enclosed with a circle indicates Schmitt trigger input. 8 O Input F -C µPD75512(A) 3.1 PORT PINS (2/2) Pin Name Input/ Output P70 P71 Shared Pin Function 8-bit I/O When Reset O Input Input/ Output Circuit Type* KR4 Input/ output KR5 P72 KR6 P73 KR7 P80 PPO P81 4-bit input/output port (PORT7). Built-in pull-up resistor can be specified in 4-bit units by software. E SCK1 Input F -A F 4-bit input port (PORT8). x Input P82 SO1 E P83 SI1 B 4-bit input/output port (PORT9). Built-in pull-up resistors can be specified in bit units by mask option. P90 to P93 Input/ output — P100 to P103 Input/ output — 4-bit input/output port (PORT10). P110 to P113 Input/ output — 4-bit input/output port (PORT11). x Low level (when pulldown resistor is provided) or high impedance V Input E Input E x P120 to P123 P130 to P133 Input/ output Input/ output P140 to P143 Input/ output P150 to P153 Input — — — AN4 to AN7 N-ch open-drain 4-bit input/output port (PORT12). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. N-ch open-drain 4-bit input/output port (PORT13). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. N-ch open-drain 4-bit input/output port (PORT14). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. 4-bit input port (PORT15). High level (when pull-up resistor is provided) or high impedance M x High level (when pull-up resistor is provided) or high impedance M x High level (when pull-up resistor is provided) or high impedance M x x Input Y-A *: The number enclosed with a circle indicates Schmitt trigger input. 9 µPD75512(A) 3.2 NON-PORT PINS Pin Name Input/ Output Shared Pin Function When Reset TI0 Input P13 The external event pulse input for the timer/event counter. PTO0 Output P20 PCL Output BUZ — B -C Timer/event counter output Input E-B P22 Clock output Input E-B Output P23 Fixed frequency output (for buzzer output or system clock trimming) Input E-B SCK0 Input/ output P01 Serial clock input/output Input F -A SO0/SB0 Input/ output P02 Serial data output Serial bus input/output Input F -B SI0/SB1 Input/ output P03 Serial data input Serial bus input/output Input M -C INT4 Input P00 Edge detection vector interrupt input (both rising edge and falling edge detection) — B P10 Edge detection vector interrupt input (detection edge selectable) — B -C — B -C INT0 Input INT1 P11 Synchronized with clock Asynchronous INT2 Input P12 KR0-KR3 Input P60-P63 Parallel falling edge detection testable input Input F -C KR4-KR7 Input P70-P73 Parallel falling edge detection testable input Input F -A SCK1 Input/ output P81 Serial clock input/output Input F SO1 Output P82 Serial data output Input E SI1 Input P83 Serial data input Input B AN0-AN3 Edge detection testable input (rising edge detection) Asynchronous — Input AN4-AN7 Y A/D converter analog input — P150-P153 Y-A AVREF Input — A/C converter reference voltage input — Z AVSS — — A/D converter reference ground — — — Pins for connecting the crystal ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. — — — — — B Input E X1, X2 Input XT1 Input — XT2 — — Pins for connecting the crystal oscillator to the subsystem clock generator. When the external clock is used, inputs the external clock to pin XT1. In this case, pin XT2 must be left open. RESET Input System reset input PPO Output P80 IC — — Internally Connected. Connect directly to VSS. — — VDD — — Positive power supply — — VSS — — GND — — Timer/pulse generator pulse output *: The number enclosed with a circle indicates Schmidt trigger input. 10 Input/ Output Circuit Type* µPD75512(A) 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µ PD75512(A). TYPE D TYPE A VDD VDD data P–ch P–ch OUT IN output disable N–ch Input buffer of CMOS standard N–ch Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off) TYPE E TYPE B data IN/OUT Type D output disable IN Type A Schmitt trigger input with hysteresis characteristics TYPE B–C This input/output circuit consists of D-type push-pull outputs and Type A input buffers. TYPE E–B VDD P.U.R. VDD P.U.R. enable P.U.R. P–ch P.U.R. enable P–ch data IN/OUT Type D output disable IN Type A P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics P.U.R. : Pull-Up Resistor Fig. 3-1 Pin Input/Output Circuits (1/3) 11 µPD75512(A) Type E-C Type F-B VDD VDD P.U.R. P.U.R. P.U.R. enable P–ch data P.U.R. enable output disable (P-ch) P–ch VDD P-ch IN/OUT Type D IN/OUT data output disable output disable (N-ch) output disable Type A N-ch Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Type F Type F-C VDD P.U.R. data IN/OUT Type D P.U.R. enable output disable P–ch data IN/OUT Type D Type B output disable Type B This input/output circuit consists of D-type push-pull outputs and Type B Schmitt trigger inputs. VDD Type F-A P.U.R. : Pull-Up Resistor Type M P.U.R. P.U.R. enable VDD P.U.R. (Mask Option) IN/OUT P–ch data IN/OUT data N-ch (can withstand up to +10 V) Type D output disable output disable Type B P.U.R. : Pull-Up Resistor Middle-voltage input buffer (can withstand up to +10 V) P.U.R. : Pull-Up Resistor Fig. 3-1 Pin Input/Output Circuits (2/3) 12 µPD75512(A) Type M-C Type Y-A IN instruction VDD P.U.R. P.U.R. enable P–ch IN/OUT V DD IN P–ch N–ch + V DD data N-ch Sampling C output disable – AVSS Reference voltage (from a voltage tap of series resistor string) AVSS input enable P.U.R. : Pull-Up Resistor Type Z Type V AV REF data IN/OUT Type D output disable Reference voltage Type A P.D.R (Mask Option) AVSS P.D.R. : Pull-Down Resistor Type Y V DD IN P–ch N–ch + V DD Sampling C – AVSS Reference voltage (from a voltage tap of series resistor string) AVSS Input enable Fig. 3-1 Pin Input/Output Circuits (3/3) 13 µPD75512(A) ★ 3.4 RECOMMENDED CONDITIONS FOR UNUSED PINS Table 3-1 Recommended Conditions for Unused Pins Pin P00/INT4 Recommended Conditions Connect to VSS P01/ SCK0 P02/SO0/SB0 Connect to VSS or VDD P03/SI1/SB1 P10/INT0-P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ Input state: Connect to VSS or VDD P30-P33 Output state: Open P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/PPO P81/ SCK1 Connect to VSS or VDD P82/SO1 P83/SI1 P90-P93 P100-P103 P110-P113 Input state: Connect to VSS or VDD P120-P123 Output state: Open P130-P133 P140-P143 P150/AN4-P153/AN7 Connect to VSS AN0-AN3 XT1 Connect to VSS or VDD XT2 Open AVREF Connect to VSS AVSS IC 14 Connect directly to VSS µPD75512(A) 3.5 MASK OPTION SELECTION The following mask options are provided with the pins. (1) Pull-up/pull-down resistor selection Table 3-2 Pull-up/Pull-down Resistor Selection Pins P40-P43 P50-P53 Mask Option (1) With pull-up resistor (2) Without pull-up resistor (Can be specified in bit units) (Can be specified in bit units) P120-P123 P130-P133 P140-P143 P90-P93 (1) With pull-down resistor (2) Without pull-down resistor (Can be specified in bit units) (2) (Can be specified in bit units) ★ Feedback resistor selection for the subsystem clock oscillation Table 3-3 Feedback Resistor Selection Pins XT1, XT2 Note: Mask Option (1) With feedback resistor (When the subsystem clock is used) (2) Without feedback resistor (When the subsystem clock is not used) The operation is not affected if the feedback resistor is selected when the subsystem clock is not used. However, the supply current IDD is increased. 15 µPD75512(A) ★ 4. MEMORY CONFIGURATION • Program memory (ROM) ... 12160 × 8 bits (0000H-2F7FH) • 0000H, 0001H : Vector table to which address from which program is started is written after reset • 0002H-000DH : Vector table to which address from which program is started is written after interrupt • 0020H-007FH : Table area referenced by GETI instruction • Data memory • Data area .... 512 × 4 bits (000H–1FFH) • Peripheral hardware area .... 128 × 4 bits (F80H–FFFH) 16 µPD75512(A) Address 7 0000H 6 MBE RBE 0 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE INT0 start address (upper 6 bits) CALL !addr instruction subroutine entry address INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE RBE INTCSIO0 start address (upper 6 bits) INTCSIO0 start address (lower 8 bits) 000AH MBE RBE CALLF !faddr instruction entry address INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTTPG start address (upper 6 bits) BRCB !caddr instruction branch address BR !addr instruction branch address BR $addr instruction relational branch address (–15 to –1, +2 to +16) INTTPG start address (lower 8 bits) 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 007FH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2F7FH Remarks: In addition to the above, branching to an address, for which only the lower 8 bits of the PC are modified, is possible by the BR PCDE and BR PCXA instructions. Fig. 4-1 Program Memory Map 17 µPD75512(A) Data memory General 000H purpose register 01FH area 008H Stack area Memory bank (32 × 4) 256× 4 0 256× 4 1 Data area Static RAM (512 × 4) 0FFH 100H 1FFH Unmapped F80H Peripheral hardware area 128× 4 FFFH Fig. 4-2 Data Memory Map 18 15 µPD75512(A) 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 ★ PORT I/O ports are classified into following kinds: • CMOS input (PORTS 0, 1, 8, 15) : 16 • CMOS input/output (PORTS 2, 3, 6, 7, 9, 10, 11) : 28 • N-ch open-drain input/output (PORTS 4, 5, 12, 13, 14) : 20 Total : 64 Table 5-1 Port Functions Port (Pin Name) Function PORT0 4-bit input Operation/Feature Can be read or tested regardless of the operation mode of the shared pin. Can be specified for I/O in 4-bit units 4-bit I/O Can be specified for I/O in 1/4-bit units. PORT3 PORT4 PORT5 Also serves as the INT4, SCK0 , SO0/SB0, and SI0/SB1 pins Also serves as INT0 to 2, and TIO pins PORT1 PORT2 Remarks 4-bit I/O (N-ch open-drain, can sustain with 10V) Can be specifiedfor I/O in 4-bit units Can be specified for I/O in 1/4-bit units PORT6 4-bit I/O Can be specified I/O in 4-bit units PORT7 Ports 4 and 5 can be paired to I/O data in 8-bit units Ports 6 and 7 can be paired to I/O data in 8-bit units Also serves as PTO0, PCL and BUZ pins. — Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option Also serves as KR0-3. Also serves as KR4-7. PORT8 4-bit input Can be read or tested regardless of the operation mode of the shared pin. Also serves as PPO, SCK1 , SO1, and SI1 pins. PORT9 4-bit I/O Can be specified for I/O in 4-bit units. Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. 4-bit I/O Can be specified for I/O in 4-bit units. PORT10 — PORT11 PORT12 PORT13 PORT14 PORT15 4-bit I/O (N-ch open-drain, can sustain with 10V) Can be specified for I/O in 4-bit units. 4-bit Input Can be read or tested regardless of the operation mode of the shared pins Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. Also serves as AN4-7 pins. 19 µPD75512(A) 6.2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. • 0.95 µ s, 1.91 µ s, 15.3 µ s (main system clock: 4.19 MHz) • 122 µs (subsystem clock: 32.768 kHz) · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · Clock output circuit · A/D converter · INT0 noise rejecter circuit XT1 V DD XT2 Subsystem clock oscillator f XT Watch timer Timer/pulse generator X1 Main system f X clock oscillator WM.3 SCC Oscillator disable signal SCC3 1/8 to 1/4096 Frequency divider 1/2 1/16 SCC0 Internal bus Frequency divider Selector X2 Selector V DD 1/4 PCC PCC0 Φ · CPU · Clock output circuit · INT0 noise rejecter circuit PCC1 4 HALT F/F PCC2 S HALT* STOP* PCC3 R PCC2, PCC3 clear signal STOP F/F Q S Q Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit *: instruction execution. Remarks 1: f X = Main system clock frequency 2: f XT = Subsystem clock frequency 3: Φ = CPU clock 4: PCC: Processor clock control register 5: SCC: System clock control register 6: One clock cycle (t CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC characteristics in 10. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 20 µPD75512(A) 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. • Clock output (PCL): Φ, 524 kHz, 262 kHz, 65.5 kHz (operating at 4.19 MHz) From the clock generator Φ Output buffer fX/23 Selector fX/24 PCL/P22 fX/26 PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken. 21 µPD75512(A) 5.4 BASIC INTERVAL TIMER The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fX/25 fX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fX/29 BT fX/212 3 BTM3 SET1* BTM2 BTM1 Wait release signal for standby release BTM0 BTM 4 8 Internal bus *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 22 BT interrupt request flag Vector interrupt request IRQBT signal µPD75512(A) 5.5 WATCH TIMER The µPD75512(A) has a built-in 1-ch watch timer. The watch timer has these functions. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. • 0.5 second interval can be generated either from the main system clock or subsystem clock. • Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. • Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that zero second watch start is possible. fW (256 Hz: 3.91 ms) 27 fX From the 128 (32.768 kHz) clock generator f XT (32.768 kHz) Selector fW Frequency divider (32.768 kHz) f W (2.048 16 kHz) fW 2 14 INTW (IRQW set signal) Selector (2 Hz 0.5 sec) Clear Output buffer P23/BUZ WM WM7 PORT2.3 0 0 0 0 8 WM2 WM1 WM0 P23 output latch Bit 2 of PMGB Port 2 input/output mode Bit test instruction Internal bus Remarks: ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz. Fig. 5-4 Watch Timer Block Diagram 5.6 TIMER/EVENT COUNTER The µPD75512(A) has a built-in 1-ch timer/event counter. The timer/event counter has these functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. • Event counter operation • Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). • Supplies serial shift clock to the serial interface circuit. • Count condition read out function 23 24 Internal bus 8 SET1* TM0 8 8 TMOD0 TOE0 TO enable flag Modulo register (8) TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 Coincidence Comparator (8) Input buffer P20 output latch Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 PORT2.0 8 TOUT F/F Reset P20/PTO0 Output buffer T0 P13/TI0 From the clock generator Count register (8) MPX CP Clear ( INTT0 IRQT0 set signal ) Timer operation start signal RESET IRQT0 clear signal *:Instruction execution Fig. 5-5 Timer/Event Counter Block Diagram µPD75512(A) µPD75512(A) 5.7 TIMER/PULSE GENERATOR The µPD75512(A) contains a timer/pulse generator, that can be used as the timer or the pulse generator. Timer/ pulse generator has the following functions. (a) Function, when used in the timer mode • 8-bit interval timer operation (IRQTPG generation), for which the clock source can be changed in 5 steps. • Square waveform output to the PPO pin (b) Function, when used in the PWM pulse generation mode • 14-bit accuracy PWM pulse output to PPO pin (can be used as a D/A converter for electronics tuning). 15 • Fixed time interval interrupt generation (2 /fX = 7.81ms: fX = 4.19 MHz) When no pulse output is required, the PPO pin can be used as 1-bit output port. Note: When setting the STOP mode, if the timer pulse generator is in operating mode, erroneous operation may occur. Therefore, the timer/pulse generator must be set in no-operation state by the mode register, before setting the STOP mode. Internal bus 8 8 MODH MODL Modulo register L (8) Modulo register H (8) TPGM3 (Set to 1 ) INTTPG (IRQTPG set signal) Modulo latch H (8) 8 Coincidence Comparator (8) Output buffer Selector T F/F PPO Frequency divider fx 1/2 CP Prescaler select latch (5) Set 8 Count register (8) TPGM4 TPGM5 TPGM7 TPGM1 Clear Clear Fig. 5-6 Timer/Pulse Generator Block Diagram (Timer Mode) 25 µPD75512(A) Internal bus MODH MODL Modulo register H (8) Modulo register L (8) TPGM3 MODH(8) MODL7-2 (6) Modulo latch (14) Output buffer TPGM1 fx PWM pulse generator PPO Selector 1/2 Frequency divider INTTPG IRQTPG set signal TPGM5 TPGM7 15 (2 = 7.8 ms: f x at 4.19MHz) fx Fig. 5-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode) 5.8 SERIAL INTERFACE The µPD75512(A) is provided with two serial interface channels. Table 5-2 indicates differences between channel 0 and channel 1. Table 5-2 Differences Between Channel 0 and Channel 1 Serial Transfer Mode, Funciton 3-Line Serial I/O Channel 0 4 3 Channel 1 4 3 Clock Selection fX/2 , fX/2 , TOUT F/F, external clock fX/2 , fX/2 external clock Transfer Method MSB first/LSB first selectable MSB first Transfer Completion Flag Serial transfer completion interrupt request flag (IRQCSI0) Serial transfer completion flag (EOT) Usable Unprovided 2-Line Serial I/O Serial Bus Interface (SBI) (1) Serial interface function (Channel 0) The µPD75512(A) is equipped with the following four modes: • Operation stop mode • Three-line serial I/O mode • Two-line serial I/O mode • SBI mode (serial bus interface mode) 26 Internal bus 8/4 CSIM0 8 Bit test 8 8 Slave address register (SVA) (8) SBIC Coincidence signal Address comparator RELT CMDT (8) P03/SI/SB1 SET CLR Shift register (SIO0) (8) D SO0 latch Q ACKT ACKE BSYE Selector Bit test Bit manipulation Selector P02/SO/SB0 Busy/ acknowledge output circuit Bus release/ command/ acknowledge detector circuit P01/SCK0 Serial clock counter P01 output latch Serial clock control circuit RELD CMDD ACKD INTCSI0 control circuit ( MPX INTCSI0 IRQCSI0 set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) 27 µPD75512(A) External SCK0 Fig. 5-8 Serial Interface (Channel 0) Block Diagram ) µPD75512(A) (2) Serial interface (Channel 1) configuration µPD75512(A) serial interface (channel 1) has following two modes. • Operation stop mode • 3-line serial I/O mode 28 Internal bus 8 Bit manipulation SIO1 write signal (serial start signal) bit 0 P83/SI1 7 bit 7 SIO1 Shift register 1 (8) Bit manipulation 8 0 Serial operation mode (8) register 1 (8) CSIM1 P82/SO1 Clear Serial clock counter (3) Overflow Set Serial transfer completion flag (EOT) Clear P81/SCK1 R Q S fx /23 MPX Fig. 5-9 Serial Interface (Channel 1) Block Diagram 29 µPD75512(A) fx /24 µPD75512(A) 5.9 A/D CONVERTER The µ PD75512(A) is provided with an 8-bit resolution analog-to-digital (A/D) converter with eight channels of analog inputs (AN0-AN7). This A/D converter is of a successive approximation type. Internal bus 8 0 ADM6 ADM5 ADM4 SOC EOC ADM1 0 ADM 8 AN0 Control circuit AN1 Sample hold circuit AN3 AN4 Multiplexer AN2 SA register (8) + – Comparator AN5 AN6 8 AN7 Tap decoder AVREF R/2 R R R R/2 AVSS Fig. 5-10 Block Diagram of A/D Converter 30 µPD75512(A) 5.10 BIT SEQUENTIAL BUFFER ..... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-11 Bit Sequential Buffer Format 6. INTERRUPT FUNCTIONS The µPD75512(A) has 7 different interrupt sources and multiplexed interrupt with priority order. In addition to that, the µ PD75512 is also provided with two types of test sources, of which INT2 has two types of edge detection testable inputs. The interrupt control circuit of the µPD75512(A) has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 31 32 Internal bus 2 2 2 IM2 IM1 IM0 Interrupt enable flag (IExxx) INT BT INT4 /P00 INT0 /P10 INT1 /P11 KR7/P73 IRQ1 Priority control circuit Vector table address generator IRQW Selector INTW Falling edge detection circuit IRQ0 IRQTPG INTTPG KR0/P60 IST IRQT0 INTT0 Rising edge detection circuit IPS VRQn IRQ4 IRQCSI0 INTCSI0 2 Decoder IRQBT Both edge detection circuit Edge Noise detection elimination circuit circuit Edge detection circuit INT2 /P12 (IME) 4 Standby release signal IRQ2 Fig. 6-1 Interrupt Control Block Diagram µPD75512(A) IM2 µPD75512(A) 7. STANDBY FUNCTIONS In order to fully exploit the µPD75512(A) low power dissipation, CPU operation can be stopped by setting the unit to the standby mode, thus, further reducing power dissipation. The µPD75512(A) features two standby modes, a STOP mode and a HALT mode. Table 7-1 Status in Standby Mode Mode Item STOP Mode HALT Mode Instruction for Setting STOP instrtuction HALT instruction System Clock at the Time of Setting Can be set only when operating on the main system clock Can be set when operating either on the main system clock or the subsystem clock Clock Oscillator Only the main system clock can stop its operation. Only the CPU clock Φ stops its operation. (oscillation continues) Basic Interval Timer Does not operate Operates (Sets IRQBT with the reference time interval) Serial Interface (Channel 0) Can operate only when the external SCK0 input is selected as the serial clock Operates when the timer system clock is operating or external SCK0 is selected Serial Interface (Channel 1) Can operate only when the external SCK1 input is selected as the serial clock Operates only when the main system clock is operating Timer/Event Counter Can only operate when the TI0 pin input is selected as system clock Operates only when the main system clock is operating Clock Timer Operates when f XT is selected as the count clock Can operate A/D Converter Does not operate Operates only when the main system clock is operating Timer/Pulse Generator Does not operate Operates only when the main system clock is operating Operation Status Timer/Pulse Generator CPU Release Signal INT1, INT2, and INT4 can operate, but INT0 cannot operate Does not operate An interrupt request signal from a piece of hardware, whose operation is enabled by the interrupt enable flag, or the RESET signal input 33 µPD75512(A) 8. RESET FUNCTIONS When the RESET signal is input, the µPD75512(A) is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Fig. 8-1 Reset Operation by RESET Input Table 8-1 Status of Each Hardware after Reset (1/2) Hardware RESET Input in Standby Mode RESET Input during Operation The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. Same as left Retained Undefined 0 0 Interrupt Status Flag (IST0, 1) 0 0 Bank Enable Flag (MBE, RBE) The contents of bit 6 of address 0000H of the program memory are set to RBE and those of bit 7 are set to MBE. Same as left Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained * Undefined Retained Undefined Bank Selection Register (MBS, RBS) 0, 0 0, 0 Basic Interval Counter (BT) Timer Mode Register (BTM) Undefined Undefined 0 0 Program Counter (PC) PSW Carry Flag (CY) Skip Flag (SK0-2) General-Purpose Register (X, A, H, L, D, E, B, C) Timer/Event Counter Counter (T0) Modulo Register (TMOD0) Mode Register (TM0) Timer/Pulse Generator Watch Timer 0 0 FFH FFH 0 0 TOE0, TOUT F/F 0, 0 0, 0 Modulo Register Retained Retained Mode Register 0 0 Mode Register (WM) 0 0 *: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input. 34 µPD75512(A) Table 8-1 Status of Each Hardware after Reset (2/2) Hardware Serial Interface (Channel 0) Shift Register (SIO0) Retained Undefined 0 0 SBI Control Register (SBIC) 0 0 Retained Undefined 1 1 04H (EOC = 1) 04H (EOC = 1) P01/SCK0 Output Latch A/D Converter Mode Regiseter (ADM), EOC SA Register Serial Interface (Channel 1) Interrupt Function Digital Port RESET Input during Operation Operation Mode Register (CSIM0) Slave Address Register (SVA) Clock Generator, Clock Output Circuit RESET Input in Standby Mode 7FH 7FH Processor Clock Control Register (PCC) 0 0 System Clock Control Register (SCC) 0 0 Clock Output Mode Register (CLOM) 0 0 Retained Undefined Operation Mode Register 1 (CSIM1) 0 0 Serial Transfer End Flag (EOT) 0 0 Reset (0) Reset (0) Interrupt Enable Flag (IExxx) 0 0 Interrupt Master Enable Flag (IME) 0 0 INT0, INT1, INT2 Mode Registers (IM0, 1, 2) 0, 0, 0 0, 0, 0 Output Buffer Off Off Output Latch Shift Register (SIO1) Interrupt Request Flag (IRQxxx) Clear (0) Clear (0) Input/Output Mode Register (PMGA, B, C) 0 0 Pull-Up Resistor Specification Register (POGA) 0 0 Retained Undefined Bit Sequential Buffer (BSB0-3) 35 µPD75512(A) 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label* 2-bit immediate data or label fmem pmem FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr caddr faddr 0000H to 2F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx RBn MBn PORT0 to PORT15 IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG RB0-RB3 MB0, MB1, MB15 *: Only even addresses can be described in mem when processing 8-bit data. 36 µPD75512(A) (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator XA' : Expanded register pair (XA') BC' : Expanded register pair (BC') DE' : Expanded register pair (DE') HL' : Expanded register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 15) IME : Interrupt mask enable flag IPS : Interrupt priority selector register IExxx : Interrupt enable flag RBS : Memory bank selector register MBS : Memory bank selector register PCC : Processor clock control register . : Delimiter of address and bit (xx) : Contents addressed by xx xxH : Hexadecimal data 37 µPD75512(A) (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-2F7FH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H-0FFFH (PC13, 12 = 00B) or 1000H-1F7FH (PC13, 12 = 01B) or 2000H-2F7FH (PC13, 12 = 10B) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Remarks 1: (4) Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2: In *2, MB = 0 regardless of MBE and MBS. 3: In *4 and *5, MB = 15 regardless of MBE and MBS. 4: *6 to *10 indicate areas that can be addressed. Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped ····························································· S = 0 • When 1-byte or 2-byte instruction is skipped ······································ S = 1 • When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ······· S = 2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 38 µPD75512(A) Instructions Mnemonics Transfer MOV XCH Table Reference MOVT Operand A, #n4 Machine Bytes Cycles 1 1 Operation Addressing Area A ← n4 Skip Conditions String effect A reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A,mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 *3 mem, XA 2 2 (mem) ← XA A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 XA ← (PC13-8+DE)ROM XA, @PCXA 1 3 XA ← (PC13-8+XA)ROM 39 µPD75512(A) Addressing Area Mnemonics Operand Bit MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem. bit 2 2 CY ← (H+mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2+L 3-2.bit(L 1-0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3-0.bit) ← CY *1 Arithme- ADDS tic A,#n4 1 1+S A ← A+n4 carry XA,#n8 2 2+S XA ← XA+n8 carry Operation A,@HL 1 1+S A ← A+(HL) XA,rp’ 2 2+S XA ← XA+rp’ carry rp’1,XA 2 2+S rp’1 ← rp’1+XA carry A,@HL 1 1 A,CY ← A+(HL)+CY XA,rp’ 2 2 XA,CY ← XA+rp’+CY rp’1,XA 2 2 rp’1,CY ← rp’1+XA+CY A,@HL 1 1+S Transfer ADDC SUBS SUBC AND OR XOR 40 Machine Bytes Cycles Instructions Operation A ← A-(HL) XA,rp’ 2 2+S XA ← XA-rp’ rp’1,XA 2 2+S rp’1 ← rp’1-XA A,@HL 1 1 A,CY ← A-(HL)-CY XA,rp’ 2 2 XA,CY ← XA-rp’-CY rp’1,XA 2 2 rp’1,CY ← rp’1-XA-CY A,#n4 2 2 A←A A,@HL 1 1 A←A ∧ n4 ∧ (HL) XA,rp’ 2 2 XA ← XA-rp’ rp’1,XA 2 2 rp’1 ← rp’1 A,#n4 2 2 A←A A,@HL 1 1 XA,rp’ 2 2 rp’1,XA 2 2 A,#n4 2 2 A,@HL 1 1 XA,rp’ 2 2 rp’1,XA 2 2 ∧ XA ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp’ rp’1 ← rp’1 ∨ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp’ rp’1 ← rp’1 ∨ XA *1 Skip Conditions carry *1 *1 borrow borrow borrow *1 *1 *1 *1 µPD75512(A) Instructions Mnemonics Operand Bytes Machine Cycles Operation Addressing Area Skip Conditions Accumu- RORC lator A 1 1 CY ← A0, A3 ← CY, An-1 ← An Manipu- NOT A 2 2 A← A INCS reg 1 1+S reg ← reg+1 ment/ rp1 1 1+S rp1 ← rp1+1 Decre- @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 *3 (mem) = 0 lation Incre- ment DECS mem 2 2+S (mem) ← (mem)+1 reg 1 1+S reg ← reg-1 reg = 0 rp1 = 00H reg = FH rp’ 2 2+S rp’ ← rp’-1 rp’ = FFH Compari- SKE reg,#n4 2 2+S Skip if reg = n4 reg = n4 son @HL,#n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A,@HL 1 1+S Skip if A = (HL) *1 A = (HL) XA,@HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A,reg 2 2+S Skip if A = reg A = reg XA,rp’ 2 2+S Skip if XA = rp’ XA = rp’ Carry SET1 CY 1 1 Flag CLR1 CY 1 1 Manipu- SKT lation NOT1 CY 1 1+S CY 1 1 CY ← 1 CY ← 0 Skip if CY = 1 CY = 1 CY ← CY 41 µPD75512(A) Instructions Mnemonics Operand Operation Addressing Area Memory/ SET1 mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) ← 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 CLR1 SKT SKF fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 0 *5 AND1 OR1 XOR1 Branch BR Skip Conditions @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 (mem.bit) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 SKTCLR fmem.bit 42 Machine Bytes Cycles 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L 1-0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem 3-0.bit) = 1 and clear *1 (@H+mem.bit) = 1 ∧ (fmem.bit) CY,fmem.bit 2 2 CY ← CY CY,pmem.@L 2 2 CY ← CY ∧ (pmem 7-2+L3-2.bit(L1-0)) CY,@H+mem.bit 2 2 CY ← CY *4 *5 ∧ (H+mem3-0.bit) ← CY ∨ (fmem.bit) *4 *5 CY,fmem.bit 2 2 CY CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) CY,@H+mem.bit 2 2 CY ← CY CY,fmem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) ∨ (fmem.bit) *1 *1 *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) CY,@H+mem.bit 2 2 CY ← CY addr — — PC 13-0 ← addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) *6 ∨ (H+mem3-0.bit) *5 *1 !addr 3 3 PC 13-0 ← addr *6 $addr 1 2 PC 13-0 ← addr *7 BRCB !caddr 2 2 PC 13-0 ← PC13,12+caddr11-0 *8 BR PCDE 2 3 PC 13-0 ← PC13-8+DE PCXA 2 3 PC 13-0 ← PC13-8+XA µPD75512(A) Machine Bytes Cycles Addressing Area Instructions Mnemonics Subroutine/ Stack Control CALL !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, PC13,12 PC13-0 ← addr, SP ← SP-4 *6 CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, PC13,12 PC13-0 ← 00, faddr, SP ← SP-4 *9 RET 1 3 MBE, RBE, PC13,12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S MBE, RBE, PC13,12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RETI 1 3 PC13,12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 BS 2 2 (SP-1) ← MBS, (SP-2) ← RBS, SP ← SP-2 rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME (IPS.3) ← 1 2 2 IExxx ← 1 2 2 IME (IPS.3) ← 0 2 2 IExxx ← 0 PUSH POP Inter- EI rupt Control Operand IExxx DI IExxx I/O IN * 1 OUT * 1 Operation A,PORTn 2 2 A ← PORTn XA,PORTn 2 2 XA ← PORTn+1,PORTn PORTn,A 2 2 PORTn ← A PORTn,XA (n = 4, 6) (n = 2-7, 9-14) 2 2 PORTn+1,PORT n ← XA HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n MBn 2 2 1 3 SEL GETI * 2 taddr Undefined (n = 0-15) CPU Special Skip Conditions (n = 4, 6) (n = 0-3) MBS ← n (n = 0, 1, 15) . Where TBR instruction, PC13-0 ← (taddr)4-0+(taddr+1) ......................................................... . Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, PC13,12 PC13-0 ← (taddr)5-0+(taddr+1) SP ← SP-4 ......................................................... . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) *10 ............................. ............................. Depends on referenced instruction *1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. *2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of GETI instruction. 43 µPD75512(A) 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Symbol Supply Voltage Conditions Ratings VDD VI1 Other than ports 4, 5, 12-14 Input Voltage VI2 Ports 4, 5, 12-14 Output Voltage VO w/pull-up resistor V -0.3 to V DD+0.3 V -0.3 to VDD+0.3 Open drain High-Level Output Current Low-Level Output IOH* IOL* Unit -0.3 to +7.0 V -0.3 to +11 V -0.3 to V DD+0.3 V 1 pin Peak rms -10 -5 mA mA All pins Peak rms Peak -30 -15 10 mA mA mA rms 5 mA Peak rms 100 60 mA mA Peak 100 mA rms 60 mA 1 pin Current Total of ports 0, 2, 3, 4 Total of ports 5-11 Total of ports 12-14 Peak 40 mA rms mA °C °C Operating Temperature Topt 25 -40 to +85 Storage Temperature Tstg -65 to +150 *: rms = Peak value x √Duty OPERATING SUPPLY VOLTAGE Parameter A/D Converter Symbol Supply voltage Ambient temperature Timer/Pulse Supply voltage Generator Ambient temperatuare Other Circuits Supply voltage Ambient temperatuare MIN. MAX. Unit VDD Conditions 3.5 6.0 V °C Ta -40 +85 VDD 4.5 6.0 V Ta -40 +85 °C VDD 2.7 6.0 V Ta -40 +85 °C TYP. MAX. Unit 15 pF 15 pF 15 pF CAPACITANCE (T a = 25°C, VDD = 0 V) Parameter 44 Symbol Input Capacitance CI Output Capacitance CO Input/Output Capacitance CIO Conditions f = 1 MHz Pins other than thosemeasured are at 0 V MIN. µPD75512(A) MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Oscillator Recommended Constants Ceramic Item Oscillation frequency(fX)*1 X1 X2 C1 C2 Crystal Conditions VDD = osccillation voltage range 1.0 1.0 X1 input frequency (f X)*1 X1 X2 4.19 µ PD74HCU04 1.0 X1 input high-, low-level widths (t XH, t XL) *3 4 C2 External Clock MAX. 5.0 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 X2 C1 TYP. Oscillation stabiliza- After VDD came to MIN. value of tion time*2 oscillation voltage range Oscillation frequency (fX)*1 X1 MIN. 5.0 MHz ms MHz 10 ms 30 ms 5.0 100 *3 Unit *3 500 MHz ns SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Oscillator Recommended Constants Item Conditions Oscillation*1 Crystal XT1 frequency (fXT) XT2 R C3 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 10 s Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 C4 External Clock XT1 XT2 Open XT1 input frequency (f XT)*1 32 100 kHz XT1 input high-, low-level widths (tXTH, t XTL ) 5 15 µs *1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction ★ execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µ s. 45 µPD75512(A) ★ Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 46 µPD75512(A) DC CHARACTERISTICS (T a = -40 to +85°C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Symbol Conditions MIN. TYP. MAX. Unit VIH1 Ports 2, 3, 9-11, P80, P82 0.7VDD VDD V VIH2 Ports 0, 1, 6, 7, 15, P81, P83, RESET 0.8VDD VDD V VIH3 Ports 4, 5, 12-14 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7VDD 10 V VIH4 X1, X2, XT1 VDD -0.5 VDD V Low-level Input VIL1 Ports 2-5, 9-14, P80, P82 0 0.3VDD V Voltage VIL2 Ports 0, 1, 6, 7, 15, P81, P83, RESET 0 0.2VDD V VIL3 X1, X2, XT1 0 0.4 V High-Level Output VOH Voltage Low-Level Output Voltage High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current VOL ILIH1 VDD -1.0 VDD -0.5 Ports 3, 4, and 5 VDD = 4.5 to 6.0 V, IOL = 5 mA V V 1.0 V VDD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.2 0.5 V 0.2VDD V SB0, 1 Open-drain Pull-up resistor ≥ 1 kΩ VI = VDD Other than below 3 µA X1, X2, XT1 20 µA ILIH3 VI = 9 V Ports 4, 5, 12-14 (open-drain) 20 µA ILIL1 VI = 0 V Other than below ILIH2 ILIL2 X1, X2, XT1 ILOH1 VO = VDD Other than below ILOH2 VO = 9 V Ports 4, 5, 12-14 (open-drain) ILOL VO = 0 V Internal Pull-Up Resistor RU1 Internal Pull-Down Resistor VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 µA Ports 0, 1, 2, 3, 6, 7 (except P00) V I = 0V VDD = 5.0 V±10% 15 VDD = 3.0 V±10% 30 RU2 Ports 4, 5, 12-14 VO = V DD-2.0 V VDD = 5.0 V±10% 15 RD VO = 2 V VDD = 3.0 V±10% 10 Port 9 20 40 -3 µA -20 µA 3 µA 20 µA -3 µA 80 kΩ 300 kΩ 40 70 kΩ 60 kΩ 70 140 kΩ 47 µPD75512(A) Parameter Supply Current Symbol *1 IDD1 IDD2 IDD3 Conditions MHz*2 4.19 crystal oscillator C1 = C2 = 22pF IDD5 MAX. Unit VDD = 5 3 9 mA VDD = 3 V±10%* 4 0.55 1.5 mA HALT mode VDD = 5 V±10% 600 1800 µA VDD = 3 V±10% 200 600 µA 40 120 µA VDD = 3 V±10% 5 15 µA VDD = 5 V±10% 0.5 20 µA VDD = 3 V±10% 0.3 10 µA 5 µA HALT mode XT1 = 0 V STOP mode TYP. Ooperation mode 32.768 kHz*5 crystal Operation oscillator mode IDD4 MIN. V±10%* 3 VDD = 3 V±10% Ta = 25°C *1: Currents for the built-in pull-up resistor are not included. 2: Including when the subsystem clock is operated. 3: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 4: When operated in the low-speed mode with the PCC set to 0000. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation. 48 µPD75512(A) AC CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) (1) Basic Operation Parameter Symbol Conditions w/main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. Unit 0.95 64 µs 3.8 64 µs 125 µs CPU Clock Cycle Time*1 (Minimum Instruction Execution Time = 1 Machine Cycle) tCY TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, Low-Level Widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt Input High-, Low-Level Widths tINTH, tINTL INT0 *2 µs INT1, 2, 4 10 µs 10 µs RESET Low-Level Width tRSL 10 µs w/sub-system clock 114 KR0-7 122 *1: The CPU clock (Φ) cycle time is determined by the oscillation frequency tCY vs VDD of the connected oscillator, system clock control register (SCC), and processor (with main system clock) 70 clock control register (PCC). The figure 64 60 on the right is cycle time tCY vs. supply voltage V DD characteristics at the main 6 system clock. 5 2: 2tCY or 128/fX depending on the setting Guaranteed operating range 4 Cycle time tCY [µs] of the interrupt mode register (IM0). 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 49 µPD75512(A) (2) Serial Transfer Operation (a) Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKH1 1600 ns 3800 ns ns ns 150 ns 400 RL = 1 kΩ, CL = 100 pF* Unit (tKCY1/2)-50 SI Hold Time (vs. SCK ↑ ) tKSI1 tKSO1 MAX. (t KCY1/2)-150 SI Set-Up Time (vs. SCK ↑) tSIK1 SCK ↓→ SO Output Delay Time TYP. ns V DD = 4.5 to 6.0 V 250 ns 1000 ns MAX. Unit *: RL and CL are load resistance and load capacitance of the SO output line. (b) Two-Line and Three-Line Serial I/O Modes (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 ns 3200 ns 400 ns tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑) tKSI2 400 ns SCK ↓→ SO Output Delay Time tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V *: RL and CL are load resistance and load capacitance of the SO output line. 50 TYP. 300 ns 1000 ns µPD75512(A) (c) SBI Mode (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V TYP. MAX. Unit 1600 ns 3800 ns SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 SCK ↓→ SB0, 1 Output Delay Time tKSO3 SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns (d) VDD = 4.5 to 6.0 V MIN. VDD = 4.5 to 6.0 V tKCY3/2-50 ns tKCY3/2-150 ns 150 ns tKCY3/2 ns 0 250 0 1000 ns ns SBI Mode (SCK: external clock input (slave)) Parameter SCK Cycle Time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns tKCY4/2 ns SCK High-, Low-Level Widths tKL4 tKH4 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK4 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 SCK ↓→ SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 0 1000 ns ns *: RL and C L are load resistance and load capacitance of the SO output line. 51 µPD75512(A) (3) A/D Converter (Ta = -40 to +85°C, VDD = 3.5 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. 8 8 2.5 V ≤ AVREF ≤ VDD* 2 Absolute Accuracy*1 MAX. Unit 8 bit ±2.0 LSB Conversion Time*3 tCONV 168/fX µs Sampling Time*4 tSAMP 44/fX µs Analog Input Voltage VIAN AVREF V AVSS Analog Input Impedance RAN 1000 AVREF Current AIREF 1.0 *1: Absolute accuracy excluding quantization error (± MΩ 2.0 mA 1 –2 LSB) 2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AVREF). 2.5 V 0.6 V DD 0.65 V DD V DD (3.5 to 6.0 V) AV REF ADM1=0 ADM1=1 ADM1 can be set to either 0 or 1 when 0.6VDD ≤ AVREF ≤ 0.65VDD 3: Time since execution of conversion start instruction until EOC = 1 (40.1 µ s: fX = 4.19 MHz) 4: Time since execution of conversion start instruction until end of sampling (10.5 µs: fX = 4.19 MHz) 52 µPD75512(A) AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 53 µPD75512(A) SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tKSO2 SB0,1 54 tSIK2 tKSI2 µPD75512(A) SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 INTERRUPT INPUT TIMING tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING: tRSL RESET 55 µPD75512(A) LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Wait Time*2 Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Released by RESET Released by interrupt 217/fX ms *3 ms *1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 2 20/fX (approx. 250 ms) WAIT time ( ): f X = 4.19 MHz – 0 1 1 2 17/fX (approx. 31.3 ms) – 1 0 1 2 15/fX (approx. 7.82 ms) – 1 1 1 2 13/fX (approx. 1.95 ms) DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 56 µPD75512(A) PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S C D detail of lead end 25 24 80 1 G H I M J K M P 11. N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.7 Q 0.1 ± 0.1 S 3.0 MAX. +0.008 0.106 0.004 ± 0.004 0.119 MAX. 57 µPD75512(A) 12. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75512(A) be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, consult NEC. Table 12-1 Soldering Conditions of Surface Mount Type µPD75512GF(A)-xxx-3B9: 80-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1 IR30-00-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1 VP15-00-1 Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C max. (package surface temperature) WS60-00-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 58 µPD75512(A) APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD755XX(A) SERIES PRODUCTS Product Item µPD75512(A) ROM Configuration ROM (Bit) µPD75516(A) Mask ROM 12160 x 8 µPD75P516 EPROM/One-time PROM 16256 x 8 RAM (Bit) 16256 x 8 512 x 4 Mask Option • Ports 4, 5, 12, 14 are provided with internal pull-up resistors. Not provided • Port 9 is provided with an internal pull-down resistor. VPP, PROM, Pins for programming LED Direct Drive Electrical Supply Voltage Range Specifi- Absolute Maximum cations Not provided Provided Not offered Offered 2.7 to 6.0 V 4.75 to 5.5 V Differ in high-level / low-level output current Ratings DC Characteristics Differ in low-level output voltage A/D Converter Differ in ambient temperature range and absolute accuracy Characteristics Quality Grade Package Special 80-pin plastic QFP (14 x 20 mm) Standard • 80-pin plastic QFP (14 x 20 mm) • 80-pin ceramic WQFN 59 µPD75512(A) APPENDIX B. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75512(A): Hardware IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75516GF-R Emulation prove for µPD75512(A), provided with 80-pin conversion socket EV-9200G-80. EV-9200G-80 Software In-circuit emulator for 75X series PG-1500 PROM programmer PA-75P516GF PROM programmer adapter solely used for µPD75P516GF. It is connected to PG-1500. IE Control Program Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) PG-1500 Controller IBM PC/AT TM (PC DOS TM Ver.3.1) RA75X Relocatable Assembler * 1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 60 µPD75512(A) APPENDIX C. ★ RELATED DOCUMENTS 61 µPD75512(A) [MEMO] 62 µPD75512(A) GENERAL NOTES ON CMOS DEVICES ➀ STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . ➁ PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. ➂ STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 63 µPD75512(A) [MEMO] No p art of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 64