74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 25-BIT CONFIGURABLE REGISTERED BUFFER • FEATURES • • • • Member of the Texas Instruments Widebus+™ Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption • • • • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the Control and RESET Inputs RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low DESCRIPTION This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output. The 74SSTUB32864A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32864A ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level. ORDERING INFORMATION TA 0°C to 70°C (1) PACKAGE (1) LFBGA–ZKE Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING 74SSTUB32864AZKER SB864A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 DESCRIPTION (CONTINED) The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and gates the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn outputs low. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input should be pulled up to VCC through a pullup resistor. The two VREF pins (A3 and T3) are connected together internally by approximately 150Ω. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. 2 Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 ZKE PACKAGE Terminal Assignments for 1:1 Register-A (C0 = 0, C1 = 0) 1 2 3 4 5 6 A D1 (DCKE) NC VREF VCC Q1 (QCKE) DNU B D2 D15 GND GND Q2 Q15 S D3 D16 VCC VCC Q3 Q16 D D4 (DODT) NC GND GND Q4 (QODT) DNU E D5 D17 VCC VCC Q5 Q17 F D6 D18 GND GND Q6 Q18 G NC RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7 (QCS) DNU J CLK CSR VCC VCC NC NC K D8 D19 GND GND Q8 Q19 L D9 D20 VCC VCC Q9 Q20 M D10 D21 GND GND Q10 Q21 N D11 D22 VCC VCC Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 VCC VCC Q13 Q24 T D14 D25 VREF VCC Q14 Q25 Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection Submit Documentation Feedback 3 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0 4 Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 A D1 (DCKE) NC VREF VCC Q1A (QCKEA) Q1B (QCKEB) B D2 DNU GND GND Q2A Q2B S D3 DNU VCC VCC Q3A Q3B D D4 (DODT) NC GND GND Q4A (QODTA) Q4B(QODTB) E D5 DNU VCC VCC Q5A Q5B F D6 DNU GND GND Q6A Q6B G NC RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR VCC VCC NC NC K D8 DNU GND GND Q8A Q8B L D9 DNU VCC VCC Q9A Q9B M D10 DNU GND GND Q10A Q10B N D11 DNU VCC VCC Q11A Q11B P D12 DNU GND GND Q12A Q12B R D13 DNU VCC VCC Q13A Q13B T D14 DNU VREF VCC Q14A Q14B Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection Submit Documentation Feedback 5 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 Logic Diagram for 1:2 Register-A Configuration (Positive Logic); C0 = 0, C1 = 1 6 Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 ZKE PACKAGE (TOP VIEW) Terminal Assignments for 1:2 Register-b (C0 = 1, C1 = 1) 1 2 3 4 5 6 A D1 NC VREF VCC Q1A Q1B B D2 DNU GND GND Q2A Q2B S D3 DNU VCC VCC Q3A Q3B D D4 NC GND GND Q4A Q4B E D5 DNU VCC VCC Q5A Q5B F D6 DNU GND GND Q6A Q6B G NC RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR VCC VCC NC NC K D8 DNU GND GND Q8A Q8B L D9 DNU VCC VCC Q9A Q9B M D10 DNU GND GND Q10A Q10B N D11 (DODT) DNU VCC VCC Q11A (QODTA) Q11B (QODTB) P D12 DNU GND GND Q12A Q12B R D13 DNU VCC VCC Q13A Q13B T D14 (DCKE) DNU VREF VCC Q14A (QCKEA) Q14B (QCKEB) Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection Submit Documentation Feedback 7 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 Logic Diagram for 1:2 Register-B Configuration C0 = 1, C1 = 1 8 Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 TERMINAL FUNCTIONS TERMINAL NAME ELECTRICAL CHARACTERISTICS DESCRIPTION GND Ground Ground input VCC Power-supply voltage 1.8 V nominal VREF Input reference voltage 0.9 V nominal CLK Positive master clock input Differential input CLK Negative master clock input Differential input C0, C1 Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select. LVCMOS inputs RESET Asynchronous reset input. Resets registers and disables VREF, data, and clock differential-input receivers. When RESET is low, all Q outputs are forced low. LVCMOS input D1-D25 Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. SSTL_18 inputs CSR, DCS Chip select inputs. Disables D1–D25 (1) outputs switching when both inputs are high SSTL_18 inputs DODT The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input DCKE The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input Q1–Q25 (2) Data outputs that are suspended by the DCS and CSR control. 1.8 V CMOS outputs QCS Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QODT Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QCKE Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output NC No internal connection DNU Do not use. Inputs are in standby-equivalent mode, and outputs are driven low. (1) (2) Data inputs = D2, D3, D5, D6, D8-D25 when C0 = 0 and C1 = 0 Data inputs = D2, D3, D5, D6, D8-D14 when C0 = 0 and C1 = 1 Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1.D Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0 = 0 and C1 = 0 Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0 = 0 and C1 = 1 Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0 = 1 and C1 = 1. FUNCTION TABLE INPUTS OUTPUTS RESET DCS CSR CLK CLK Dn Qn H L X ↑ ↓ L L H L X ↑ ↓ H H H X L ↑ ↓ L L H X L ↑ ↓ H H H H H ↑ ↓ X Q0 X X H L X or Floating X or Floating L or H L or H X Q0 X or Floating X or Floating X or Floating L FUNCTION TABLE INPUTS OUTPUTS RESET CLK CLK H ↑ ↓ DCKE, DCS, DODT QCKE, QCS, QODT H H H ↑ ↓ L L H L orH L orH X Q0 L X or Floating X or Floating X or Floating L Submit Documentation Feedback 9 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VI Input voltage range (2) (3) (1) VALUE UNIT –0.5 to 2.5 V -0.5 to VCC + 0.5 V VO Output voltage range (2) (3) –0.5 to VCC + 0.5 V IIK Input clamp current, (VI < 0 or VI > VCC) ±50 mA IOK Output clamp current, (VO < 0 or VO > VCC) ±50 mA IO Continuous output current (VO = 0 to VCC) ±50 mA ICCC Continuous current through each VCC or GND ±100 mA RθJA Thermal impedance, junction-to-ambiant (4) RθJB Thermal resistance, junction-to-board (4) Tstg Storage temperature range (1) (2) (3) (4) No airflow 39.8 Airflow 150 ft/min 34.1 Airflow 250 ft/min 33.6 Airflow 500 ft/min 32.5 No airflow 14.5 K/W °C –65 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) MIN NOM UNIT Supply voltage VREF Reference voltage VTT Termination voltage VI Input voltage VIH AC high-level input voltage Data inputs, CSR VIL AC low-level input voltage Data inputs, CSR VIH DC high-level input voltage Data inputs, CSR VIL DC low-level input voltage Data inputs, CSR VIH High-level input voltage RESET, Cn VIL Low-level input voltage RESET, Cn VICR Common-mode input voltage range CLK, CLK 0.675 VI(PP) Peak-to-peak input voltage CLK, CLK 600 IOH High-level output current Q outputs –8 mA IOL Low-level output current Q outputs 8 mA TA Operating free-air temperature 70 °C (1) 10 1.7 MAX VCC 1.9 V 0.49 × VCC 0.5 × VCC 0.51 × VCC V VREF–40 mV VREF VREF + 40 mV V VCC V 0 VREF + 250 mV V VREF–250 mV VREF + 125 mV V VREF–125 mV 0.65 × VCC V V 0.35 × VCC 0 V 1.125 V V mV The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH Q outputs VOL Q outputs II ICC ICCD IOH = –100 µA 1.7V to 1.9V IOH = –6 mA 1.7V IOL = 100 µA MIN TYP (1) MAX VCC–0.2 UNIT V 1.3 1.7V to 1.9V 0.2 1.7V 0.4 All other inputs (2) VI = VCC or GND 1.9V ±5 µA Static standby RESET = GND 200 µA Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) 40 mA Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input, 1:1 configuration Chip-select-enabled low-power active mode – clock only Chip-select-enabled ICCDLP low-power active mode 1:1 configuration Chip-select-enabled low-power active mode – 1:2 configuration (1) (2) VCC IOL = 6 mA Dynamic operating – per each data input, 1:2 configuration Ci TEST CONDITIONS RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle IO = 0 1.9V 1.8V 43 Data inputs, CSR VI = VREF± 250 mV CLK, CLK VICR = 0.9 V, VI(PP) = 600 mV RESET VI = VCC or GND µA clock MHz/ D input 60 RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle µA/MHz 45 IO = 0 µA/MHz 45 IO = 0 1.8V 2 µA clock MHz/ D input 3 2.5 1.8V 3 2 V 3.5 3 pF 4 All typical values are at VCC = 1.8 V, TA = 25°C. Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. Submit Documentation Feedback 11 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 and (1) VCC = 1.8 V ± 0.1 V MIN MAX 410 UNIT fclock Clock frequency tw Pulse duration, CLK, CLK high or low tact Differential inputs active time (2) 10 ns tinact Differential inputs inactive time (3) 15 ns tsu Setup time DCS before CLK↑, CLK↓, CSR low 1 DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high th (1) (2) (3) Hold time MHz ns 600 500 DODT, DCKE, and Data before CLK↑, CLK↓ 500 DCS, DODT, DCKE, and Data after CLK↑, CLK↓ 400 ps ps All inputs slew rate is 1 V/ns ± 20%. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) FROM (INPUT) TO (OUTPUT) CLK and CLK Q RESET Q PARAMETER fmax See Figure 2 tpdm Production test, See Figure 1 tRPHL (1) See Figure 2 (1) VCC = 1.8 V ± 0.1 V MIN MAX 410 UNIT MHz 0.4 0.7 ns 3 ns Includes 350-ps test-load transmission-line delay. OUTPUT SLEW RATES over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) (1) 12 PARAMETER FROM TO dV/dt_r 20% dV/dt_f 80% dV/dt_∆ (1) 20% or 80% 80% or 20% Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). Submit Documentation Feedback VCC = 1.8 V ± 0.1 V UNIT MIN MAX 80% 1 4 V/ns 20% 1 4 V/ns 1 V/ns 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Figure 1. Output Load For Production Test PROPAGATION DELAY (Design Goal as per JEDEC Specification) PARAMETER FROM (INPUT) TO (OUTPUT) tpdm (1) CLK and CLK Q CLK and CLK Q tpdmss (1) (1) VCC = 1.8 V ± 0.1 V UNIT MIN MAX 1.1 1.5 ns 1.6 ns Includes 350 psi test-load transmission delay line Submit Documentation Feedback 13 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 Figure 2. Data Output Load Circuit and Voltage Waveforms 14 Submit Documentation Feedback 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 Figure 3. Data Output Slew-Rate Measurement Information Submit Documentation Feedback 15 74SSTUB32864A www.ti.com SCAS838 – OCTOBER 2006 APPLICATION INFORMATION The typical values below are for standard raw cards. Test equipment used was the JEDEC register validation board using pattern 0x43, 0x4F, and 0x5A. Table 1. Raw Card Values RAW CARD (1) (2) 16 (1) (2) tpdmss OVERSHOOT MIN MAX A/F (@ 800 MBit/s) 1.0 ns 1.5 ns 590 mV B/G (@ 800 MBit/s) 1.2 ns 1.9 ns 590 mV C/H (@ 800 MBit/s) 1.2 ns 1.9 ns 730 mV J (@ 667 MBit/s) 1.3 ns 2.0 ns 340 mV All values are valid under nominal conditions and minimum/maximum of typical signals on one typical DIMM. Measurements include all jitter and ISI effects. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 9-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 74SSTUB32864AZKER ACTIVE LFBGA ZKE Pins Package Eco Plan (2) Qty 96 1000 Green (RoHS & no Sb/Br) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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