Revised August 2000 100341 Low Power 8-Bit Shift Register General Description Features The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs (Pn) and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup time before the positive-going transition of the clock pulse and their outputs respond a propagation delay after this rising clock edge. ■ 35% power reduction of the 100141 ■ 2000V ESD protection ■ Pin/function compatible with 100141 ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either “parallel entry”, “hold”, “shift left” or “shift right” as described in the Truth Table. All inputs have 50 kΩ pulldown resistors. Ordering Code: Order Number Package Number Package Description 10034SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100341PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100341QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100341QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pin Descriptions Pin Names Description CP Clock Input S0 , S1 Select Inputs D0 , D7 Serial Inputs P0–P7 Parallel Inputs Q0–Q7 Data Outputs © 2000 Fairchild Semiconductor Corporation 28-Pin PLCC DS009880 www.fairchildsemi.com 100341 Low Power 8-Bit Shift Register July 1988 100341 Truth Table Function Inputs Outputs D7 D0 S1 S0 Load Register X X L L Shift Left X L L H Shift Left X H L H CP Shift Right L X H L Shift Right H X H L Hold X X H H Hold X X X X H Hold X X X X L Q6 Q5 Q4 Q3 Q2 Q1 Q0 P7 P6 P5 P4 P3 P2 P1 P0 Q6 Q5 Q4 Q3 Q2 Q1 Q0 L Q6 Q5 Q4 Q3 Q2 Q1 Q0 H L Q7 Q6 Q5 Q4 Q3 Q2 Q1 H Q7 Q6 Q5 Q4 Q3 Q2 Q1 X No Change H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care = LOW-to-HIGH Transition Logic Diagram www.fairchildsemi.com Q7 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature (TSTG) +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V VEE Pin Potential to Ground Pin Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100341 Absolute Maximum Ratings(Note 1) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) Conditions Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V −1035 mV VIN = VIH (Min) Loading with −1610 mV or VIL (Max) 50Ω to −2.0V −1165 −870 mV Guaranteed HIGH Signal Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current VOHC Output HIGH Voltage VOLC Output LOW Voltage VIH Input HIGH Voltage VIL for all Inputs for all Inputs µA 240 µA VIN = VIL (Min) VIN = VIH (Max) Inputs OPEN −157 −75 mA VEE = −4.2V to −4.8V −167 −75 mA VEE = −4.2V to −5.7V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter fMAX Max Clock Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH Hold tPW(H) Pulse Width HIGH Min TC = +25°C Max Min 0.90 1.90 0.35 1.30 400 CP TC = +85°C Min 1.00 2.00 1.00 2.10 ns 0.35 1.30 0.35 1.30 ns 400 Max Units Max 400 Dn, Pn 0.65 0.65 0.65 Sn 1.60 1.60 1.60 Dn, Pn 0.80 0.80 0.80 Sn 0.60 0.60 0.60 2.00 2.00 2.00 MHz Conditions Figures 2, 3 Figures 1, 3 (Note 4) Figures 1, 3 ns ns ns Figure 4 Figure 3 Note 4: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. 3 www.fairchildsemi.com 100341 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter Min fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time TC = +25°C Max Min 425 Max 425 TC = +85°C Min 425 1.70 1.00 1.80 1.00 1.90 ns 0.35 1.20 0.35 1.20 0.35 1.20 ns Dn, Pn 0.55 0.55 0.55 1.50 1.50 1.50 Dn, Pn 0.70 0.70 0.70 Sn 0.50 0.50 0.50 2.00 2.00 2.00 Hold Time tPW(H) Pulse Width HIGH tOSHL Maximum Skew Common Edge CP Output-to-Output Variation MHz 0.90 Sn tH Units Conditions Max Figures 2, 3 Figures 1, 3 (Note 5) Figures 1, 3 ns Figure 4 ns ns Figure 3 PLCC Only 200 200 200 ps 200 200 200 ps 250 250 250 ps 250 250 250 ps (Note 6) Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 6) Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 6) Clock to Output Path tps Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 6) Clock to Output Path Note 5: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design www.fairchildsemi.com 4 100341 Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C TC = 0°C to +85°C Symbol Parameter Min Max Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH(Max) VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current −1035 −1565 Loading with for all Inputs for all Inputs µA 0.50 240 240 VIN = VIL (Min) µA VIN = VIH (Max) Inputs OPEN −157 −75 −157 −75 mA VEE = −4.2V to −4.8V −167 −75 −167 −75 mA VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = −40°C Parameter fMAX Max Clock Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH Hold Time tPW(H) Pulse Width HIGH Min TC = +25°C Max Min 425 Max 425 TC = +85°C Min Max 425 Units MHz 0.90 1.80 1.00 1.80 1.00 1.90 ns 0.30 1.90 0.35 1.20 0.35 1.20 ns Dn, P n 0.60 0.55 0.55 Sn 1.70 1.50 1.50 Dn, P n 0.90 0.70 0.70 Sn 0.50 0.50 0.50 CP 2.00 2.00 2.00 Conditions Figures 2, 3 Figures 1, 3 (Note 8) Figures 1, 3 ns ns ns Figure 4 Figure 3 Note 8: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously. 5 www.fairchildsemi.com 100341 Test Circuitry Note: • VCC, VCCA = +2V, VEE = −2.5V • L1, L2 and L3 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCCand VEE • All unused outputs are loaded with 50Ω to GND • CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Note: • For shift right mode pulse generator connected to S0 is moved to S1. • Pulse generator connected to S1 has a LOW frequency 99% duty cycle, which allows occasional parallel load. • The feedback path from output to input should be as short as possible. FIGURE 2. Shift Frequency Test Circuit (Shift Left) www.fairchildsemi.com 6 100341 Switching Waveforms FIGURE 3. Propagation Delay and Transition Times Note: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 4. Setup and Hold Times 7 www.fairchildsemi.com 100341 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100341 Low Power 8-Bit Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com