Revised August 1999 74FR74 • 74FR1074 Dual D-Type Flip-Flop General Description Features The 74FR74 and 74FR1074 are dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is transferred to the outputs on the rising edge of the clock input (CPn). The 74FR1074 is the negative edge triggered version of this device. Both parts feature asynchronous clear (CDn) and set (SDn) inputs which are low level enabled. ■ 74FR74 is pin-for-pin compatible with the 74F74 ■ True 150 MHz fMAX capability on 74FR74 ■ Outputs sink 24 mA and source 24 mA ■ Guaranteed pin-to-pin skew specifications Ordering Code: Order Number 74FR74SC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74FR1074SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR1074PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74FR74 © 1999 Fairchild Semiconductor Corporation 74FR1074 DS010977 www.fairchildsemi.com 74FR74 • 74FR1074 Dual D-Type Flip-Flop March 1992 74FR74 • 74FR1074 Logic Symbols Pin Descriptions Pin Names 74FR74 Description Dn Data Inputs CPn Clock Inputs SDn Asynchronous Set Inputs CDn Asynchronous Clear Inputs Qn True Output Qn Complementary Output Truth Tables 74FR74 Inputs Outputs SD CD CP D Q L H X X H L H L X X L H X H H H H L L L H X Q0 Q0 L L H H H H H H X L Q H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Rising Edge Q0 = Previous Q(Q) before LOW-to-HIGH Clock Transition 74FR1074 74FR1074 Inputs Outputs SD CD CP D Q L H X X H L H L X X L H X H H H H L L L H X Q0 Q0 L L H H H H H H X L H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Falling Edge Q0 = Previous Q(Q) before HIGH-to-LOW Clock Transition www.fairchildsemi.com 2 Q 74FR74 • 74FR1074 Logic Diagrams 74FR74 74FR1074 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74FR74 • 74FR1074 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage VCC Pin Potential to Ground Pin 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to VCC Standard Output Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 2000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage Recognized HIGH Signal VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH 2.5 V Min IOH = −1 mA Voltage 2.4 V Min IOH = −3 mA Recognized LOW Signal IIN = −18 mA V Min IOH = −24 mA VOL Output LOW Voltage 0.5 V Min IOL = 24 mA IIH Input HIGH Current 5 µA Max VIN = 2.7V IBVI Input HIGH Current IIL Input LOW Current 2.0 Breakdown Test VID Input Leakage Test IOD Output Circuit 7 µA Max VIN = 7.0V −150 µA Max VIN = 0.5V (Dn, CPn) −1.8 mA Max VIN = 0.5V (CDn, SDn) V 0.0 IID = 1.9 µA, 3.75 V 0.0 VIOD = 150 mV, −275 mA Max VOUT = 0.0V 50 µA Max VOUT = VCC 24 mA Max 4.75 All Other Pins Grounded Leakage Test IOS Output Short-Circuit Current ICEX Output HIGH All Other Pins Grounded −100 Leakage Current ICC Power Supply Current www.fairchildsemi.com 4 Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 150 190 tPLH Propagation Delay 2.5 3.5 tPHL CPn to Qn or Qn 2.5 4.5 6.0 2.5 6.0 tPLH Propagation Delay 1.5 3.5 5.5 1.5 5.5 tPHL CDn or SDn to Qn or Qn 2.0 5.5 7.0 2.0 7.0 tOSHL Pin to Pin Skew (Note 3) for HL Transitions tOSLH Pin to Pin Skew (Note 3) for LH Transitions tOST Pin to Pin Skew (Note 3) for HL/LH Transitions tQ/Q True/Complement (Note 3) Output Skew tPS Pin (Signal) (Note 3) Transition Variation Max Min Max 150 5.0 2.5 Units MHz 5.0 ns ns 1.0 ns 1.0 ns 3.0 ns 1.8 ns 1.8 ns Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOST is guaranteed by design. AC Operating Requirements 74FR74 Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Max Min Units Max tS(H) Setup Time, HIGH or LOW 2.5 2.5 tS(L) Dn to CPn 2.5 2.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) Dn to CPn 0 0 tW(H) CPn Pulse Width 3.3 3.3 tW(L) HIGH or LOW 3.3 3.3 tW(L) SDn or CDn Pulse Width 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns ns ns ns (Note 4) SDn or CDn to CPn Note 4: This specification is guaranteed by design. 5 www.fairchildsemi.com 74FR74 • 74FR1074 AC Electrical Characteristics 74FR74 74FR74 • 74FR1074 AC Electrical Characteristics 74FR1074 Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 120 160 tPLH Propagation Delay 2.5 4.0 tPHL CPn to Qn or Qn 3.0 5.0 6.5 3.0 6.5 tPLH Propagation Delay 1.5 3.5 5.5 1.5 5.5 tPHL CDn or SDn to Qn or Qn 2.0 5.5 7.0 2.0 7.0 tOSHL Pin to Pin Skew (Note 5) for HL Transitions tOSLH Pin to Pin Skew (Note 5) for LH Transitions tOST Pin to Pin Skew (Note 5) for HL/LH Transitions tQ/Q True/Complement (Note 5) Output Skew tPS Pin (Signal) (Note 5) Transition Variation Max Min Max 120 5.5 2.5 Units MHz 5.5 ns ns 1.5 ns 1.5 ns 3.5 ns 2.0 ns 2.0 ns Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOST is guaranteed by design. AC Operating Requirements 74FR1074 Symbol Parameter TA = +25°C TA = 0°C = +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH or LOW 2.0 2.0 tS(L) Dn to CPn 2.0 2.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) Dn to CPn 0 0 Units Max ns ns tW(H) CPn Pulse Width 3.3 3.3 tW(L) HIGH or LOW 3.3 3.3 tW(L) SDn or CDn Pulse Width 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns ns (Note 6) SDn or CDn to CPn Note 6: This specification is guaranteed by design. www.fairchildsemi.com 6 74FR74 • 74FR1074 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 7 www.fairchildsemi.com 74FR74 • 74FR1074 Dual D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8