SSM4501GSD
N AND P-CHANNEL ENHANCEMENT
MODE POWER MOSFET
PRODUCT SUMMARY
N-CH BVDSS
D2
D2
Simple Drive Requirement
Low On-resistance
Fast Switching Characteristic
30V
RDS(ON)
D1
D1
27mΩ
ID
P-CH BVDSS
G2
S2
PDIP-8
DESCRIPTION
7A
-30V
RDS(ON)
G1
S1
49mΩ
ID
-5A
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
D1
D2
G1
G2
Pb-free; RoHS-compliant
S1
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
N-channel
VDS
Drain-Source Voltage
VGS
Gate-Source Voltage
ID@TA=25℃
ID@TA=70℃
Units
P-channel
30
-30
V
±20
±20
V
3
7
-5
A
3
5.8
-4.2
A
40
-30
A
Continuous Drain Current
Continuous Drain Current
1
IDM
Pulsed Drain Current
PD@TA=25℃
Total Power Dissipation
2
W
Linear Derating Factor
0.016
W/℃
TSTG
Storage Temperature Range
-55 to 150
℃
TJ
Operating Junction Temperature Range
-55 to 150
℃
THERMAL DATA
Symbol
Rthj-a
01/28/2008 Rev.1.00
Parameter
Thermal Resistance Junction-ambient
3
www.SiliconStandard.com
Max.
Value
Unit
62.5
℃/W
1
SSM4501GSD
N-CH ELECTRICAL CHARACTERISTICS
o
@TJ=25 C (unless otherwise specified )
Symbol
Parameter
Test Conditions
BVDSS
Drain-Source Breakdown Voltage
ΔBVDSS/ΔTj
RDS(ON)
30
-
-
V
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA
-
0.03
-
V/℃
Static Drain-Source On-Resistance2
VGS=10V, ID=7A
-
-
27
mΩ
VGS=4.5V, ID=5A
-
-
50
mΩ
VDS=VGS, ID=250uA
1
-
3
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=10V, ID=7A
-
12
-
S
o
VDS=30V, VGS=0V
-
-
1
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=24V, VGS=0V
-
-
25
uA
Gate-Source Leakage
VGS=±20V
-
-
ID=7A
-
9
13
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Min. Typ. Max. Units
2
±100 nA
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=24V
-
2
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
5
-
nC
VDS=15V
-
6
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=1A
-
5
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω,VGS=10V
-
19
-
ns
tf
Fall Time
RD=15Ω
-
4
-
ns
Ciss
Input Capacitance
VGS=0V
-
645
800
pF
Coss
Output Capacitance
VDS=25V
-
150
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
95
-
pF
SOURCE-DRAIN DIODE
Symbol
VSD
Parameter
2
Forward On Voltage
IS=1.7A, VGS=0V
2
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
01/28/2008 Rev.1.00
Test Conditions
Min. Typ. Max. Units
-
-
1.2
V
IS=7A, VGS=0V,
-
16
-
ns
dI/dt=100A/µs
-
10
-
nC
www.SiliconStandard.com
2
SSM4501GSD
P-CH ELECTRICAL CHARACTERISTICS
o
@TJ=25 C (unless otherwise specified )
Symbol
Parameter
Test Conditions
BVDSS
Drain-Source Breakdown Voltage
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=-1mA
RDS(ON)
2
Static Drain-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
IGSS
VGS=0V, ID=-250uA
Min. Typ. Max. Units
-30
-
-
V
-
-0.03
-
V/℃
VGS=-10V, ID=-5A
-
-
49
mΩ
VGS=-4.5V, ID=-3A
-
-
75
mΩ
VDS=VGS, ID=-250uA
-1
-
-3
V
VDS=-10V, ID=-5.3A
-
8
-
S
o
VDS=-30V, VGS=0V
-
-
-1
uA
o
Drain-Source Leakage Current ( Tj =70 C)
VDS=-24V, VGS=0V
-
-
-25
uA
Gate-Source Leakage
VGS= ± 20V
-
-
Drain-Source Leakage Current ( Tj =25 C)
2
±100 nA
Qg
Total Gate Charge
ID=-5A
-
9
15
nC
Qgs
Gate-Source Charge
VDS=-24V
-
2
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=-4.5V
-
5
-
nC
VDS=-15V
-
10
-
ns
2
td(on)
Turn-on Delay Time
tr
Rise Time
ID=-1A
-
7
-
ns
td(off)
Turn-off Delay Time
RG=6Ω,VGS=-10V
-
27
-
ns
tf
Fall Time
RD=15Ω
-
16
-
ns
Ciss
Input Capacitance
VGS=0V
-
460 730
pF
Coss
Output Capacitance
VDS=-25V
-
180
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
130
-
pF
SOURCE-DRAIN DIODE
Symbol
VSD
Parameter
Test Conditions
2
Forward On Voltage
2
Min. Typ. Max. Units
IS=-1.7A, VGS=0V
-
-
-1.2
V
trr
Reverse Recovery Time
IS=-5A, VGS=0V,
-
21
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
18
-
nC
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
2
3.Mounted on 1 in copper pad of FR4 board ; 90℃/W when mounted on Min. copper pad.
01/28/2008 Rev.1.00
www.SiliconStandard.com
3
SSM4501GSD
N-Channel
36
40
10V
8.0V
6.0V
5.0V
ID , Drain Current (A)
30
20
V G =4. 0 V
5.0V
24
12
V G =4.0V
10
0
0
0
1
2
3
4
0
2
V DS , Drain-to-Source Voltage (V)
3
5
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2
100
I D =7A
V G = 10V
Normalized RDS(ON)
I D =7A
T A =25 ℃
70
RDS(ON) (mΩ )
10V
8.0V
6.0V
T A =150 o C
ID , Drain Current (A)
T A =25 o C
40
1.4
0.8
0.2
10
2
5
8
-50
11
0
50
100
150
o
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
3
10
2.5
1
IS(A)
VGS(th) (V)
2
T J =150 o C
o
T J =25 C
0.1
1.5
1
0.5
0.01
0
0.4
0.8
1.2
0
-50
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
01/28/2008 Rev.1.00
0
50
T j , Junction Temperature (
100
o
150
C)
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
www.SiliconStandard.com
4
SSM4501GSD
N-Channel
f=1.0MHz
12
1000
9
C iss
V DS =16V
V DS =20V
V DS =24V
C (pF)
VGS , Gate to Source Voltage (V)
I D =7.0A
6
C oss
C rss
100
3
0
10
0
4
8
12
16
1
7
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
19
25
31
Fig 8. Typical Capacitance Characteristics
100
Normalized Thermal Response (Rthja)
1
100us
10
1ms
ID (A)
13
V DS , Drain-to-Source Voltage (V)
10ms
100ms
1
1s
10s
DC
0.1
o
T A =25 C
Single Pulse
Duty Factor = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
Single Pulse
0.01
t
T
Duty Factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja =90o C/W
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
V DS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
VDS
90%
Fig 10. Effective Transient Thermal Impedance
VG
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off)tf
Charge
Fig 11. Switching Time Waveform
01/28/2008 Rev.1.00
Q
Fig 12. Gate Charge Waveform
www.SiliconStandard.com
5
SSM4501GSD
P-Channel
40
36
-10V
-8.0V
-6.0V
T A =25 o C
-10V
-8.0V
-6.0V
o
T A =150 C
-ID , Drain Current (A)
-ID , Drain Current (A)
30
-5.0V
20
V G = - 4. 0 V
10
24
-5.0V
12
V G = - 4. 0 V
0
0
0
1
2
3
0
4
1
2
3
4
5
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
120
1.8
I D =-5.0A
T A =25 ℃
I D =-5.0A
V G = -10V
Normalized R DS(ON)
1.6
RDS(ON) (mΩ )
90
60
1.4
1.2
1
0.8
0.6
30
3
5
7
9
-50
11
0
50
100
150
T j , Junction Temperature ( o C)
-V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
10
3
2.5
1
-IS(A)
T j =150 o C
-VGS(th) (V)
2
T j =25 o C
0.1
1.5
1
0.5
0.01
0
0.1
0.4
0.7
1
1.3
-50
0
Fig 5. Forward Characteristic of
Reverse Diode
01/28/2008 Rev.1.00
50
100
150
o
-V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( C )
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
www.SiliconStandard.com
6
SSM4501GSD
P-Channel
f=1.0MHz
1000
I D =-5.0A
V DS =-24V
10
C iss
8
C oss
C (pF)
-VGS , Gate to Source Voltage (V)
12
6
C rss
100
4
2
0
10
0
4
8
12
16
1
5
9
13
17
21
25
29
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Normalized Thermal Response (Rthja)
Duty Factor = 0.5
100us
10
-ID (A)
1ms
10ms
1
100ms
0.2
0.1
0.1
0.05
0.02
0.01
PDM
0.01
1s
10s
DC
0.1
T A =25 o C
Single Pulse
0.01
Single Pulse
t
T
Duty Factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=90oC/W
0.001
0.1
1
10
100
0.0001
0.001
-V DS , Drain-to-Source Voltage (V)
Fig 9. Gate Charge Characteristics
0.01
0.1
1
10
100
1000
t , Pulse Width (s)
Fig 10. Typical Capacitance Characteristics
VG
VDS
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off)tf
Charge
Fig 11. Switching Time Waveform
01/28/2008 Rev.1.00
Q
Fig 12. Gate Charge Waveform
www.SiliconStandard.com
7
SSM4501GSD
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
01/28/2008 Rev.1.00
www.SiliconStandard.com
8