ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit V(BR)DSS 125 — — Vdc Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) IDSS — — 5.0 mAdc Gate–Body Leakage Current (VGS = 20 V, VDS = 0) IGSS — — 1.0 µAdc Gate Threshold Voltage (VDS = 10 V, ID = 100 mA) VGS(th) 1.0 3.0 5.0 Vdc Drain–Source On–Voltage (VGS = 10 V, ID = 10 A) VDS(on) 1.0 3.0 5.0 Vdc gfs 5.0 7.0 — mhos Input Capacitance (VDS = 50 V, VGS = 0, f = 1.0 MHz) Ciss — 350 — pF Output Capacitance (VDS = 50 V, VGS = 0, f = 1.0 MHz) Coss — 220 — pF Reverse Transfer Capacitance (VDS = 50 V, VGS = 0, f = 1.0 MHz) Crss — 15 — pF Gps 18 — 22 13 — — dB η 40 45 — % IMD(d3) IMD(d11) — — – 32 – 60 – 30 — OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0, ID = 100 mA) ON CHARACTERISTICS Forward Transconductance (VDS = 10 V, ID = 5.0 A) DYNAMIC CHARACTERISTICS FUNCTIONAL TESTS Common Source Amplifier Power Gain, f = 30; 30.001 MHz (VDD = 50 V, Pout = 150 W (PEP), IDQ = 250 mA) f = 175 MHz Drain Efficiency (VDD = 50 V, Pout = 150 W (PEP), f = 30; 30.001 MHz, ID (Max) = 3.75 A) Intermodulation Distortion (1) (VDD = 50 V, Pout = 150 W (PEP), f = 30 MHz, f2 = 30.001 MHz, IDQ = 250 mA) dB ψ Load Mismatch (VDD = 50 V, Pout = 150 W (PEP), f1 = 30; 30.001 MHz, IDQ = 250 mA, VSWR 30:1 at all Phase Angles) No Degradation in Output Power CLASS A PERFORMANCE Intermodulation Distortion (1) and Power Gain (VDD = 50 V, Pout = 50 W (PEP), f1 = 30 MHz, f2 = 30.001 MHz, IDQ = 3.0 A) GPS IMD(d3) IMD(d9 – 13) — — — 23 – 50 – 75 — — — dB NOTE: 1. To MIL–STD–1311 Version A, Test Method 2204B, Two Tone, Reference Each Tone. BIAS + 0 – 12 V – C5 D.U.T. R1 RF INPUT R3 T1 C7 C8 T2 C1 — 470 pF Dipped Mica C2, C5, C6, C7, C8, C9 — 0.1 µ F Ceramic Chip or Monolythic with Short Leads C3 — 200 pF Unencapsulated Mica or Dipped Mica with Short Leads C4 — 15 pF Unencapsulated Mica or Dipped Mica with Short Leads C10 — 10 µ F/100 V Electrolytic R2 C9 + – C10 50 V – RF OUTPUT C3 L1 — VK200/4B Ferrite Choke or Equivalent, 3.0 µ H L2 — Ferrite Bead(s), 2.0 µ H R1, R2 — 51 Ω /1.0 W Carbon R3 — 3.3 Ω /1.0 W Carbon (or 2.0 x 6.8 Ω /1/2 W in Parallel) T1 — 9:1 Broadband Transformer Communication Concepts, Inc. RF800-9 material 43 or equiv. T2 — 1:9 Broadband Transformer Board Material — 0.062″ Fiberglass (G10), 1 oz. Copper Clad, 2 Sides, e r = 5 Figure 1. 30 MHz Test Circuit 2 L2 C4 C2 C1 REV 1 + L1 C6 RFC2 +50 V + C10 R1 BIAS 0 – 12 V C11 L4 + C4 C5 R3 D.U.T. L3 C9 L2 RF OUTPUT C1 L1 RF INPUT C6 C2 C7 C8 R2 C3 L1 — 3/4″, #18 AWG into Hairpin L2 — Printed Line, 0.200″ x 0.500″ L3 — 1″, #16 AWG into Hairpin L4 — 2 Turns, #16 AWG, 5/16 ID RFC1 — 5.6 µH, Choke RFC2 — VK200–4B R1 — 150 Ω, 1.0 W Carbon R2 — 10 kΩ, 1/2 W Carbon R3 — 120 Ω, 1/2 W Carbon Board Material — 0.062″ Fiberglass (G10), 1 oz. Copper Clad, 2 Sides, εr = 5.0 C1, C2, C8 — Arco 463 or equivalent C3 — 25 pF, Unelco C4 — 0.1 µF, Ceramic C5 — 1.0 µF, 15 WV Tantalum C6 — 15 pF, Unelco J101 C7 — 25 pF, Unelco J101 C9 — Arco 262 or equivalent C10 — 0.05 µF, Ceramic C11 — 15 µF, 60 WV Electrolytic D1 — 1N5347 Zener Diode Figure 2. 175 MHz Test Circuit VGS , DRAIN-SOURCE VOLTAGE (NORMALIZED) TYPICAL CHARACTERISTICS 1000 Ciss C, CAPACITANCE (pF) 500 Coss 200 100 50 Crss 20 0 0 10 20 30 40 VDS, DRAIN–SOURCE VOLTAGE (VOLTS) Figure 3. Capacitance versus Drain–Source Voltage REV 1 3 50 1.04 1.03 1.02 1.01 1 0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 0.91 0.9 – 25 1D = 5 A 4A 2A 1A 250 mA 0 100 mA 25 50 75 TC, CASE TEMPERATURE (°C) Figure 4. Gate–Source Voltage versus Case Temperature 100 TYPICAL CHARACTERISTICS 2000 f T, UNITY GAIN FREQUENCY (MHz) I D, DRAIN CURRENT (AMPS) 100 10 TC = 25°C 1 2 20 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS = 30 V VDS = 15 V 1000 0 200 0 Figure 5. DC Safe Operating Area 8 12 6 10 14 ID, DRAIN CURRENT (AMPS) Pout , OUTPUT POWER (WATTS) 20 15 VDD = 50 V IDQ = 250 mA Pout = 150 W 10 20 2 5 f = 175 MHz IDQ = 250 mA 100 0 0 5 10 15 10 30 f, FREQUENCY (MHz) 100 200 40 V f = 30 MHz IDQ = 250 mA 0 0 1 2 3 Pin, INPUT POWER (WATTS) IMD, INTERMODULATION DISTORTION d5 IDQ = 250 mA 55 VDD = 50 V, f = 30 MHz, TONE SEPARATION = 1 kHz 25 35 d3 55 d5 0 20 40 4 Figure 8. Output Power versus Input Power d3 45 25 VDD = 50 V 200 35 45 20 300 25 IDQ = 500 mA 60 100 120 140 160 80 Pout, OUTPUT POWER (WATTS PEP) Figure 9. IMD versus Pout 4 18 VDD = 50 V 200 100 Figure 7. Power Gain versus Frequency REV 1 16 300 25 GPS, POWER GAIN (dB) 4 Figure 6. Common Source Unity Gain Frequency versus Drain Current 30 5 2 180 200 5 150 f = 175 MHz 100 Zin 30 150 15 30 f = 175 MHz 100 15 7.5 7.5 Zo = 10 Ω ZOL* 4 VDD = 50 V IDQ = 250 mA Pout = 150 W 2 4 ZOL* = Conjugate of the optimum load impedance ZOL* = into which the device output operates at a ZOL* = given output power, voltage and frequency. 2 NOTE: Gate Shunted by 25 Ohms. Figure 10. Series Equivalent Impedance Table 1. Common Source S–Parameters (VDS = 50 V, ID = 2 A) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ |S11| 30 0.877 40 REV 1 5 S11 f MHz S21 φ S12 S22 |S21| φ |S12| φ |S22| φ –174 10.10 77 0.008 19 0.707 –169 0.886 –175 7.47 69 0.009 24 0.715 –172 50 0.895 –175 5.76 63 0.008 33 0.756 –171 60 0.902 –176 4.73 58 0.009 39 0.764 –171 70 0.912 –176 3.86 52 0.009 46 0.784 –172 80 0.918 –177 3.19 48 0.010 54 0.802 –171 90 0.925 –177 2.69 45 0.011 62 0.808 –171 100 0.932 –177 2.34 40 0.013 67 0.850 –173 110 0.936 –178 2.06 37 0.014 72 0.865 –175 120 0.942 –178 1.77 35 0.015 76 0.875 –173 130 0.946 –179 1.55 32 0.017 77 0.874 –172 140 0.950 –179 1.39 30 0.019 77 0.884 –174 150 0.954 –180 1.23 27 0.021 78 0.909 –175 160 0.957 –180 1.13 24 0.023 79 0.911 –176 170 0.960 180 1.01 22 0.024 82 0.904 –177 180 0.962 179 0.90 20 0.026 82 0.931 –176 190 0.964 179 0.84 19 0.028 80 0.929 –178 200 0.967 179 0.75 18 0.030 79 0.922 –179 210 0.967 178 0.71 16 0.032 80 0.937 –180 220 0.969 178 0.67 14 0.035 82 0.949 180 230 0.971 178 0.60 12 0.038 81 0.950 179 240 0.970 177 0.57 12 0.037 80 0.950 179 Table 1. Common Source S–Parameters (VDS = 50 V, ID = 2 A) continued S11 S21 S12 S22 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ f MHz |S11| φ |S21| φ |S12| φ |S22| φ 250 0.972 177 0.51 12 0.039 80 0.935 179 260 0.973 177 0.47 11 0.041 79 0.954 178 270 0.972 176 0.45 9 0.044 80 0.953 176 280 0.974 176 0.41 9 0.046 80 0.965 175 290 0.974 176 0.40 6 0.046 79 0.944 175 300 0.975 176 0.39 10 0.048 82 0.929 176 310 0.976 175 0.36 9 0.049 82 0.943 176 320 0.974 175 0.33 7 0.053 78 0.954 173 330 0.975 174 0.31 4 0.056 78 0.935 172 340 0.976 174 0.30 10 0.056 77 0.948 172 350 0.975 174 0.29 7 0.058 80 0.950 174 360 0.977 174 0.28 8 0.059 79 0.978 172 370 0.976 173 0.26 8 0.061 76 0.981 170 380 0.976 173 0.26 7 0.065 75 0.944 171 390 0.977 173 0.24 10 0.066 76 0.960 171 400 0.976 172 0.23 7 0.068 80 0.955 173 410 0.976 172 0.22 9 0.071 77 0.999 170 420 0.977 172 0.21 9 0.071 76 0.962 168 430 0.976 171 0.19 10 0.073 76 0.950 168 440 0.976 171 0.20 12 0.075 75 0.953 168 450 0.978 171 0.19 10 0.080 77 0.982 168 460 0.978 170 0.18 13 0.082 74 0.990 165 470 0.978 170 0.18 10 0.081 77 0.953 168 480 0.974 170 0.18 13 0.085 78 0.944 167 490 0.973 169 0.17 13 0.086 75 0.966 165 500 0.972 169 0.17 14 0.089 73 0.980 165 REV 1 6 RF POWER MOSFET CONSIDERATIONS MOSFET CAPACITANCES The physical structure of a MOSFET results in capacitors between the terminals. The metal anode gate structure determines the capacitors from gate–to–drain (Cgd), and gate– to–source (C gs ). The PN junction formed during the fabrication of the MOSFET results in a junction capacitance from drain–to–source (Cds). These capacitances are characterized as input (Ciss), output (Coss) and reverse transfer (Crss) capacitances on data sheets. The relationships between the inter–terminal capacitances and those given on data sheets are shown below. The Ciss can be specified in two ways: 1. Drain shorted to source and positive voltage at the gate. 2. Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case the numbers are lower. However, neither method represents the actual operating conditions in RF applications. DRAIN Cgd GATE Cds Cgs Ciss = Cgd = Cgs Coss = Cgd = Cds Crss = Cgd SOURCE LINEARITY AND GAIN CHARACTERISTICS In addition to the typical IMD and power gain data presented, Figure 6 may give the designer additional information on the capabilities of this device. The graph represents the small signal unity current gain frequency at a given drain current level. This is equivalent to fT for bipolar transistors. Since this test is performed at a fast sweep speed, heating of the device does not occur. Thus, in normal use, the higher temperatures may degrade these characteristics to some extent. DRAIN CHARACTERISTICS One figure of merit for a FET is its static resistance in the full–on condition. This on–resistance, VDS(on), occurs in the linear region of the output characteristic and is specified under specific test conditions for gate–source voltage and drain current. For MOSFETs, VDS(on) has a positive temperature coefficient and constitutes an important design consideration at high temperatures, because it contributes to the power dissipation within the device. GATE CHARACTERISTICS The gate of the MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The input resistance is very high — on the order of 109 ohms — resulting in a leakage current of a few nanoamperes. Gate control is achieved by applying a positive voltage slightly in excess of the gate–to–source threshold voltage, VGS(th). Gate Voltage Rating — Never exceed the gate voltage rating. Exceeding the rated VGS can result in permanent damage to the oxide layer in the gate region. Gate Termination — The gate of this device is essentially capacitor. Circuits that leave the gate open–circuited or floatREV 1 7 ing should be avoided. These conditions can result in turn– on of the device due to voltage build–up on the input capacitor due to leakage currents or pickup. Gate Protection — This device does not have an internal monolithic zener diode from gate–to–source. If gate protection is required, an external zener diode is recommended. Using a resistor to keep the gate–to–source impedance low also helps damp transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate–drain capacitance. If the gate–to–source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate–threshold voltage and turn the device on. HANDLING CONSIDERATIONS When shipping, the devices should be transported only in antistatic bags or conductive foam. Upon removal from the packaging, careful handling procedures should be adhered to. Those handling the devices should wear grounding straps and devices not in the antistatic packaging should be kept in metal tote bins. MOSFETs should be handled by the case and not by the leads, and when testing the device, all leads should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it is designed for, soldering should be done with a grounded iron. DESIGN CONSIDERATIONS The MRF151A is an RF Power, MOS, N–channel enhancement mode field–effect transistor (FET) designed for HF and VHF power amplifier applications. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. The major advantages of RF power MOSFETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal. DC BIAS The MRF151A is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain current flows when a positive voltage is applied to the gate. RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF151A was characterized at IDQ = 250 mA, each side, which is the suggested minimum value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate bias system. GAIN CONTROL Power output of the MRF151A may be controlled from its rated value down to zero (negative gain) by varying the dc gate voltage. This feature facilitates the design of manual gain control, AGC/ALC and modulation systems. PACKAGE DIMENSIONS A U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. M 1 M Q DIM A B C D E H J K M Q R U 4 R 2 B 3 D K J H C E SEATING PLANE CASE P-244 Specifications subject to change without notice. n North America: Tel. (800) 366-2266, Fax (800) 618-8883 n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298 n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020 Visit www.macom.com for additional data sheets and product information. REV 1 8 INCHES MIN MAX 0.960 0.990 0.465 0.510 0.229 0.275 0.216 0.235 0.084 0.110 0.144 0.178 0.003 0.007 0.435 ––– 45 _NOM 0.115 0.130 0.246 0.255 0.720 0.730 STYLE 2: PIN 1. 2. 3. 4. SOURCE GATE SOURCE DRAIN MILLIMETERS MIN MAX 24.39 25.14 11.82 12.95 5.82 6.98 5.49 5.96 2.14 2.79 3.66 4.52 0.08 0.17 11.05 ––– 45 _NOM 2.93 3.30 6.25 6.47 18.29 18.54