Order this document
by MRF136Y/D
SEMICONDUCTOR TECHNICAL DATA
The RF MOSFET Line
!
Designed for wideband large–signal amplifier and oscillator applications up to
400 MHz range, in either single ended or push–pull configuration.
• Guaranteed 28 Volt, 150 MHz Performance
Output Power = 30 Watts
Broadband Gain = 14 dB (Typ)
Efficiency = 54% (Typical)
30 W, to 400 MHz
N–CHANNEL
MOS BROADBAND
RF POWER FET
• Small–Signal and Large–Signal
Characterization
• 100% Tested For Load
Mismatch At All Phase
Angles With 30:1 VSWR
• Space Saving Package For
Push–Pull Circuit
Applications
• Excellent Thermal Stability,
Ideally Suited For Class A
Operation
'
"
CASE 319B–02, STYLE 1
• Facilitates Manual Gain
Control, ALC and
Modulation Techniques
MAXIMUM RATINGS
Rating
Symbol
Val e
Value
Unit
Drain–Source Voltage
VDSS
65
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
65
Vdc
VGS
±40
Vdc
Drain Current — Continuous
ID
5.0
Adc
Total Device Dissipation @ TC = 25°C
Derate above 25°C
PD
100
0.571
Watts
W/°C
Storage Temperature Range
Tstg
–65 to +150
°C
Operating Junction Temperature
TJ
200
°C
Symbol
Max
Unit
RθJC
1.75
°C/W
Gate–Source Voltage
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 0
1
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Drain–Source Breakdown Voltage
(VGS = 0, ID = 5.0 mA)
V(BR)DSS
65
—
—
Vdc
Zero–Gate Voltage Drain Current
(VDS = 28 V, VGS = 0)
IDSS
—
—
2.0
mAdc
Gate–Source Leakage Current
(VGS = 40 V, VDS = 0)
IGSS
—
—
1.0
µAdc
Gate Threshold Voltage
(VDS = 10 V, ID = 25 mA)
VGS(th)
1.0
3.0
6.0
Vdc
Forward Transconductance
(VDS = 10 V, ID = 250 mA)
gfs
250
400
—
mmhos
Input Capacitance
(VDS = 28 V, VGS = 0, f = 1.0 MHz)
Ciss
—
24
—
pF
Output Capacitance
(VDS = 28 V, VGS = 0, f = 1.0 MHz)
Coss
—
27
—
pF
Reverse Transfer Capacitance
(VDS = 28 V, VGS = 0, f = 1.0 MHz)
Crss
—
5.5
—
pF
Common Source Power Gain (Figure 1)
(VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA)
Gps
12
14
—
dB
Drain Efficiency (Figure 1)
(VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA)
η
50
54
—
%
Electrical Ruggedness (Figure 1)
(VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA,
VSWR 30:1 at all Phase Angles)
ψ
OFF CHARACTERISTICS (1)
ON CHARACTERISTICS (1)
DYNAMIC CHARACTERISTICS (1)
FUNCTIONAL CHARACTERISTICS (2)
NOTES:
1. Each side measured separately.
2. Measured in push–pull configuration.
REV 0
2
No Degradation in Output Power
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R5 — 56 kΩ, 1 W
R6 — 1.6 kΩ, 1/4 W
T1 — Primary Winding — 3 Turns #28 Enameled Wire.
T1 — Secondary Winding — 2 Turns #28 Enameled Wire.
T1 — Both windings wound through a Fair/Rite Balun 65 core.
T1 — Part #2865002402.
T2 — 1:1 Transformer Wound Bifilar — 2 Turns Twisted Pair
T1 — #24 Enameled Wire through a Indiana General Balun Q1
T1 — core. Part #18006–1–Q1. Primary winding center tapped.
Board Material — 0.062″ G10, 1 oz. Cu Clad, Double Sided
C1 — 5.0 pF
C2, C3, C4, C6, C7, C9, C11 — 0.1 µF Ceramic
C5, C8 — 680 pF Feedthru
C10 — 15 pF
D1 — 1N4740 Motorola Zener
RFC1 — 17 Turns, #24 AWG Wound on R5
RFC2 — Ferroxcube VK–200–19/4B or Equivalent
R1 — 10 kΩ, 1/4 W
R2, R3 — 560 Ω, 1/2 W
R4 — 10 Turns, 10 kΩ
Figure 1. 30–150 MHz Test Circuit
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Figure 2. Output Power versus Input Power
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Figure 3. Output Power versus Input Power
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Figure 4. Output Power versus Input Power
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Figure 8. Drain Current versus Gate Voltage
(Transfer Characteristics)*
REV 0
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Figure 7. Output Power versus Supply Voltage
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Figure 6. Output Power versus Supply Voltage
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Figure 5. Output Power versus Supply Voltage
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Figure 9. Gate–Source Voltage versus
Case Temperature*
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Figure 10. Capacitance versus Drain–Source Voltage
Figure 11. DC Safe Operating Area
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TYPICAL PERFORMANCE IN BROADBAND TEST CIRCUIT
(Refer to Figure 1)
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Figure 12. Output Power versus Input Power
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Figure 14. Drain Efficiency versus Frequency
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Figure 13. Power Gain versus Frequency
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% :
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Figure 15. Output Power versus Gate Voltage
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TYPICAL 400 MHz PERFORMANCE
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Figure 16. Output Power versus Input Power
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Figure 17. Output Power versus Gate Voltage
Zin & ZOL* are given
from drain–to–drain and
gate–to–gate respectively.
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3 !F
3
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Figure 18. Input and Output Impedance
REV 0
6
°
7
7
°
7
7
7
°
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7
°
°
°
7
7
°
°
°
7
Figure 19. S11, Input Reflection Coefficient
versus Frequency
VDS = 28 V ID = 0.5 A
Figure 20. S12, Reverse Transmission Coefficient
versus Frequency
VDS = 28 V ID = 0.5 A
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7
°
°
7
°
°
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7
°
°
°
°
7
7
3 !F
7
°
°
3 !F
7
7
7
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7
7
7
°
7
Figure 21. S21, Forward Transmission Coefficient
versus Frequency
VDS = 28 V ID = 0.5 A
Figure 22. S22, Output Reflection Coefficient
versus Frequency
VDS = 28 V ID = 0.5 A
REV 0
7
7
7
°
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7
3 !F
°
7
3 !F
°
DESIGN CONSIDERATIONS
The MRF136Y is an RF power N–Channel enhancement
mode field–effect transistor (FET) designed especially for HF
and VHF power amplifier applications. M/A-COM RF MOS
FETs feature planar design for optimum manufacturability.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high gain,
low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control signal,
thus facilitating manual gain control, ALC and modulation.
DC BIAS
The MRF136Y is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied without
gate bias. A positive gate voltage causes drain current to flow
(see Figure 8). RF power FETs require forward bias for
optimum gain and power output. A Class AB condition with
quiescent drain current (IDQ) in the 25–100 mA range is
sufficient for many applications. For special requirements
such as linear amplification, IDQ may have to be adjusted to
optimize the critical parameters.
The MOS gate is a dc open circuit. Since the gate bias circuit
does not have to deliver any current to the FET, a simple
resistive divider arrangement may sometimes suffice for this
function. Special applications may require more elaborate
gate bias systems.
GAIN CONTROL
Power output of the MRF136Y may be controlled from rated
values down to the milliwatt region (>20 dB reduction in power
output with constant input power) by varying the dc gate
REV 0
8
voltage. This feature, not available in bipolar RF power
devices, facilitates the incorporation of manual gain control,
AGC/ALC and modulation schemes into system designs. A
full range of power output control may require dc gate voltage
excursions into the negative region.
AMPLIFIER DESIGN
Impedance matching networks similar to those used with
bipolar transistors are suitable for the MRF136Y. See
M/A-COM Application Note AN721, Impedance Matching
Networks Applied to RF Power Transistors. Large signal
impedance parameters are provided. Large signal impedances should be used for network designs wherever possible.
While the s parameters will not produce an exact design
solution for high power operation, they do yield a good first
approximation. This is particularly useful at frequencies
outside those presented in the large signal impedance plots.
RF power FETs are triode devices and are therefore not
unilateral. This, coupled with the very high gain, yields a
device capable of self oscillation. Stability may be achieved
using techniques such as drain loading, input shunt resistive
loading, or feedback. S parameter stability analysis can
provide useful information in the selection of loading and/or
feedback to insure stable operation. The MRF136Y was
characterized with a resistive feedback loop around each of its
two active devices.
For further discussion of RF amplifier stability and the use
of two port parameters in RF amplifier design, see M/A-COM
Application Note AN215A.
LOW NOISE OPERATION
Input resistive loading will degrade noise performance, and
noise figure may vary significantly with gate driving impedance. A low loss input matching network with its gate
impedance optimized for lowest noise is recommended.
PACKAGE DIMENSIONS
–A–
L
IDENTIFICATION
NOTCH
Q 2 PL
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D
F 4 PL
B
J
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CASE 319B–02
ISSUE C
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
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