HD74LS221 Dual Monostable Multivibrators REJ03D0458–0300 Rev.3.00 Jul.15.2005 This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity of typically 1.2 V. A high immunity to VCC noise of typically 1.5 V is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration relative to the output pulse. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequence are illustrated as a part of the switching characteristics waveforms. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC range for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 100 kΩ). Throughout these ranges, pulse width is defined by the relationship: tw (out) = Cext • Rext • 1n 2. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS221P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74LS221RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.3.00, Jul.15.2005, page 1 of 8 HD74LS221 Pin Arrangement 1A 1 16 VCC 1B 2 15 1 Rext/Cext 1CLR 3 14 1 Cext 13 1Q 12 2Q 11 2CLR 1Q 4 2Q 5 CLR Q Q Q Q 2 Cext 6 2 Rext/Cext 7 10 2B GND 8 9 2A CLR (Top view) Function Table Inputs Clear A L X X H X X H L H ↓ ↑ L Notes: H; high level, L; low level, X; irrelevant. ↓; Transition from high to low level. ↑; Transition from low to high level. ; one high-level pulse. ; one low-level pulse. Outputs B X X L ↑ H H Q H H H Q L L L Block Diagram (1/2) A B Clear Rev.3.00, Jul.15.2005, page 2 of 8 Q Q Q Clear Q HD74LS221 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C 1 — — V/s V/µs Supply voltage Output current Operating temperature Rate of rise or fall of input pulse Schmitt input, B dV/dt 1 — — A or B tw (in) 40 — — Clear tw (clear) 40 — — tsu 15 — — ns External timing resistance Rext 1.4 — 100 kΩ External timing capacitance Cext 0 — 1000 µF Input pulse width Logic Input, A Setup time Duty cycle RT = 2 kΩ — — 50 RT = 100 kΩ — — 90 ns Electrical Characteristics (Ta = –20 to +75 °C) Item A Threshold voltage B Symbol VT+ VT– VT+ Output voltage – VT VOH VOL IIH Input current A B, Clear IIL min. — 0.8 — 0.8 2.7 — typ.* 1.0 1.0 1.0 0.9 — — max. 2.0 — 2.0 — — 0.4 — — — — — — 0.5 20 –0.4 — — –0.8 0.1 II — — Short-circuit output current IOS –20 — –100 Supply current ICC — 4.7 11 Input clamp voltage VIK — — 19 — 27 –1.5 Note: * VCC = 5 V, Ta = 25°C Rev.3.00, Jul.15.2005, page 3 of 8 Unit V V V V V µA Condition VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V VCC = 4.75 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V mA VCC = 5.25 V, VI = 0.4 V mA VCC = 5.25 V, VI = 7 V mA VCC = 5.25 V V mA V Ouiescent VCC = 5.25 V Triggered VCC = 4.75 V, IIN = –18 mA HD74LS221 Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol tPLH Propagation delay time tPHL tPHL tPLH Output pulse width Inputs A B A B Clear Clear tw (out) A or B Outputs Q Q Q Q Q Q min. — — — — — — typ. 45 35 50 40 35 44 max. 70 55 80 65 55 65 70 120 150 20 47 70 600 670 750 6 6.7 7.5 Unit Condition ns Cext = 80 pF, Rext = 2 kΩ ns ns ns Cext = 80 pF, Rext = 2 kΩ CL = 15 pF, RL = 2 kΩ Cext = 0 pF, Rext = 2 kΩ ns Q or Q Cext = 100 pF, Rext = 10 kΩ ms Cext = 1 µF, Rext = 10 kΩ Caution in use In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible. Testing Method Test Circuit VCC + A Input – Cext P.G. Zout = 50Ω Rext Load circuit 1 RL A Cext Rext /Cext Q CL B Input P.G. Zout = 50Ω B CLR Input CLR P.G. Zout = 50Ω Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Rev.3.00, Jul.15.2005, page 4 of 8 Q Same as Load Circuit 1. HD74LS221 Waveforms 1 Trigger from B, then clear (A input is low). tTLH tTHL tw (in) 3V B Input 10% 90% 1.3V 90% 1.3V 10% 0V ≥ 60ns 3V CLR 1.3V 0V tPLH tPHL 3V Q 1.3V 1.3V 0V tPHL tPLH VOH Q 1.3V 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Waveforms 2 Trigger from A, then clear (B input is high). tTLH tTHL tw (in) A 90% 1.3V 10% 3V 10% 90% 1.3V 0V ≥ 60ns 3V CLR 1.3V 0V tPLH tPHL VOH Q 1.3V 1.3V VOL tPLH VOH Q 1.3V tPHL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Rev.3.00, Jul.15.2005, page 5 of 8 1.3V VOL HD74LS221 Waveforms 3 Trigger from B, then clear (A input is low). tTLH tTHL 3V B Input 10% 90% 1.3V 90% 10% 0V ≥ 60ns 3V CLR 1.3V 0V VOH Q VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Waveforms 4 Trigger from A (B and clear input are high). tTHL tTLH 3V A 90% 90% 10% 10% 0V 3V Q 1.3V tw (out) 1.3V 0V tw (out) Q 1.3V VOH 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Rev.3.00, Jul.15.2005, page 6 of 8 HD74LS221 Waveforms 5 Clear overriding B, then trigger from B. tTLH tTHL 3V 90% 90% 1.3V 1.3V 10% B Input 1.3V 10% 0V ≥ 50ns tsu ≥ 0ns CLR 1.3V 3V 1.3V 0V Triggered VOH Q 1.3V 1.3V VOL Not Triggered Note: tw (out) Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Waveforms 6 Positive transition of Clear. tTLH tTHL 3V B Input 10% ≥ 50ns 90% 1.3V 90% 1.3V 10% 0V ≥ 50ns 3V CLR 1.3V 1.3V 0V VOH Q VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Rev.3.00, Jul.15.2005, page 7 of 8 HD74LS221 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A θ bp e Dimension in Millimeters Min 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 8 1 Z e *3 bp x A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 1.75 A M L1 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 e 1.27 x 0.25 y 0.15 0.635 Z 0.40 L L Rev.3.00, Jul.15.2005, page 8 of 8 8° 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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