DRV604 www.ti.com SLOS659 – JANUARY 2010 DirectPath™ 2Vrms Line Driver and HP Amp With Adjustable Gain Check for Samples: DRV604 FEATURES APPLICATIONS • • • • • 1 23 • • • • • • • • • • DirectPath™ – Eliminates Pop/Clicks – Eliminate Output DC-Blocking Capacitors 3.0V to 3.7V Supply Voltage Low Noise and THD – SNR > 109dB – Typical Vn < 7µVrms 20–20kHz – THD+N < 0.002% at 10kΩ Output Voltage into 5kΩ Load – 2Vrms at 3.3V Supply Voltage Stereo DirectPath™ Headphone: – 40mW into 32Ω at 3.3V Supply Voltage – 16Ω to ∞ Ω Stable Load Range Differential Input Power Sense UVP for Brown Out Protection Short Circuit and Thermal Protection ±8kV IEC ESD Protection Footprint Compatible with DRV602 and DRV603 Supports Dual Line Driver Configuration - DAC + RIGHT Line Driver LEFT - DAC + DRV604 SOC - Headphone DAC + LCD and PDP TV Blu-ray Disc™, DVD Players Mini/Micro Combo Systems Soundcards DESCRIPTION The DRV604 is a 2Vrms Pop-Free stereo line driver with stereo headphone output designed to allow the removal of the output DC-blocking capacitors for reduced component count and cost. The device is ideal for single supply electronics where size and cost are critical design parameters. Designed using TI’s patented DirectPath™ technology, The DRV604 is capable of driving 2 Vrms into a 5kΩ load. The headphone output can generate a clean 40mW into 32Ω load from a 3.3V supply.. The device has differential inputs and uses external gain setting resistors that supports a gain range of -1V/V to -10V/V. Headphone and line outputs have ±8kV IEC ESD protection enabling a simple ESD protection circuit. The DRV604 has built-in enable control for pop-free on/off control. DRV604 can monitor an external supply voltage using its built in comparator enabling it to shut down during a brown out condition before up stream audio DAC’s can produce click and pop artifacts. Using the DRV604 in audio products can reduce component count considerably compared to traditional methods of generating headphone output and 2Vrms output. The DRV604 does not require a power supply greater than 3.3V to generate its 5.6Vpp output, nor does it require a split rail power supply. The DRV604 integrates its own charge pump to generate a negative supply rail that provides a clean, pop-free ground biased 2Vrms output. The DRV604 is available in a 28-pin HTSSOP. For a stereo line driver with no HP amp see DRV603. - DAC + 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath, FilterPro are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated DRV604 SLOS659 – JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION PIN ASSIGNMENT The DRV604 is available in the thermally enhanced package: 28-Pin HTSSOP package (PWP). 1 +LD_L +LD_R 28 2 -LD_L -LD_R 27 3 OUT_LDL OUT_LDR 26 4 AGND Ex_UVP 25 5 EN_LD PGND 24 6 PVSS_LD PVDD_LD 23 7 CN_LD CP_LD 22 8 CN_HP CP_HP 21 9 PVSS_HP PVDD_ HP 20 10 EN_HP PGND 19 11 AGND NC 18 12 OUT_HPL OUT_HPR 17 13 -HP_L -HP_R 16 14 +HP_L +HP_R 15 PIN FUNCTIONS PIN FUNCTION (1) DESCRIPTION NAME PWP NO. +LD_L 1 I Positive input, Line driver Left –LD_L 2 I Negative input, Line driver Left OUT_LDL 3 O Output, Line driver Left AGND 4 P Analog Ground EN_LD 5 I Enable for Line driver, active high PVSS_LD 6 O Charge Pump Negative Supply Voltage Output for Line Driver CN_LD 7 I/O Charge Pump Flying Capacitor Negative connection, Line Driver CN_HP 8 I/O Charge Pump Flying Capacitor Negative connection, Headphone PVSS_HP 9 O Headphone, Charge Pump Negative Supply Voltage Output EN_HP 10 I Enable for Headphone, active high AGND 11 P Analog Ground OUT_HPL 12 O Output, Headphone Left –HP_L 13 I Negative input, Headphone Left +HP_L 14 I Positive input, Headphone Left +HP_R 15 I Positive input, Headphone Right (1) 2 I = input, O = output, P = power Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 PIN FUNCTIONS (continued) PIN FUNCTION (1) DESCRIPTION NAME PWP NO. –HP_R 16 I Negative input, Headphone Right OUT_HPR 17 O Output, Headphone Right NC 18 PGND 19 P Charge Pump Power Ground, Headphone PVDD_HP 20 P Headphone Supply Voltage, connect to positive supply, internally connected to pin 23 CP_HP 21 I/O Charge Pump Flying Capacitor Positive connection, Headphone CP_LD 22 I/O Charge Pump Flying Capacitor Positive connection, Line Driver PVDD_LD 23 P Line Driver Supply Voltage, connect to positive supply, internally connected to pin 20 PGND 24 P Charge Pump Power Ground, Line Driver Ex_UVP 25 I External Under Voltage Protection OUT_LDR 26 O Output, Line Driver Right –LD_R 27 I Negative input, Line driver Right +LD_R 28 I Positive input, Line driver Right No connect SYSTEM BLOCK DIAGRAM Short-Circuit Protection OpAmp LD OpAmp LD Click & Pop Suppression Charge Pump LD Enable Control LD Internal UVP Thermal Protection External UVP Charge Pump HP Enable Control HP Click & Pop Suppression OpAmp HP OpAmp HP Short-Circuit Protection ORDERING INFORMATION (1) (1) TA PACKAGE DESCRIPTION –40°C–85°C DRV604PWP 28-Pin For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 3 DRV604 SLOS659 – JANUARY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PVDD to GND Input voltage, VI DRV604PWP UNIT –0.3 to 4.5 V PVSS–0.3 to PVDD+0.3 V 1000 Ω Minimum load impedance – line outputs 8 Ω EN_LD to GND –0.3 to PVDD+0.3 V EN_HP to GND –0.3 to PVDD+0.3 V Maximum operating junction temperature range, TJ –40 to 150 °C Storage temperature –40 to 150 °C Minimum load impedance – headphone outputs (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) PACKAGE RqJP(°C/W) RqJA(°C/W) RyJT(°C/W) DRV604PWP 0.72 28 0.45 (1) PowerPAD soldered to TI recommended board. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PVDD Power supply RL (HP) RL (LD) DC supply voltage Load impedance MIN NOM MAX 3.0 3.3 3.7 32 32 UNIT V Ω 5 10 VIL Low level input voltage EN_LD, EN_HP 38 40 43 %PVDD VIH High level input voltage EN_LD, EN_HP 57 60 66 %PVDD TA Free-air temperature –40 25 85 °C 4 Submit Documentation Feedback kΩ Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 ELECTRICAL CHARACTERISTICS PVDD_LD = PVDD_HP = 3.3 V, RLD = 5 kΩ, RHP = 32 Ω, RFB = 20 kΩ, RIN = 10 kΩ, TA = 25°C, Charge pump: CCP_LD = CCP_HP = 1.0 µF (unless otherwise noted) PARAMETER DRV604 TEST CONDITIONS MIN TYP 70 80 Output offset voltage PSRR Power supply rejection ratio VOH High level output voltage PVDD = 3.3 V VOL Low level output voltage PVDD = 3.3 V Vuvp_on PVDD, undervoltage detection Internal under-voltage detection. Vuvp_hysteresis PVDD, undervoltage detection, hysteresis 200 mV Vuvp External undervoltage detection 1.25 V IHys External undervoltage detection hysteresis current 5 µA Fcp Charge pump switching frequency 700 kHz |IIH| High level input current PVDD = 3.3 V, VIH = PVDD, EN_HP, EN_LD 1 µA |IIL| low level input current PVDD = 3.3 V, VIL = 0 V, EN_HP, EN_LD 1 µA Supply current, no load PVDD, EN_LD, EN_HP = 3.3 V Supply current, line driver, no load PVDD, EN_LD = 3.3 V, EN_HP = GND 12 Supply current, headphone, no load PVDD, EN_LD = GND, EN_HP = 3.3 V 13 Supply current, disabled PVDD = 3.3 V, EN_LD, EN_HP = GND, Ex_UVP = GND 2.5 Tsd 1 UNIT |Vos| I(PVDD) PVDD = 3.3 V MAX dB 3.1 V 260 15 Thermal shutdown Thermal shutdown hysteresis mV 25 –3.05 V 2.8 V 35 mA 5 150 °C 15 °C ELECTRICAL CHARACTERISTICS, LINE DRIVER PVDD_LD = PVDD_HP = 3.3 V, Rload = 5 kΩ, RFB = 20 kΩ, RIN = 10 kΩ, TA = 25°C, Charge pump: CCP_LD = CCP_HP = 1.0 µF (unless otherwise noted) DRV604 PARAMETER TEST CONDITIONS MIN TYP MAX VO Output voltage, outputs in phase 1% THD+N, f = 1 kHz, 10 kΩ load THD+N Total harmonic distortion plus noise f = 1 kHz, 10 kΩ load, VO = 2 Vrms SNR Signal-to-noise ratio A-weighted, AES17 filter, 2 Vrms ref 109 dB DNR Dynamic range A-weighted, AES17 filter, 2 Vrms ref 109 dB Vn Noise voltage A-weighted, AES17 filter Slew rate GBW Unity gain bandwidth Crosstalk – Line L-R & R-L 10 kΩ load, VO = 2 Vrms 2.1 UNIT 0.001% 7 V/µS 8 MHz -100 dB V Positive common-mode input voltage +2.0 Vincm_neg Negative common-mode input voltage -3.0 Ilimit Current limit Maximum capacitive load Product Folder Link(s) :DRV604 V 60 mA 220 pF Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated uV 4.5 Vincm_pos PVDD = 3.3 V Vrms 5 DRV604 SLOS659 – JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS, HEADPHONE PVDD_LD = PVDD_HP = 3.3 V, RHP = 32 Ω, TA = 25°C, Charge pump: CCP_LD = CCP_HP = 1.0 µF (unless otherwise noted) PARAMETER TAS5630 TEST CONDITIONS MIN TYP MAX UNIT PO Output power, outputs in phase THD+N = 1%, f = 1 kHz, 32 Ω load 40 mW VO Output voltage, outputs in phase THD+N = 1%, f = 1 kHz, 32 Ω load 1.45 Vrms THD+N Total harmonic distortion plus noise SNR Signal-to-noise ratio DNR Dynamic range Vn Noise voltage f = 1 kHz, 32 Ω load, PO = 40 mW 0.02% f = 1 kHz, 5 kΩ load, VO = 2 Vrms 0.001% A-weighted, AES17 filter, 1.45 Vrms ref (66 mW into 32 Ω) 106 A-weighted, AES17 filter, 2 Vrms ref 5 kΩ load 109 A-weighted, AES17 filter, 1.45 Vrms ref (66 mW into 32 Ω) 106 A-weighted, AES17 filter, 2 Vrms ref 5 kΩ load 109 A-weighted, AES17 filter Slew rate GBW Unity gain bandwidth Crosstalk Channel to channel Vincm_pos Positive common-mode input voltage Vincm_neg Ilimit 6 7 dB dB µV 4.5 V/µS 8 MHz 75 dB 2.0 V Negative common-mode input voltage –3.0 V Output current limit 190 mA Maximum capacitive load 220 pF f = 1 kHz, Rload = 32 Ω, PO = 40 mW Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 TYPICAL CHARACTERISTICS, LINE DRIVER THD+N vs OUTPUT VOLTAGE THD+N vs OUTPUT VOLTAGE, LINEAR SCALE 10 10 Load = 5 kW to 100 kW, Output in Phase = 1 kHz 1 0.1 0.01 0.001 0.0001 40m VI = 3.3 V, THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % VI = 3.3 V, Load = 5 kW, Linear Scale = 1 kHz, Outputs in Phase = 1 kHz 1 0.1 0.01 0.001 0.0001 100m 200m 500m 1 VO - Output Voltage - V 2 1 4 1.5 2 VO - Output Voltage - V Figure 1. 3 Figure 2. THD+N vs FREQUENCY CHANNEL SEPARATION 0 10 VI = 3.3 V, THD+N - Total Harmonic Distortion + Noise - % 2.5 VI = 3.3 V, Load = 5 kW, 2 Vrms -20 Load = 5 kW, 2 Vrms 1 Amplitude - dBr -40 0.1 0.01 -60 -80 L to R R to L -100 0.001 -120 0.0001 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 20 20k 50 100 Figure 3. 200 500 1k 2k f - Frequency - Hz 5k 20k Figure 4. HP TO LD CROSSTALK AC PSRR, Ksvr 0 0 VI = 3.3 V, Line Load = 5 kW, 32 W HP Load, 40 mW 200 mV Vpp supply ripple = 70 mV Vrms -20 Amplitude - dBr Amplitude - dBr -20 -40 -60 HP to line left -40 VI = 3.3 V, 200 mV Vpp Ripple on PSU, Line Load = 5 kW, 32 W HP Load Amplifier output - relative to 70 mV -60 HP to line right -80 -80 -100 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 20k -100 20 Figure 5. 50 100 200 500 1k 2k f - Frequency - Hz 5k 20k Figure 6. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 7 DRV604 SLOS659 – JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS, HEADPHONE THD+N vs OUTPUT POWER THD+N vs OUTPUT POWER, LINEAR SCALE 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 3.3 V, 32W, 1 kHz In phase 1 Out of phase 0.1 0.01 3.3 V, 32W, 1 kHz In phase Out of phase 1 0.1 0.01 0.001 0.001 100u 5m 10m 2m PO - Output Power - W 500u 50m 50 100 PO - Output Power - mW 200m Figure 7. Figure 8. CHANNEL SEPARATION LD TO HP CROSSTALK 0 0 3.3 V, LD 2 Vrms into 5 kW, 32 W HP Load No Signal 40 mW into 32W -20 Amplitude - dBr Amplitude - dBr -20 -40 -60 -80 -100 20 8 150 -40 -60 -80 -100 50 100 200 500 1k 2k f - Frequency - Hz 5k 20k -120 20 50 100 200 500 1k 2k f - Frequency - Hz Figure 9. Figure 10. START STOP Figure 11. Figure 12. Submit Documentation Feedback 5k 20k Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 13 illustrates the conventional line driver amplifier connection to the load and output signal. DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal. Conventional Solution 9-12 V VDD + Mute Circuit Co + + OPAMP Output VDD/2 GND MUTE DRV604 Solution 3.3 V DirectPath VDD + Mute Circuit DRV604 Output GND VSS MUTE Figure 13. Conventional and DirectPath HP and Line Driver The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail, combining this with the build in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 13 illustrate the ground-referenced headphone and line driver architecture. This is the architecture of the DRV604. COMPONENT SELECTION Charge Pump The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that are smaller than 1µF can not be recommended for the HP section as it will limit the negative voltage swing in low impedance loads. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 9 DRV604 SLOS659 – JANUARY 2010 www.ti.com Decoupling Capacitors The DRV604 is a DirectPath™ amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device PVDD leads works best. Placing this decoupling capacitor close to the DRV604 is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Gain Setting Resistors Ranges The gain setting resistors, Rin and Rfb, must be chosen so that noise, stability and input capacitor size of the DRV604 is kept within acceptable limits. Voltage gain is defined as Rfb divided by Rin. Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different gain settings. Table 1. Recommended Resistor Values INPUT RESISTOR VALUE, Rin FEEDBACK RESISTOR VALUE, Rfb DIFFERENTIAL INPUT GAIN INVERTING INPUT GAIN NON INVERTING INPUT GAIN 10 kΩ 10 kΩ 1.0 V/V –1.0 V/V 2.0 V/V 10 kΩ 15 kΩ 1.5 V/V –1.5 V/V 2.5 V/V 10 kΩ 20 kΩ 2.0 V/V –2.0 V/V 3.0 V/V 4.7 kΩ 47 kΩ 10.0 V/V –10.0 V/V 11.0 V/V Cin Cin Rin - In Rin - In Rfb Rfb - Differential Input Inverting + + + In Cin Rin Rfb Cx Rin Rfb - Non Inverting + + In Cin Rx Figure 14. Differential, Inverting and Non-inverting Gain Configuration Internal and External Under Voltage Detection and RESET Output The DRV604 contains an internal precision band gap reference voltage and 2 comparators, one is used to monitor the supply voltages, PVDD_LD and PVDD_HP, and the other to monitor an external user selectable voltage on pin 25. The internal PVDD monitor is set at 2.8 V with 200 mV hysteresis. The external under voltage detection can be used to shutdown the DRV604 before an input device can make a pop. The shutdown threshold at the Ex_UVP pin is 1.25 V. A resistor divider is used to obtain the shutdown threshold and hysteresis desired for the application. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 Comparator Ex_UVP 25 AMP Enable 1.25 V Bandgap PVDD_LD 23 PVDD_HP 20 Comparator Internal PVDD The selected thresholds can be determined as follows: (R11 + R12 ) VUVP = 1.25 V ´ R12 (1) æ R11 ö VHysteresis = 5 μA × R13 × ç +1÷ è R12 ø (2) With the condition R13 >> R11||R12 For example, to obtain VUVP = 4.5 V and 400 mV hysteresis, use R11 = 10 kΩ, R12 = 3 kΩ and R13 = 22kΩ. To filter supply spikes and noise a capacitor across R12 can be added. External Sense Voltage DRV604 5 mA R11 R13 Comparator Ex_UVP 25 R12 1.25 V Bandgap Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV604. These capacitors block the DC portion of the audio source and allow the DRV604 inputs to be properly biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the DC-offset voltage at the output. These capacitors form a high-pass filter with the input resistor, Rin. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input resistor chosen from Table 1, then the frequency and/or capacitance can be determined when one of the two values are given. 1 1 fc in = Cin = 2p ´ Rin ´ Cin 2p ´ fc in ´ Rin (3) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 11 DRV604 SLOS659 – JANUARY 2010 www.ti.com Using the DRV604 as a 2nd order filter Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible with the DRV604 as it can be used like a standard OPAMP. Several filter topologies can be implemented both single ended and differential. In the figure below a Multi Feed Back (MFB), with differential input and single ended input is shown. An AC-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum. The component values can be calculated with the help of the TI FilterPro™ program available on the TI website at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html Inverting Input Differential Input R2 C3 R1 R2 C3 C1 R3 R1 R3 C1 - In - In DRV604 + C2 DRV604 + C2 + In C3 R1 R3 C1 R2 Figure 15. 2nd Order Active Low Pass Filter The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small size ac-coupling cap. C2 can be split in two with the midpoint connected to GND, this can increase the common-mode attenuation. Pop-Free Power Up Pop-free power up is ensured by keeping the EN_LD and EN_HP and/or Ex_UVP low during power supply ramp up and down. The pins should be kept low until the input AC-coupling capacitors are fully charged before asserting the EN_xx pins high, this way proper pre-charge of the ac-coupling is performed and pop-less power-up is achieved. Figure 16 illustrates the preferred sequence. Supply Supply Ramp EN_xx Time for ac-coupling capacitors to charge Figure 16. Power-Up/Down Sequence 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 DRV604 www.ti.com SLOS659 – JANUARY 2010 Dual Stereo Line Driver The DRV604 Headphone stereo amplifier can also be used as Line Driver and has the same high output voltage capability as the Line amp when driving 5kΩ load impedances. This makes the DRV604 ideal for applications like dual SCART outputs on LCD TV, or for multiple line outputs like in DVD or Blue-Ray players where 2x DRV604 can give a very space effective solution for a 8ch line output. Capacitive Load The DRV604 has the ability to drive a high capacitive load up to 220pF directly, higher capacitive loads can be accepted by adding an output series resistor of 47Ω or larger for the line driver output. Layout Recommendations A proposed layout for the DRV604 can be seen in the DRV604EVM user's guide, SLOU288, and the Gerber files can be downloaded on www.ti.com, open the DRV604 product folder and look in the Tools and Software folder. The gain setting resistors, Rin and Rfb, must be placed close to the input pins to minimize the capacitive loading on these input pins and to ensure maximum stability of the DRV604. Ground traces are recommended to be routed as a star ground to minimize hum interference. PVDD, PVSS decoupling capacitors and the charge pump capacitors should be connected with short traces. Footprint Compatible with the DRV603 The DRV604 stereo line driver section is pin compatible with the DRV603. A single PCB layout can therefore be used with stuffing options for different output configurations. 1 DRV604 DRV603 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 13 DRV604 SLOS659 – JANUARY 2010 www.ti.com APPLICATION CIRCUIT C11 C1 2 2 2 28 2 33.0k 2 -LD_R -LD_L 27 C13 3 2 1 2 33.0k C16 22pF OUT_LDL OUT_LDR 26 1 330pF R16 GND 2 1 1 +LD_R GND 1 R12 33.0k +LD_L R15 33.0k 22pF LD_L_OUT 1 2 330pF R13 1 LD_L_IN R14 10.0k C15 2 1 1 C12 1 1 10uF U1 2 R11 10.0k LD_L_OUT C14 1 1uF 2 10uF 2 2 1 1 LD_L_IN R3 Ex_UVP AGND 25 1 VSUP 2 2 4 R1 22k GND 1 2 6 PVSS_LD PVDD_LD 23 GND C9 470pF 2 1 R2 3.90k 2 C5 1uF C3 2 PGND EN_LD 24 11 10k 5 1 EN_LD 1uF GND CP_LD CN_HP CP_HP 22 GND 21 C4 PVDD_HP PVSS_HP 20 C6 1uF 1uF GND 10 PGND EN_HP 19 2 EN_HP 1R C7 10uF C8 1uF 2 9 1 2 2 1 1 +3.3V R4 2 1 8 CN_LD 1 7 GND GND GND 11 18 C21 1 1 2 R25 30.0k R26 2 1 2 -HP_L 16 33.0k C25 14 +HP_R +HP_L 15 1 2 2 1 C22 330pF -HP_R R23 330pF GND 1 R21 10.0k HP_R_OUT C26 22pF 2 2 17 2 10uF R24 10.0k GND PDRV604 C2 1 1 33.0k 13 OUT_HPR OUT_HPL 1 C23 22pF 2 1 2 1 2 30.0k R22 12 1 GND HP_L_OUT HP_L_IN NC AGND 2 2.2uF C24 2 1 HP_R_IN 10uF Single-Ended Input and Output with 3.3x Gain in the Line Section, 3x Gain in the Headphone Section. AC-Coupling Input with a High Pass Pole of 1.6Hz, 2nd Order Low Pass Filter at 50kHz. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :DRV604 PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV604PWP ACTIVE HTSSOP PWP 28 DRV604PWPR ACTIVE HTSSOP PWP 28 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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