STB80NF03L-04 N-CHANNEL 30V - 0.0035 Ω - 80A TO-262/TO-263 STripFET POWER MOSFET PRELIMINARY DATA T YPE V DSS R DS(on) ID STB80NF03L-04 30 V < 0.004 Ω 80 A ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.0035 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW THRESHOLD DRIVE THROUGH-HOLE I2PAK (TO-262) POWER PACKAGE IN TUBE (SUFFIX ”-1”) SURFACE-MOUNTING D2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX ”T4”) 3 3 12 DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique ”Single Feature Size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 1 I2PAK TO-262 (suffix ”-1”) D2PAK TO-263 (suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc. ) ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS Value Un it Drain-source Voltage (VGS = 0) Parameter 30 V Drain- gate Voltage (R GS = 20 kΩ) 30 V ± 20 V G ate-source Voltage o ID Drain Current (continuous) at Tc = 25 C 80 A ID Drain Current (continuous) at Tc = 100 C o 56 A Drain Current (pulsed) 320 A T otal Dissipation at Tc = 25 C 210 W Derating Factor 1.43 W /o C Peak Diode Recovery voltage slope 3.5 V/ns I DM (•) P tot dv/dt Ts tg Tj o Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area March 2000 -65 to 175 o C 175 o C ( 1) ISD ≤ 80 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/7 STB80NF03L-04 THERMAL DATA R thj -case Rthj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose o 0.7 62.5 0.5 300 C/W oC/W o C/W o C Max Value Unit AVALANCHE CHARACTERISTICS Symbo l Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 80 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 15 V) 600 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 30 Unit V 1 10 µA µA ± 100 nA Typ. Max. Unit 1.5 2.5 T c =125 oC V GS = ± 20 V ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 10V ID = 40 A V GS = 4.5V I D = 40 A I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 1 0.0035 0.004 0.004 0.0055 80 V Ω Ω A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/7 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =15 A V GS = 0 Min. Typ. Max. Unit 20 50 S 7000 1700 600 pF pF pF STB80NF03L-04 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 15 V I D = 40 A R G = 4.7 Ω V GS = 4.5 V (Resistive Load, see fig. 3) 50 230 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 24 V ID = 80 A V GS = 4.5 V 100 22 42 135 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbo l Parameter Test Con ditions Min. t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 15 V I D = 40 A V GS = 4.5 V R G = 4.7 Ω (Resistive Load, see fig. 3) 220 130 ns ns tr (Voff) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time V clamp = 24 V I D = 80 A V GS = 4.5 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 65 250 340 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 80 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 80 A di/dt = 100 A/µs T j = 150 o C V DD = 15 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 80 320 A A 1.5 V 70 ns 0.14 µC 4 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area 3/7 STB80NF03L-04 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/7 STB80NF03L-04 TO-262 (I2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 E 10 10.4 0.393 0.409 L 13.1 13.6 0.515 0.531 L1 3.48 3.78 0.137 0.149 L2 1.27 1.4 0.050 0.055 E e B B2 C2 A1 A C A L1 L2 D L P011P5/E 5/7 STB80NF03L-04 TO-263 (D2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.21 1.36 0.047 0.053 D 8.95 9.35 0.352 0.368 E 10 10.4 0.393 0.409 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.624 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 D C2 A2 A C DETAIL”A” DETAIL ”A” A1 B2 E B G L2 L L3 P011P6/E 6/7 STB80NF03L-04 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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