STMICROELECTRONICS SPC56AP54L5

SPC56AP60x, SPC56AP54x
SPC560P60x, SPC560P54x
32-bit Power Architecture® based MCU with 1088 KB Flash memory
and 80 KB RAM for automotive chassis and safety applications
Datasheet  production data
Features
■
64 MHz, dual issue, 32-bit CPU core complex
(e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
■
Memory organizazion
– Up to 1024 KB on-chip code Flash memory
with additional 64 KB for EEPROM
emulation (data flash), with ECC, with
erase/program controller
– Up to 80 KB on-chip SRAM with ECC
■
Fail safe protection
– ECC protection on system SRAM and
Flash
– Safety port
– SWT with servicing sequence pseudorandom generator
– Power management
– Non-maskable interrupt for both cores
– Fault collection and control unit (FCCU)
– Safe mode of system-on-chip (SoC)
– Register protection scheme
LQFP100
14 x 14 mm
LQFP144
20 x 20 mm
■
Communications interfaces
– 2 LINFlex modules (LIN 2.1,
1 × Master/Slave, 1 × Master Only)
– 5 DSPI modules with automatic chip select
generation
– 2 FlexCAN interfaces (2.0B Active) with 32
message buffers
– 1 Safety port based on FlexCAN; usable as
third CAN when not used as safety port
– 1 FlexRay™ module (V2.1) with dual or
single channel, 64 message buffers and up
to 10 Mbit/s
■
2 CRC units with three contexts and 3
hardwired polynomials(CRC8,CRC32 and
CRC-16-CCITT)
■
10-bit A/D converter
– 27 input channels and pre-sampling feature
– Conversion time < 1 µs including sampling
time at full precision
– Programmable cross triggering unit (CTU)
– 4 analog watchdog with interrupt capability
■
Nexus® L2+ interface
■
Single 3.3 V or 5 V supply for I/Os and ADC
■
2 on-platform peripherals set with 2 INTC
■
■
16-channel eDMA controller with multiple
transfer request sources
On-chip CAN/UART Bootstrap loader with boot
assist module (BAM)
■
■
General purpose I/Os (80 GPIO + 26 GPI on
LQFP144; 49 GPIO + 16 GPI on LQFP100)
Ambient temperature ranges: –40 to 125 °C or
–40 to 105 °C
Table 1.
■
2 general purpose eTimer units
– 6 timers, each with up/down count
capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
May 2012
This is information on a product in full production.
Device summary
Part number
Package
768 KB Flash
1 MB Flash
LQFP144
SPC560P54L5
SPC56AP54L5
SPC560P60L5
SPC56AP60L5
LQFP100
SPC560P54L3
SPC56AP54L3
SPC560P60L3
SPC56AP60L3
Doc ID 18340 Rev 3
1/104
www.st.com
1
Contents
SPC56xP54x, SPC56xP60x
Contents
1
2/104
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.1
High performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3
Enhanced direct memory access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4
On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5
On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6
Interrupt controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.7
System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.8
Frequency modulated phase-locked loop (FMPLL) . . . . . . . . . . . . . . . . 16
1.5.9
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.10
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.11
Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12
System timer module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13
Software watchdog timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14
Fault collection and control unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.15
System integration unit (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.16
Boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.17
Error correction status module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18
FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.19
Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20
FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.21
Serial communication interface module (LINFlex) . . . . . . . . . . . . . . . . . 21
1.5.22
Deserial serial peripheral interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 22
1.5.23
eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.24
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.25
Cross triggering unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.26
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.27
Nexus development interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5.28
IEEE 1149.1 (JTAG) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
1.5.29
2
3
Contents
On-chip voltage regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27
2.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.1
Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.3
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.1
General notes for specifications at maximum junction temperature . . . 56
3.6
Electromagnetic interference (EMI) characteristics . . . . . . . . . . . . . . . . . 58
3.7
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8
Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 58
3.8.1
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58
3.8.2
Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
3.9
Power Up/Down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.10
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.10.1
3.11
NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.1
DC electrical characteristics (5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.11.2
DC electrical characteristics (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.11.3
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.12
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.13
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.14
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . 74
3.15
Analog-to-Digital converter (ADC) electrical characteristics . . . . . . . . . . 74
3.16
3.15.1
Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.15.2
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Doc ID 18340 Rev 3
3/104
Contents
SPC56xP54x, SPC56xP60x
3.17
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.17.1
3.18
4
Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.1
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.18.2
IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.18.3
Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.18.4
External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.18.5
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.1
LQFP144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.2
LQFP100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPC56xP54/60 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPC56xP54/60 device configuration difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPC56xP54/60 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Approved NPN ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . 64
Supply current (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . 67
Supply current (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Peripherals supply current (5 V and 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) . . . . . . . . . . . . . 72
Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1) . . . . . . . . . . . . . 72
Input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH)‘ . . . . . . . . . . . . . . . . . . . 73
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Doc ID 18340 Rev 3
5/104
List of figures
SPC56xP54x, SPC56xP60x
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
6/104
SPC56xP54/60 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LQFP176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LQFP100 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Independent ADC supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94
DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95
DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95
DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56xP54/60 series of microcontroller units (MCUs). It also describes the device
features and highlights important electrical and physical characteristics. For functional
characteristics, refer to the device reference manual.
1.2
Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement
in integrated automotive application controllers. It belongs to an expanding range of
automotive-focused products designed to address chassis applications specifically the
airbag application.
This family is one of a series of next-generation integrated automotive microcontrollers
based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family
complies with the Power Architecture embedded category. It operates up to 64 MHz and
offers high performance processing optimized for low power consumption. It capitalizes on
the available development infrastructure of current Power Architecture devices and is
supported with software drivers, operating systems and configuration code to assist with
users implementations.
1.3
Device comparison
Table 2 provides a summary of different members of the SPC56xP54/60 family and their
features—relative to Full-featured version—to enable a comparison among the family
members and an understanding of the range of functionality offered within this family.
Table 2.
SPC56xP54/60 device comparison
Feature
Code Flash memory (with ECC)
SPC560P54
SPC560P60
SPC56AP54
SPC56AP60
768 KB
1 MB
768 KB
1 MB
64 KB
80 KB
Data Flash / EE (with ECC)
SRAM (with ECC)
Processor core
64 KB
64 KB
80 KB
32-bit e200z0h
Instruction set
VLE
CPU performance
0-64 MHz
FMPLL (frequency-modulated phaselocked loop) modules
1
INTC (interrupt controller) channels
PIT (periodic interrupt timer)
32-bit Dual e200z0h
148
1 (includes four 32-bit timers)
Doc ID 18340 Rev 3
7/104
Introduction
Table 2.
SPC56xP54x, SPC56xP60x
SPC56xP54/60 device comparison (continued)
Feature
SPC560P54
SPC560P60
Enhanced DMA (direct memory
access) channels
SPC56AP54
SPC56AP60
16
FlexRay
Yes (64 message buffer)
3(1),(2)
FlexCAN (controller area network)
Safety port
Yes (via third FlexCAN module)
Yes(3)
FCCU (fault collection and control unit)
CTU (cross triggering unit)
Yes
eTimer channels
2×6
FlexPWM (pulse-width modulation)
channels
No
Analog-to-digital converters (ADC)
One (10-bit, 27-channel)(4)
LINFlex modules
2 (1 × Master/Slave, 1 × Master only)
DSPI (deserial serial peripheral
interface) modules
5(5)
CRC (cyclic redundancy check) units
2(6)
JTAG interface
Yes
Yes (Level 2+)(7)
Nexus port controller (NPC)
Digital power supply(8)
3.3 V or 5 V single supply with external transistor
Analog power supply
3.3 V or 5 V
Internal RC oscillator
16 MHz
Supply
External crystal oscillator
4–40 MHz
LQFP100
LQFP144
Packages
Temperature
Standard ambient
temperature
LQFP100
LQFP144
LQFP176 (9)
–40 to 125 °C
1. Each FlexCAN module has 32 message buffers.
2. One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
3. Enhanced FCCU version
4. Same amount of ADC channels as on SPC560P44/50 not considering the internally connected ones. 26 channels on
LQFP144 and 16 channels on LQFP100.
5. Increased number of CS for DSPI_1
6. Upgraded specification with addition of 8-bits polynomial (CRC-8 VDA CAN) support and 3rd context
7. Improved debugging capability with data trace capability and increased Nexus throughput available on emulation package
8. 3.3 V range and 5 V range correspond to different orderable parts.
9. Software development package only. Not available for production.
SPC56xP54/60 is present on the market in two different options enabling different features:
Full-featured, and Airbag configuration. Table 3 shows the main differences between the two
versions.
8/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 3.
Introduction
SPC56xP54/60 device configuration difference
Feature
Full-featured
Airbag
Yes
No
Yes (64 message buffer)
No
DSPI (deserial serial peripheral interface) modules
5
4
CRC (cyclic redundancy check) unit
2
1
CTU (cross triggering unit)
FlexRay
1.4
Block diagram
Figure 1 shows a top-level block diagram of the SPC56xP54/60 MCU. Table 4 summarizes
the functions of the blocks.
Doc ID 18340 Rev 3
9/104
Introduction
Figure 1.
SPC56xP54x, SPC56xP60x
SPC56xP54/60 block diagram
e200z0 Core
e200z0 Core
INTC_0
32-bit
general
purpose
registers
Variable
length
Exception
encoded
handler
instructions
32-bit
general
purpose
registers
Variable
length
Exception
encoded
handler
instructions
INTC_1
SWT_0
Special
purpose
registers
Integer
Instruction
execution
unit
unit
Special
purpose
registers
Integer
Instruction
execution
unit
unit
SWT_1
PMU
STM_0
Branch
prediction
unit
Load/Store
unit
Branch
prediction
unit
Load/Store
unit
JTAG
STM_1
JTAG
ECSM_1
ECSM_0
Nexus
port
controller
Nexus 2+
SEMA4_0
DMAMUX_0
INSTR
Nexus 2+
SEMA4_1
DATA
INSTR
DATA
DMA_0
M2
M3
M0
M1
M5
M6
Cross Bar Switch (XBAR, AMBA 2.0 v6 AHB) XBAR_0
Memory protection unit MPU_0
S7
Memory protection unit MPU_1
S2
S0
S1
NASPS_0
P0
NASPS_1
P1
PFLASHC_0
PBRIDGE_0
S6
S3
PBRIDGE_1
SRAMC_0
1024KB
code flash
with ECC
4x16KB
data flash
with ECC
32KB
SRAM
with ECC
26
10/104
Doc ID 18340 Rev 3
FCCU_0
DSPI_4
MC_RGM
XOSC
FMPLL
IRCOSC
CMU_1
CMU_0
MC_CGM
WakeUp
FlexCAN_0
Peripheral Bus (IPS)
SafetyPort_0
LINFlex_1
LINFlex_0
DSPI_3
DSPI_2
DSPI_1
DSPI_0
eTimer_1
eTimer_0
CTU_0
ADC_0
FlexRay
Peripheral Bus (IPS)
CRC_1
48KB
SRAM
with ECC
FlexCAN_1
MC_ME
SSCM
MC_PCU
PIT
BAM
SIUL
CRC_0
SRAMC_1
SPC56xP54x, SPC56xP60x
Table 4.
Introduction
SPC56xP54/60 series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM)
Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network
(FlexCAN)
Supports the standard CAN communications protocol
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR)
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus
width.
Cyclic redundancy checker
(CRC) unit
Is dedicated to the computation of CRC off-loading the CPU. Each context has
a separate CRC computation engine in order to allow the concurrent
computation of the CRC of multiple data streams.
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host
processor via “n” programmable channels
Enhanced timer (eTimer)
Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC)
Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection and control unit
(FCCU)
Provides functional safety to the device
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexRay (FlexRay communication
Provides high-speed distributed control for advanced automotive applications
controller)
Frequency-modulated phaselocked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Doc ID 18340 Rev 3
11/104
Introduction
Table 4.
SPC56xP54x, SPC56xP60x
SPC56xP54/60 series block summary (continued)
Block
Function
Peripheral bridge (PBRIDGE)
Is the interface between the system bus and on-chip peripherals
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the
device
Semaphore unit (SEMA4)
Provides the hardware support needed in multi-core systems for implementing
semaphores and provide a simple mechanism to achieve lock/unlock
operations via a single write access
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AUTOSAR(1) and operating
system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Wakeup unit (WKPU)
Supports up to 18 external sources that can generate interrupts or wakeup
events, of which 1 can cause non-maskable interrupt requests or wakeup
events.
1. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)
12/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
1.5
Feature details
1.5.1
High performance e200z0h core processor
The e200z0h Power Architecture core provides the following features:
1.5.2
●
High performance e200z0 core processor for managing peripherals and interrupts
●
Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
●
Harvard architecture
●
Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
–
Results in smaller code size footprint
–
Minimizes impact on performance
●
Branch processing acceleration using lookahead instruction buffer
●
Load/store unit
–
1-cycle load latency
–
Misaligned access support
–
No load-to-use pipeline bubbles
●
Thirty-two 32-bit general purpose registers (GPRs)
●
Separate instruction bus and load/store bus Harvard architecture
●
Hardware vectored interrupt support
●
Reservation instructions for implementing read-modify-write constructs
●
Long cycle time instructions, except for guarded loads, do not increase interrupt latency
●
Extensive system development support through Nexus debug port
●
Non maskable Interrupt support
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between six
master ports and six slave ports. The crossbar supports a 32-bit address bus width and a
32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grant it ownership of the slave port. All
other masters requesting that slave port are stalled until the higher priority master
completes its transactions. Requesting masters are treated with equal priority and will be
granted access to a slave port in round-robin fashion, based upon the ID of the last master
to be granted access.
Doc ID 18340 Rev 3
13/104
Introduction
SPC56xP54x, SPC56xP60x
The crossbar provides the following features:
●
●
1.5.3
6 master ports:
–
2 e200z0 core complex Instruction ports
–
2 e200z0 core complex Load/Store Data ports
–
eDMA
–
FlexRay
6 slave ports:
–
2 Flash memory (code flash and data flash)
–
2 SRAM (48 KB + 32 KB)
–
2 PBRIDGE
●
32-bit internal address, 32-bit internal data paths
●
Fixed Priority Arbitration based on Port Master
●
Temporary dynamic priority elevation of masters
Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size.
The eDMA module provides the following features:
1.5.4
●
16 channels support independent 8, 16 or 32-bit single value or block transfers
●
Supports variable sized queues and circular queues
●
Source and destination address registers are independently configured to postincrement or remain constant
●
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
●
Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
●
DMA transfers possible between system memories, DSPIs, ADC, eTimer and CTU
●
Programmable DMA Channel Multiplexer for assignment of any DMA source to any
available DMA channel with up to 30 potential request sources
●
eDMA abort operation through software
On-chip flash memory with ECC
The SPC56xP54/60 provides up to 1024 KB of programmable, non-volatile, flash memory.
The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash
memory module interfaces the system bus to a dedicated flash memory array controller. It
supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains a four-entry, 4x128-bit prefetch buffers. Prefetch buffer
hits allow no-wait responses. Normal flash memory array accesses are registered and are
forwarded to the system bus on the following cycle, incurring 2 wait states.
14/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
The flash memory module provides the following features:
●
1.5.5
Up to 1024 KB flash memory
–
14 blocks (2×16 KB + 2×32 KB + 2×16 KB + 2×64 KB + 6×128 KB) code flash
–
4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
–
Full Read While Write (RWW) capability between code and data flash
●
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
●
Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page
buffer miss at 64 MHz
●
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
●
Hardware and software configurable read and write access protections on a per-master
basis.
●
Configurable access timing allowing use in a wide range of system frequencies.
●
Multiple-mapping support and mapping-based block access timing (0–31 additional
cycles) allowing use for emulation of other memory types.
●
Software programmable block program/erase restriction control.
●
Erase of selected block(s)
●
Read page size of 128 bits (4 words)
●
64-bit ECC with single-bit correction, double-bit detection for data integrity
●
Embedded hardware program and erase algorithm
●
Erase suspend, program suspend and erase-suspended program
●
Censorship protection scheme to prevent flash memory content visibility
●
Hardware support for EEPROM emulation
On-chip SRAM with ECC
The SPC56xP54/60 SRAM module provides a general-purpose memory of up to 80 KB.
The SRAM module provides the following features:
●
Supports read/write accesses mapped to the SRAM memory from any master
●
Up to 80 KB general purpose RAM
–
1.5.6
2 blocks (48 KB + 32 KB)
●
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
●
Typical SRAM access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8and 16-bit writes if back to back with a read to same memory block
Interrupt controller (INTC)
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
Doc ID 18340 Rev 3
15/104
Introduction
SPC56xP54x, SPC56xP60x
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
The INTC provides the following features:
●
Unique 9-bit vector for each separate interrupt source
●
8 software triggerable interrupt sources
●
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Ability to modify the ISR or task priority.
–
●
Modifying the priority can be used to implement the Priority Ceiling Protocol for
accessing shared resources.
2 external high priority interrupts directly accessing the main core and IOP critical
interrupt mechanism
The INTC module is replicated for each processor.
1.5.7
System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC56xP54/60:
●
Lock detect circuitry continuously monitors lock status
●
Loss of clock (LOC) detection for PLL outputs
●
Programmable output clock divider (1, 2, 4, 8)
●
Programmable output clock divider (1, 2, 3 to 256)
●
eTimer module running at the same frequency as the e200z0h core
●
On-chip oscillator with automatic level control
●
Internal 16 MHz RC oscillator for rapid start-up and safe mode
–
1.5.8
Supports frequency trimming by user application
Frequency modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz
input clock. Further, the FMPLL supports programmable frequency modulation of the
system clock. The FMPLL multiplication factor, output clock divider ratio are all software
configurable.
16/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
The FMPLL has the following major features:
●
Input clock frequency from 4 MHz to 40 MHz
●
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
●
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
●
Modulation enabled/disabled through software
●
Triangle wave modulation
●
Programmable modulation depth (±0.25% to ±4% deviation from center frequency)
–
●
1.5.9
Programmable modulation frequency dependent on reference frequency
Self-clocked mode (SCM) operation
Main oscillator
The main oscillator provides these features:
1.5.10
●
Input frequency range 4 MHz to 40 MHz
●
Crystal input mode or Oscillator input mode
●
PLL reference
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current
charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap
reference voltage.
The RC Oscillator provides these features:
1.5.11
●
Nominal frequency 16 MHz
●
±6% variation over voltage and temperature after process trim
●
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the PLL
●
RC oscillator is used as the default system clock during startup
Periodic interrupt timer (PIT)
The PIT module implements these features:
1.5.12
●
Up to four general purpose interrupt timers
●
32-bit counter resolution
●
Clocked by system clock frequency
●
Each channel can be used as trigger for a DMA request
System timer module (STM)
The STM module implements these features:
●
32-bit up counter with 8-bit prescaler
●
Four 32-bit compare channels
●
Independent interrupt source for each channel
●
Counter can be stopped in debug mode
The STM module is replicated for each processor.
Doc ID 18340 Rev 3
17/104
Introduction
1.5.13
SPC56xP54x, SPC56xP60x
Software watchdog timer (SWT)
The SWT has the following features:
●
Fault tolerant output
●
Safe internal RC oscillator as reference clock
●
Windowed watchdog
●
Program flow control monitor with 16-bit pseudorandom key generation
The SWT module is replicated for each processor.
1.5.14
Fault collection and control unit (FCCU)
The FCCU provides an independent fault reporting mechanism even if the CPU is exhibiting
unstable behaviors. The FCCU module has the following features:
1.5.15
●
Redundant collection of hardware checker results
●
Redundant collection of error information and latch of faults from critical modules on
the device
●
Collection of self-test results
●
Configurable and graded fault control
–
Internal reactions (no internal reaction, IRQ)
–
External reaction (failure is reported to the external/surrounding system via
configurable output pins)
System integration unit (SIUL)
The SPC56xP54/60 SIUL controls MCU pad configuration, external interrupts, general
purpose I/O (GPIO) pin configuration, and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIUL provides the following features:
●
Centralized general purpose input output (GPIO) control of input/output pins and
analog input-only pads (package dependent)
●
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
●
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
●
All peripheral pins (except ADC channels) can be alternatively configured as both
general purpose input or output pins
●
ADC channels support alternative configuration as general purpose inputs
●
Direct readback of the pin value is supported on all pins through the SIU
●
Configurable digital input filter that can be applied to some general purpose input pins
for noise elimination
–
1.5.16
Up to 4 internal functions can be multiplexed onto one pin
Boot and censorship
Different booting modes are available in the SPC56xP54/60:
18/104
●
From internal flash memory
●
Via a serial link
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
The default booting scheme is the one which uses the internal flash memory (an internal
pull-down is used to select this mode). The alternate option allows the user to boot via
FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the contents of the flash memory and offer
increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile
memory.
Boot assist module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all
SPC56xP54/60 devices that are based on the e200z0h core. The BAM program is executed
every time the device is powered on if the alternate boot mode has been selected by the
user.
The BAM provides the following features:
1.5.17
●
Serial bootloading via FlexCAN or LINFlex.
●
BAM can accept a password via the used serial communication channel to grant the
legitimate user access to the non-volatile memory.
Error correction status module (ECSM)
The ECSM on this device features the following:
●
Platform configuration and revision
●
ECC error reporting for flash memory and SRAM
●
ECC error injection for SRAM
The ECSM module is replicated for each processor.
1.5.18
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth. FlexCAN module contains 32 message buffers.
Doc ID 18340 Rev 3
19/104
Introduction
SPC56xP54x, SPC56xP60x
The FlexCAN module provides the following features:
●
–
Standard data and remote frames
–
Extended data and remote frames
–
0 to 8 bytes data length
–
Programmable bit rate as fast as 1 Mbit/s
●
32 message buffers of 0 to 8 bytes data length
●
Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
●
Programmable loop-back mode supporting self-test operation
●
3 programmable mask registers
●
Programmable transmit-first scheme: lowest ID or lowest buffer number
●
Time stamp based on 16-bit free-running timer
●
Global network time, synchronized by a specific message
●
Maskable interrupts
●
Independent of the transmission medium (an external transceiver is assumed)
●
High immunity to EMI
●
Short latency time due to an arbitration scheme for high-priority messages
●
Transmit features
●
●
1.5.19
Full implementation of the CAN protocol specification, Version 2.0B
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
Arbitration scheme according to message ID or message buffer number
–
Internal arbitration to guarantee no inner or outer priority inversion
–
Transmit abort procedure and notification
Receive features
–
Individual programmable filters for each mailbox
–
8 mailboxes configurable as a six-entry receive FIFO
–
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
System clock
–
Direct oscillator clock to avoid PLL jitter
Safety port (FlexCAN)
The SPC56xP54/60 MCU has a second CAN controller synthesized to run at high bit rates
to be used as a safety port. The CAN module of the safety port provides the following
features:
20/104
●
Identical to the FlexCAN module
●
Bit rate as fast as 7.5 Mb at 60 MHz CPU clock using direct connection between CAN
modules (no physical transceiver required)
●
32 Message buffers of 0 to 8 bytes data length
●
Can be used as a third independent CAN module
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
1.5.20
Introduction
FlexRay
The FlexRay module provides the following features:
1.5.21
●
Full implementation of FlexRay Protocol Specification 2.1
●
64 configurable message buffers can be handled
●
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
●
Message buffers configurable as Tx, Rx or RxFIFO
●
Message buffer size configurable
●
Message filtering for all message buffers based on FrameID, cycle count and message
ID
●
Programmable acceptance filters for RxFIFO message buffers
Serial communication interface module (LINFlex)
The LINFlex on the SPC56xP54/60 features the following:
●
Supports LIN Master mode (on both modules), LIN Slave mode (on one module) and
UART mode
●
LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications
●
Handles LIN frame transmission and reception without CPU intervention
●
LIN features
●
●
–
Autonomous LIN frame handling
–
Message buffer to store Identifier and up to 8 data bytes
–
Supports message length as long as 64 bytes
–
Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing;
Checksum and Time-out errors
–
Classic or extended checksum calculation
–
Configurable Break duration as long as 36-bit times
–
Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
–
Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
–
Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
–
Autonomous LIN header handling
–
Autonomous LIN response handling
UART mode
–
Full-duplex operation
–
Standard non return-to-zero (NRZ) mark/space format
–
Data buffers with 4-byte receive, 4-byte transmit
–
Configurable word length (8-bit or 9-bit words)
–
Error detection and flagging
–
Parity, Noise and Framing errors
–
Interrupt-driven operation with four interrupt sources
–
Separate transmitter and receiver CPU interrupt sources
–
16-bit programmable baud-rate modulus counter and 16-bit fractional
–
2 receiver wake-up methods
Doc ID 18340 Rev 3
21/104
Introduction
1.5.22
SPC56xP54x, SPC56xP60x
Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial
interface for communication between the SPC56xP54/60 MCU and external devices.
The DSPI modules provide these features:
1.5.23
●
Full duplex, synchronous transfers
●
Master or slave operation
●
Programmable master bit rates
●
Programmable clock polarity and phase
●
End-of-transmission interrupt flag
●
Programmable transfer baud rate
●
Programmable data frames from 4 to 16 bits
●
Up to 28 chip select lines available
–
8 each on DSPI_0 and DSPI_1
–
4 each on DSPI_2, DSPI_3, and DSPI_4
●
8 clock and transfer attributes registers
●
Chip select strobe available as alternate function on one of the chip select pins for
deglitching
●
FIFOs for buffering up to 5 transfers on the transmit and receive side
●
Queueing operation possible through use of the eDMA
●
General purpose I/O functionality on pins when not used for SPI
eTimer
Two eTimer modules are provided, each with six 16-bit general purpose up/down
timer/counter per module. The following features are implemented:
●
●
22/104
Individual channel capability
–
Input capture trigger
–
Output compare
–
Double buffer (to capture rising edge and falling edge)
–
Separate prescaler for each counter
–
Selectable clock source
–
0% to 100% pulse measurement
–
Rotation direction flag (Quad decoder mode)
Maximum count rate
–
Equals peripheral clock/2 — for external event counting
–
Equals peripheral clock — for internal clock counting
●
Cascadeable counters
●
Programmable count modulo
●
Quadrature decode capabilities
●
Counters can share available input pins
●
Count once or repeatedly
●
Preloadable counters
●
Pins available as GPIO when timer functionality not in use
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
1.5.24
Introduction
Analog-to-digital converter (ADC)
The ADC module provides the following features:
Analog part:
●
1 on-chip analog-to-digital converter
●
10-bit AD resolution
●
1 sample and hold unit per ADC
●
Conversion time, including sampling time, less than 1 s (at full precision)
●
Typical sampling time is 150 ns min. (at full precision)
●
Differential non-linearity error (DNL) ±1 LSB
●
Integral non-linearity error (INL) ±1.5 LSB
●
Total unadjusted error (TUE) <3 LSB
●
Single-ended input signal range from 0 to 3.3 V / 5.0 V
●
ADC and its reference can be supplied with a voltage independent from VDDIO
●
ADC supply can be equal or higher than VDDIO
●
ADC supply and the ADC reference are not independent from each other (they are
internally bonded to the same pad)
●
Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part:
●
27 input channels (26 + 1 internally connected)
●
4 analog watchdogs to compare ADC results against predefined levels (low, high,
range) before results are stored
●
2 operating modes: Normal mode and CTU control mode
●
Normal mode features
●
1.5.25
–
Register-based interface with the CPU: control register, status register, 1 result
register per channel
–
ADC state machine managing 3 request flows: regular command, hardware
injected command, and software injected command
–
Selectable priority between software and hardware injected commands
–
DMA compatible interface
CTU control mode features
–
Triggered mode only
–
4 independent result queues (2 × 16 entries, 2 × 4 entries)
–
Result alignment circuitry (left justified; right justified)
–
32-bit read mode allows to have channel ID on one of the 16-bit part
–
DMA compatible interfaces
Cross triggering unit (CTU)
The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests
on user selected conditions with minimized CPU load for dynamic configuration.
Doc ID 18340 Rev 3
23/104
Introduction
SPC56xP54x, SPC56xP60x
It implements the following features:
1.5.26
1.5.27
●
Double buffered trigger generation unit with up to eight independent triggers generated
from external triggers
●
Trigger generation unit configurable in sequential mode or in triggered mode
●
Each Trigger can be appropriately delayed to compensate the delay of external low
pass filter
●
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●
Double buffered ADC command list pointers to minimize ADC-trigger unit update
●
Double buffered ADC conversion command list with up to 24 ADC commands
●
Each trigger has the capability to generate consecutive commands
●
ADC conversion command allows to control ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
Cyclic redundancy check (CRC)
●
3 contexts for the concurrent CRC computation
●
Separate CRC engine for each context
●
Zero-wait states during the CRC computation (pipeline scheme)
●
3 hard-wired polynomials (CRC-8 VDA CAN, CRC-32 ethernet and CRC-16-CCITT)
●
Support for byte/half-word/word width of the input data stream
●
Support for expected and actual CRC comparison
Nexus development interface (NDI)
The NDI block provides real-time development support capabilities for the SPC56xP54/60
Power Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard.
This development support is supplied for MCUs without requiring external address and data
pins for internal visibility. The NDI block is an integration of several individual Nexus blocks
that are selected to provide the development support interface for this device. The NDI block
interfaces to the host processor and internal buses to provide development support as per
the IEEE-ISTO 5001-2003 Class 2+ standard. The development support provided includes
access to the MCU’s internal memory map and access to the processor’s internal registers
during run time.
24/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Introduction
The Nexus Interface provides the following features:
●
Configured via the IEEE 1149.1
●
All Nexus port pins operate at VDDIO (no dedicated power supply)
●
Nexus 2+ features supported
●
●
–
Static debug
–
Watchpoint messaging
–
Ownership trace messaging
–
Program trace messaging
–
Real time read/write of any internally memory mapped resources through JTAG
pins
–
Overrun control, which selects whether to stall before Nexus overruns or keep
executing and allow overwrite of information
–
Watchpoint triggering, watchpoint triggers program tracing
–
DDR
Auxiliary Output Port
–
4 MDO (Message Data Out) pins
–
MCKO (Message Clock Out) pin
–
2 MSEO (Message Start/End Out) pins
–
EVTO (Event Out) pin
Auxiliary Input Port
–
1.5.28
EVTI (Event In) pin
IEEE 1149.1 (JTAG) controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features:
●
IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)
●
Selectable modes of operation include JTAGC/debug or normal system operation.
●
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
–
●
BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
A 5-bit instruction register that supports the additional following public instructions:
–
ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_CORE0,
ACCESS_AUX_TAP_CORE1, ACCESS_AUX_TAP_NASPS_0,
ACCESS_AUX_TAP_NASPS_1
●
Three test data registers: a bypass register, a boundary scan register, and a device
identification register.
●
A TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
Doc ID 18340 Rev 3
25/104
Introduction
1.5.29
SPC56xP54x, SPC56xP60x
On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
26/104
●
Uses external NPN transistor
●
Regulates external 3.3 V to 5.0 V down to 1.2 V for the core logic
●
Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
The LQFP pinouts are shown in the following figures.
LQFP176 pinout (top view)(a)
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PA[15]
PA[14]
PC[6]
PG[1]
RDY
MDO11
VSS_HV_IO4
VDD_HV_IO4
PD[2]
PF[3]
MDO10
NC
NC
NC
PB[6]
PF[2]
PA[13]
PF[1]
PA[9]
PF[0]
VSS_LV_COR2
VDD_LV_COR2
PC[8]
PD[4]
PD[3]
VSS_HV_IO3
VDD_HV_IO3
PD[0]
PC[15]
PC[9]
PA[12]
PE[15]
PA[11]
PE[14]
PA[10]
PE[13]
PB[3]
PF[14]
PB[2]
PF[15]
PF[13]
PC[10]
PB[1]
PB[0]
Figure 2.
NMI
PA[6]
PD[1]
PF[4]
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
LQFP176
PA[4]
VPP_TEST
PF[12]
PD[14]
PG[3]
PC[14]
PG[2]
PC[13]
PG[4]
PD[12]
PG[6]
VDD_HV_FL
VSS_HV_FL
PD[13]
VSS_LV_COR1
VDD_LV_COR1
PA[3]
VDD_HV_IO2
VSS_HV_IO2
NC
MDO9
MDO8
MDO7
VSS_HV_IO6
VDD_HV_IO6
TDO
TCK
TMS
TDI
PG[5]
PA[2]
PG[7]
PC[12]
NC
NC
PG[8]
PC[11]
PG[9]
PD[11]
PG[10]
PD[10]
PG[11]
PA[1]
PA[0]
VDD_LV_REGCOR
NC
NC
VSS_LV_REGCOR
VDD_HV_REG
NC
NC
PD[7]
PG[0]
PE[1]
PE[3]
PC[1]
PE[4]
PB[7]
PE[5]
PC[2]
PE[6]
PB[8]
PE[7]
PE[2]
NC
VREG_BYPASS
PB[9]
PB[10]
PB[11]
PB[12]
VDD_HV_AD
VSS_HV_AD
PD[15]
PE[8]
PB[13]
PE[9]
PB[15]
NC
NC
NC
NC
PE[10]
PB[14]
PE[11]
PC[0]
PE[12]
PE[0]
BCTRL
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VDD_HV_IO5
VSS_HV_IO5
MDO4
MDO5
MDO6
NC
NC
NC
PF[5]
VDD_HV_IO0
VSS_HV_IO0
PF[6]
MDO0
PA[7]
PC[4]
PA[8]
PC[5]
PA[5]
PC[7]
PC[3]
VSS_LV_COR0
VDD_LV_COR0
PF[7]
PF[8]
VDD_HV_IO1
VSS_HV_IO1
PF[9]
PF[10]
PF[11]
PD[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
PD[8]
PD[5]
PD[6]
VSS_LV_COR3
VDD_LV_COR3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
a. Software development package only. Not available for production.
Doc ID 18340 Rev 3
27/104
Package pinouts and signal descriptions
LQFP144 pinout (top view)(b)
NMI
PA[6]
PD[1]
PF[4]
PF[5]
VDD_HV_IO0
VSS_HV_IO0
PF[6]
MDO
PA[7]
PC[4]
PA[8]
PC[5]
PA[5]
PC[7]
PC[3]
VSS_LV_COR0
VDD_LV_COR0
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
LQFP144
b. Availability of port pin alternate functions depends on product selection
28/104
Doc ID 18340 Rev 3
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
PD[15]
PE[8]
PB[13]
PE[9]
PB[15]
PE[10]
PB[14]
PE[11]
PC[0]
PE[12]
PE[0]
BCTRL
VREG_BYPASS
PB[9]
PB[10]
PB[11]
PB[12]
VDD_HV_AD
VSS_HV_AD
PD[7]
PG[0]
PE[1]
PE[3]
PC[1]
PE[4]
PB[7]
PE[5]
PC[2]
PE[6]
PB[8]
PE[7]
PE[2]
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PF[7]
PF[8]
VDD_HV_IO1
VSS_HV_IO1
PF[9]
PF[10]
PF[11]
PD[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
PD[8]
PD[5]
PD[6]
VSS_LV_COR3
VDD_LV_COR3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PA[15]
PA[14]
PC[6]
PG[1]
PD[2]
PF[3]
PB[6]
PF[2]
PA[13]
PF[1]
PA[9]
PF[0]
VSS_LV_COR2
VDD_LV_COR2
PC[8]
PD[4]
PD[3]
VSS_HV_IO3
VDD_HV_IO3
PD[0]
PC[15]
PC[9]
PA[12]
PE[15]
PA[11]
PE[14]
PA[10]
PE[13]
PB[3]
PF[14]
PB[2]
PF[15]
PF[13]
PC[10]
PB[1]
PB[0]
Figure 3.
SPC56xP54x, SPC56xP60x
PA[4]
VPP_TEST
PF[12]
PD[14]
PG[3]
PC[14]
PG[2]
PC[13]
PG[4]
PD[12]
PG[6]
VDD_HV_FL
VSS_HV_FL
PD[13]
VSS_LV_COR1
VDD_LV_COR1
PA[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
PG[5]
PA[2]
PG[7]
PC[12]
PG[8]
PC[11]
PG[9]
PD[11]
PG[10]
PD[10]
PG[11]
PA[1]
PA[0]
SPC56xP54x, SPC56xP60x
Package pinouts and signal descriptions
LQFP100 pinout (top view)(c)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PA[15]
PA[14]
PC[6]
PD[2]
PB[6]
PA[13]
PA[9]
VSS_LV_COR2
VDD_LV_COR2
PC[8]
PD[4]
PD[3]
VSS_HV_IO3
VDD_HV_IO3
PD[0]
PC[15]
PC[9]
PA[12]
PA[11]
PA[10]
PB[3]
PB[2]
PC[10]
PB[1]
PB[0]
Figure 4.
NMI
PA[6]
PD[1]
PA[7]
PC[4]
PA[8]
PC[5]
PA[5]
PC[7]
PC[3]
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[4]
VPP TEST
PD[14]
PC[14]
PC[13]
PD[12]
VDD_HV_FL
VSS_HV_FL
PD[13]
VSS_LV_COR1
VDD_LV_COR1
PA[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
PA[2]
PC[12]
PC[11]
PD[11]
PD[10]
PA[1]
PA[0]
2.2
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
VREG_BYPASS
PB[9]
PB[10]
PB[11]
PB[12]
VDD_HV_AD
VSS_HV_AD
PD[15]
PB[13]
PB[15]
PB[14]
PC[0]
PE[0]
BCTRL
PD[7]
PE[1]
PC[1]
PB[7]
PC[2]
PB[8]
PE[2]
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS_LV_COR0
VDD_LV_COR0
VDD_HV_IO1
VSS_HV_IO1
PD[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
PD[8]
PD[5]
PD[6]
VSS_LV_COR3
VDD_LV_COR3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin descriptions
The following sections provide signal descriptions and related information about the
functionality and configuration of the SPC56xP54/60 devices.
2.2.1
Power supply and reference voltage pins
Table 5 lists the power supply and reference voltage for the SPC56xP54/60 devices.
Table 5.
Supply pins
Supply
Symbol
Pin
Description
LQFP
100
LQFP
144
LQFP
176(1)
47
69
81
50
72
86
VREG control and power supply pins
BCTRL
Voltage regulator external NPN Ballast base control pin
VDD_HV_REG (3.3 V or
Voltage regulator supply voltage
5.0 V)
c.
Availability of port pin alternate functions depends on product selection
Doc ID 18340 Rev 3
29/104
Package pinouts and signal descriptions
Table 5.
SPC56xP54x, SPC56xP60x
Supply pins (continued)
Supply
Pin
LQFP
100
LQFP
144
LQFP
176(1)
VDD_LV_REGCOR
1.2 V decoupling(2) pins for core logic supply and voltage
regulator feedback. Decoupling capacitor must be connected
between this pins and VSS_LV_REGCOR.
48
70
82
VSS_LV_REGCOR
1.2 V decoupling(2) pins for core logic GND and voltage regulator
feedback. Decoupling capacitor must be connected between this
pins and VDD_LV_REGCOR.
49
71
85
Symbol
Description
ADC0 reference and supply voltage
VDD_HV_AD
ADC supply and high reference voltage
39
56
64
VSS_HV_AD
ADC ground and low reference voltage
40
57
65
Power supply pins (3.3 V or 5.0 V)
VDD_HV_IO0
Input/Output supply voltage
—
6
14
VSS_HV_IO0
Input/Output ground
—
7
15
VDD_HV_IO1
Input/Output supply voltage
13
21
29
VSS_HV_IO1
Input/Output ground
14
22
30
VDD_HV_IO2
Input/Output supply voltage
63
91
115
VSS_HV_IO2
Input/Output ground
62
90
114
VDD_HV_IO3
Input/Output supply voltage
87
126
150
VSS_HV_IO3
Input/Output ground
88
127
151
VDD_HV_IO4
Input/Output supply voltage
—
—
169
VSS_HV_IO4
Input/Output ground
—
—
170
VDD_HV_IO5
Input/Output supply voltage
—
—
5
VSS_HV_IO5
Input/Output ground
—
—
6
VDD_HV_IO6
Input/Output supply voltage
—
—
108
VSS_HV_IO6
Input/Output ground
—
—
109
VDD_HV_FL
Code and data flash supply voltage
69
97
121
VSS_HV_FL
Code and data flash supply ground
68
96
120
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
16
27
35
VSS_HV_OSC
Crystal oscillator amplifier ground
17
28
36
Power supply pins (1.2 V)
VDD_LV_COR0
1.2 V Decoupling pins for core logic supply. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR0 pin.
12
18
26
VSS_LV_COR0
1.2 V Decoupling pins for core logic GND. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR0 pin.
11
17
25
30/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 5.
Package pinouts and signal descriptions
Supply pins (continued)
Supply
Pin
Symbol
Description
LQFP
100
LQFP
144
LQFP
176(1)
VDD_LV_COR1
1.2 V Decoupling pins for core logic supply. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR1 pin.
65
93
117
VSS_LV_COR1
1.2 V Decoupling pins for core logic GND. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR1 pin.
66
94
118
VDD_LV_COR2
1.2 V Decoupling pins for core logic supply. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR2 pin.
92
131
155
VSS_LV_COR2
1.2 V Decoupling pins for core logic GND. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR 2 pin.
93
132
156
VDD_LV_COR3
1.2 V Decoupling pins for core logic supply. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR3 pin.
25
36
44
VSS_LV_COR3
1.2 V Decoupling pins for core logic GND. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR 3 pin.
24
35
43
1. LQFP176 available only as development package.
2. See datasheet Voltage Regulator Electrical Characteristics section for more details.
2.2.2
System pins
Table 6 and Table 7 contain information on pin functions for the SPC56xP54/60 devices. The
pins listed in Table 6 are single-function pins. The pins shown in Table 7 are multi-function
pins, programmable via their respective Pad Configuration Register (PCR) values.
Table 6.
Symbol
System pins
Description
Pad Speed(1)
Pin
SRC=0 SRC=1
LQFP LQFP LQFP
100
144 176(2)
Direction
Dedicated pins
MDO0
Nexus Message Data Output—line 0
Output
Only
Fast
—
9
17
MDO4
Nexus Message Data Output—line 4
Output
Only
Fast
—
—
7
MDO5
Nexus Message Data Output—line 5
Output
Only
Fast
—
—
8
MDO6
Nexus Message Data Output—line 6
Output
Only
Fast
—
—
9
Doc ID 18340 Rev 3
31/104
Package pinouts and signal descriptions
Table 6.
SPC56xP54x, SPC56xP60x
System pins (continued)
Symbol
Description
Pad Speed(1)
Pin
SRC=0 SRC=1
LQFP LQFP LQFP
100
144 176(2)
Direction
MDO7
Nexus Message Data Output—line 7
Output
Only
Fast
—
—
110
MDO8
Nexus Message Data Output—line 8
Output
Only
Fast
—
—
111
MDO9
Nexus Message Data Output—line 9
Output
Only
Fast
—
—
112
MDO10
Nexus Message Data Output—line 10
Output
Only
Fast
—
—
166
MDO11
Nexus Message Data Output—line 11
Output
Only
Fast
—
—
171
RDY
Nexus ready output
Output
Only
—
—
—
—
172
NMI
Non-Maskable Interrupt
Input Only
—
—
1
1
1
XTAL
Analog output of the oscillator amplifier
circuit. Needs to be grounded if oscillator is
used in bypass mode.
—
—
—
18
29
37
EXTAL
Analog input of the oscillator amplifier
circuit, when the oscillator is not in bypass
mode.
Analog input for the clock generator when
the oscillator is in bypass mode.
—
—
—
19
30
38
TMS(3)
JTAG state machine control
Input Only
—
—
59
87
105
TCK
JTAG clock
Input Only
—
—
60
88
106
TDI(3)
JTAG data input
Input Only
—
—
58
86
104
TDO(3)
JTAG data output
Output
Only
—
—
61
89
107
Bidirectional
Medium
—
20
31
39
(3)
Reset pin
RESET(4)
Bidirectional reset with Schmitt trigger
characteristics and
noise filter
Test pin
VPP TEST
Pin for testing purpose only. To be tied to
ground in normal operating mode.
—
—
—
74
107
131
VREG_BYPASS
Pin for testing purpose only. To be tied to
ground in normal operating mode.
—
—
—
34
51
59
1. SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
2. LQFP176 available only as development package.
3. In this pin there is an internal pull, refer to JTAGC chapter in the device reference manual for pull direction.
4. Its configuration can be set up by the PCR[108] register inside the SIU module. See SIUL chapter in the device reference
manual.
32/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
2.2.3
Package pinouts and signal descriptions
Pin muxing
Table 7 defines the pin list and muxing for the SPC56xP54/60 devices relative to Fullfeatured version.
Each row of Table 7 shows all the possible ways of configuring each pin, via “alternate
functions”. The default function assigned to each pin after reset is the ALT0 function.
Pins marked as external interrupt capable can also be used to resume from STOP and
HALT mode.
SPC56xP54/60 devices provide four main I/O pad types depending on the associated
functions:
●
Slow pads are the most common, providing a compromise between transition time and
low electromagnetic emission.
●
Medium pads provide fast enough transition for serial communication channels with
controlled current to reduce electromagnetic emission.
●
Fast pads provide maximum speed. They are used for improved NEXUS debugging
capability.
●
Symmetric pads are designed to meet FlexRay requirements.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
Table 7.
Port
pin
Pin muxing(1)
PCR
register
Alternate
function
(2),(3)
Functions
Peripheral
(4)
I/O
direction
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
Port A
A[0]
A[1]
A[2](8)
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
ETC[0]
SCK_2
F[0]
EIRQ[0]
SIUL
eTimer_0
DSPI_2
FCCU
SIUL
I/O
I/O
I/O
O
I
Slow
Medium
51
73
89
PCR[1]
ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
ETC[1]
SOUT_2
F[1]
EIRQ[1]
SIUL
eTimer_0
DSPI_2
FCCU
SIUL
I/O
I/O
O
O
I
Slow
Medium
52
74
90
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
ETC[2]
CS3
—
SIN_2
ABS[0]
EIRQ[2]
SIUL
eTimer_0
DSPI_4
—
DSPI_2
MC_RGM
SIUL
I/O
I/O
O
—
I
I
I
Slow
Medium
57
84
102
Doc ID 18340 Rev 3
33/104
Package pinouts and signal descriptions
Table 7.
Port
pin
A[3](8)
A[4](8)
A[5]
A[6]
A[7]
A[8]
A[9]
34/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[3]
ETC[3]
CS0_2
—
ABS[1]
EIRQ[3]
SIUL
eTimer_0
DSPI_2
—
MC_RGM
SIUL
I/O
I/O
I/O
—
I
I
Slow
Medium
64
92
116
PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[4]
ETC[0]
CS1_2
ETC[4]
FAB
EIRQ[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
I/O
I/O
O
I/O
I
I
Slow
Medium
75
108
132
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
CS0_1
ETC[5]
CS7_0
EIRQ[5]
SIUL
DSPI_1
eTimer_1
DSPI_0
SIUL
I/O
I/O
I/O
O
I
Slow
Medium
8
14
22
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
GPIO[6]
SCK_1
CS2_4
—
EIRQ[6]
SIUL
DSPI_1
DSPI_4
—
SIUL
I/O
I/O
I/O
—
I
Slow
Medium
2
2
2
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
GPIO[7]
SOUT_1
CS1_4
—
EIRQ[7]
SIUL
DSPI_1
DSPI_4
—
SIUL
I/O
O
I/O
—
I
Slow
Medium
4
10
18
PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[8]
—
CS0_4
—
SIN_1
EIRQ[8]
SIUL
—
DSPI_4
—
DSPI_1
SIUL
I/O
—
I/O
—
I
I
Slow
Medium
6
12
20
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
CS1_2
—
—
SIN_4
SIUL
DSPI_2
—
—
DSPI_4
I/O
O
—
—
I
Slow
Medium
94
134
158
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[10]
ALT0
ALT1
ALT2
ALT3
—
GPIO[10]
CS0_2
—
—
EIRQ[9]
SIUL
DSPI_2
—
—
SIUL
I/O
I/O
—
—
I
Slow
Medium
81
118
142
PCR[11]
ALT0
ALT1
ALT2
ALT3
—
GPIO[11]
SCK_2
—
—
EIRQ[10]
SIUL
DSPI_2
—
—
SIUL
I/O
I/O
—
—
I
Slow
Medium
82
120
144
PCR[12]
ALT0
ALT1
ALT2
ALT3
—
GPIO[12]
SOUT_2
—
—
EIRQ[11]
SIUL
DSPI_2
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
83
122
146
PCR[13]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[13]
CS4_1
—
—
SIN_2
EIRQ[12]
SIUL
DSPI_1
—
—
DSPI_2
SIUL
I/O
—
—
—
I
I
Slow
Medium
95
136
160
PCR[14]
ALT0
ALT1
ALT2
ALT3
—
GPIO[14]
TXD
ETC[4]
CS5_1
EIRQ[13]
SIUL
Safety Port
eTimer_1
DSPI_1
SIUL
I/O
O
I/O
O
I
Slow
Medium
99
143
175
PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[15]
CS6_1
ETC[5]
—
RXD
EIRQ[14]
SIUL
DSPI_1
eTimer_1
—
Safety Port
SIUL
I/O
O
I/O
—
I
I
Slow
Medium
100
144
176
I/O
O
I/O
—
I
Slow
Medium
76
109
133
Port B
B[0]
PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TXD
ETC[2]
DEBUG[0]
EIRQ[15]
SIUL
FlexCAN_0
eTimer_1
SSCM
SIUL
Doc ID 18340 Rev 3
35/104
Package pinouts and signal descriptions
Table 7.
Port
pin
B[1]
B[2]
B[3]
B[6]
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
B[8]
B[9]
36/104
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[17]
CS7_1
ETC[3]
DEBUG[1]
RXD
EIRQ[16]
SIUL
DSPI_1
eTimer_1
SSCM
FlexCAN_0
SIUL
I/O
O
I/O
—
I
I
Slow
Medium
77
110
134
PCR[18]
ALT0
ALT1
ALT2
ALT3
—
GPIO[18]
TXD
SOUT_4
DEBUG[2]
EIRQ[17]
SIUL
LINFlex_0
DSPI_4
SSCM
SIUL
I/O
O
I/O
—
I
Slow
Medium
79
114
138
PCR[19]
ALT0
ALT1
ALT2
ALT3
—
GPIO[19]
—
SCK_4
DEBUG[3]
RXD
SIUL
—
DSPI_4
SSCM
LINFlex_0
I/O
—
I/O
—
I
Slow
Medium
80
116
140
SIUL
MC_CGL
DSPI_2
MC_CGL
I/O
O
O
O
Slow
Medium
96
138
162
SIUL
I
PCR[22]
ALT0
ALT1
ALT2
ALT3
—
B[7]
SPC56xP54x, SPC56xP60x
GPIO[22]
clk_out
CS2_2
clk_out_div256
EIRQ[18]
PCR[23]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[23]
—
—
—
AN[0]
RXD
SIUL
—
—
Input Only
—
ADC_0
LINFlex_0
—
—
29
43
51
PCR[24]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[24]
—
—
—
AN[1]
ETC[5]
SIUL
—
—
—
ADC_0
eTimer_0
Input Only
—
—
31
47
55
PCR[25]
ALT0
ALT1
ALT2
ALT3
—
GPIO[25]
—
—
—
AN[11]
SIUL
—
—
—
ADC_0
Input Only
—
—
35
52
60
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
B[10]
B[11]
B[12]
B[13]
B[14]
B[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
I/O
direction
Peripheral
(4)
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[26]
ALT0
ALT1
ALT2
ALT3
—
GPIO[26]
—
—
—
AN[12]
SIUL
—
—
—
ADC_0
Input Only
—
—
36
53
61
PCR[27]
ALT0
ALT1
ALT2
ALT3
—
GPIO[27]
—
—
—
AN[13]
SIUL
—
—
—
ADC_0
Input Only
—
—
37
54
62
PCR[28]
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
—
—
AN[14]
SIUL
—
—
—
ADC_0
Input Only
—
—
38
55
63
PCR[29]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[29]
—
—
—
AN[16]
RXD
SIUL
—
—
Input Only
—
ADC_0
LINFlex_1
—
—
42
60
68
PCR[30]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[30]
—
—
—
AN[17]
ETC[4]
EIRQ[19]
SIUL
—
—
—
ADC_0
eTimer_0
SIUL
Input Only
—
—
44
64
76
PCR[31]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[31]
—
—
—
AN[18]
EIRQ[20]
SIUL
—
—
—
ADC_0
SIUL
Input Only
—
—
43
62
70
—
—
45
66
78
Port C
C[0]
PCR[32]
ALT0
ALT1
ALT2
ALT3
—
GPIO[32]
—
—
—
AN[19]
SIUL
—
—
—
ADC_0
Input Only
Doc ID 18340 Rev 3
37/104
Package pinouts and signal descriptions
Table 7.
Port
pin
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
38/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
Peripheral
(4)
I/O
direction
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[33]
ALT0
ALT1
ALT2
ALT3
—
GPIO[33]
—
—
—
AN[2]
SIUL
—
—
—
ADC_0
Input Only
—
—
28
41
49
PCR[34]
ALT0
ALT1
ALT2
ALT3
—
GPIO[34]
—
—
—
AN[3]
SIUL
—
—
—
ADC_0
Input Only
—
—
30
45
53
PCR[35]
ALT0
ALT1
ALT2
ALT3
—
GPIO[35]
CS1_0
ETC[4]
TXD
EIRQ[21]
SIUL
DSPI_0
eTimer_1
LINFlex_1
SIUL
I/O
O
I/O
O
I
Slow
Medium
10
16
24
PCR[36]
ALT0
ALT1
ALT2
ALT3
—
GPIO[36]
CS0_0
—
DEBUG[4]
EIRQ[22]
SIUL
DSPI_0
—
SSCM
SIUL
I/O
I/O
—
—
I
Slow
Medium
5
11
19
PCR[37]
ALT0
ALT1
ALT2
ALT3
—
GPIO[37]
SCK_0
SCK_4
DEBUG[5]
EIRQ[23]
SIUL
DSPI_0
DSPI_4
SSCM
SIUL
I/O
I/O
I/O
—
I
Slow
Medium
7
13
21
PCR[38]
ALT0
ALT1
ALT2
ALT3
—
GPIO[38]
SOUT_0
—
DEBUG[6]
EIRQ[24]
SIUL
DSPI_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow
Medium
98
142
174
PCR[39]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[39]
—
—
DEBUG[7]
SIN_0
SIN_4
SIUL
—
—
SSCM
DSPI_0
DSPI_4
I/O
—
—
—
I
I
Slow
Medium
9
15
23
PCR[40]
ALT0
ALT1
ALT2
ALT3
GPIO[40]
CS1_1
CS1_4
CS6_0
SIUL
DSPI_1
DSPI_4
DSPI_0
I/O
O
O
O
Slow
Medium
91
130
154
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
C[9]
C[10]
C[11]
C[12]
C[13]
C[14]
C[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[41]
ALT0
ALT1
ALT2
ALT3
GPIO[41]
CS3_2
CS0_4
—
SIUL
DSPI_2
DSPI_4
—
I/O
O
I/O
—
Slow
Medium
84
123
147
PCR[42]
ALT0
ALT1
ALT2
ALT3
GPIO[42]
CS2_2
CS2_4
—
SIUL
DSPI_2
DSPI_4
—
I/O
O
O
—
Slow
Medium
78
111
135
PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[4]
CS2_2
CS0_3
SIUL
eTimer_0
DSPI_2
DSPI_3
I/O
I/O
O
I/O
Slow
Medium
55
80
96
PCR[44]
ALT0
ALT1
ALT2
ALT3
GPIO[44]
ETC[5]
CS3_2
CS1_3
SIUL
eTimer_0
DSPI_2
DSPI_3
I/O
I/O
O
O
Slow
Medium
56
82
100
PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
ETC[1]
—
—
EXT_IN
RXD
SIUL
eTimer_1
—
—
CTU_0
FlexCAN_1
I/O
I/O
—
—
I
I
Slow
Medium
71
101
125
PCR[46]
ALT0
ALT1
ALT2
ALT3
GPIO[46]
ETC[2]
EXT_TGR
TXD
SIUL
eTimer_1
CTU_0
FlexCAN_1
I/O
I/O
O
O
Slow
Medium
72
103
127
PCR[47]
ALT0
ALT1
ALT2
ALT3
—
GPIO[47]
CA_TR_EN
ETC[0]
—
EXT_IN
SIUL
FlexRay_0
eTimer_1
—
CTU_0
I/O
O
I/O
—
I
Slow
Symmetric
85
124
148
I/O
O
I/O
—
Slow
Symmetric
86
125
149
Port D
D[0]
PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
CA_TX
ETC[1]
—
SIUL
FlexRay_0
eTimer_1
—
Doc ID 18340 Rev 3
39/104
Package pinouts and signal descriptions
Table 7.
Port
pin
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
40/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[49]
ALT0
ALT1
ALT2
ALT3
—
GPIO[49]
CS4_1
ETC[2]
EXT_TRG
CA_RX
SIUL
DSPI_1
eTimer_1
CTU_0
FlexRay_0
I/O
O
I/O
O
I
Slow
Medium
3
3
3
PCR[50]
ALT0
ALT1
ALT2
ALT3
—
GPIO[50]
CS5_1
ETC[3]
—
CB_RX
SIUL
DSPI_1
eTimer_1
—
FlexRay_0
I/O
O
I/O
—
I
Slow
Medium
97
140
168
PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
CB_TX
ETC[4]
—
SIUL
FlexRay_0
eTimer_1
—
I/O
O
I/O
—
Slow
Symmetric
89
128
152
PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
CB_TR_EN
ETC[5]
—
SIUL
FlexRay_0
eTimer_1
—
I/O
O
I/O
—
Slow
Symmetric
90
129
153
PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
CS3_0
—
SOUT_3
SIUL
DSPI_0
—
DSPI_3
I/O
O
—
O
Slow
Medium
22
33
41
PCR[54]
ALT0
ALT1
ALT2
ALT3
GPIO[54]
CS2_0
SCK_3
SOUT_4
SIUL
DSPI_0
DSPI_3
DSPI_4
I/O
O
I/O
O
Slow
Medium
23
34
42
PCR[55]
ALT0
ALT1
ALT2
ALT3
—
GPIO[55]
CS3_1
—
CS4_0
SIN_3
SIUL
DSPI_1
—
DSPI_0
DSPI_3
I/O
O
—
O
I
Slow
Medium
26
37
45
PCR[56]
ALT0
ALT1
ALT2
ALT3
GPIO[56]
CS2_1
RDY
CS5_0
SIUL
DSPI_1
nexus_0
DSPI_0
I/O
O
O
O
Slow
Medium
21
32
40
PCR[57]
ALT0
ALT1
ALT2
ALT3
GPIO[57]
—
TXD
CS6_1
SIUL
—
LINFlex_1
DSPI_1
I/O
—
O
O
Slow
Medium
15
26
34
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
—
CS0_3
—
SIUL
—
DSPI_3
—
I/O
—
I/O
—
Slow
Medium
53
76
92
PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
—
CS1_3
SCK_3
SIUL
—
DSPI_3
DSPI_3
I/O
—
O
I/O
Slow
Medium
54
78
94
PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
—
—
DS7_1
RXD
SIUL
—
—
DSPI_1
LINFlex_1
I/O
—
—
O
I
Slow
Medium
70
99
123
PCR[61]
ALT0
ALT1
ALT2
ALT3
GPIO[61]
—
CS2_3
SOUT_3
SIUL
—
DSPI_3
DSPI_3
I/O
—
O
O
Slow
Medium
67
95
119
PCR[62]
ALT0
ALT1
ALT2
ALT3
—
GPIO[62]
—
CS3_3
—
SIN_3
SIUL
—
DSPI_3
—
DSPI_3
I/O
—
O
—
I
Slow
Medium
73
105
129
PCR[63]
ALT0
ALT1
ALT2
ALT3
—
GPIO[63]
—
—
—
AN[20]
SIUL
—
—
—
ADC_0
Input Only
—
—
41
58
66
Port E
E[0]
E[1]
PCR[64]
ALT0
ALT1
ALT2
ALT3
—
GPIO[64]
—
—
—
AN[21]
SIUL
—
—
—
ADC_0
Input Only
—
—
46
68
80
PCR[65]
ALT0
ALT1
ALT2
ALT3
—
GPIO[65]
—
—
—
AN[4]
SIUL
—
—
—
ADC_0
Input Only
—
—
27
39
47
Doc ID 18340 Rev 3
41/104
Package pinouts and signal descriptions
Table 7.
Port
pin
E[2]
E[3]
E[4]
E[5]
E[6]
E[7]
E[8]
E[9]
42/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
Peripheral
(4)
I/O
direction
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[66]
ALT0
ALT1
ALT2
ALT3
—
GPIO[66]
—
—
—
AN[5]
SIUL
—
—
—
ADC_0
Input Only
—
—
32
49
57
PCR[67]
ALT0
ALT1
ALT2
ALT3
—
GPIO[67]
—
—
—
AN[6]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
40
48
PCR[68]
ALT0
ALT1
ALT2
ALT3
—
GPIO[68]
—
—
—
AN[7]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
42
50
PCR[69]
ALT0
ALT1
ALT2
ALT3
—
GPIO[69]
—
—
—
AN[8]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
44
52
PCR[70]
ALT0
ALT1
ALT2
ALT3
—
GPIO[70]
—
—
—
AN[9]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
46
54
PCR[71]
ALT0
ALT1
ALT2
ALT3
—
GPIO[71]
—
—
—
AN[10]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
48
56
PCR[72]
ALT0
ALT1
ALT2
ALT3
—
GPIO[72]
—
—
—
AN[22]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
59
67
PCR[73]
ALT0
ALT1
ALT2
ALT3
—
GPIO[73]
—
—
—
AN[23]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
61
69
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
E[10]
E[11]
E[12]
E[13]
E[14]
E[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
I/O
direction
Peripheral
(4)
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[74]
ALT0
ALT1
ALT2
ALT3
—
GPIO[74]
—
—
—
AN[24]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
63
75
PCR[75]
ALT0
ALT1
ALT2
ALT3
—
GPIO[75]
—
—
—
AN[25]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
65
77
PCR[76]
ALT0
ALT1
ALT2
ALT3
—
GPIO[76]
—
—
—
AN[26]
SIUL
—
—
—
ADC_0
Input Only
—
—
—
67
79
PCR[77]
ALT0
ALT1
ALT2
ALT3
—
GPIO[77]
SCK_3
—
—
EIRQ[25]
SIUL
DSPI_3
—
—
SIUL
I/O
I/O
—
—
I
Slow
Medium
—
117
141
PCR[78]
ALT0
ALT1
ALT2
ALT3
—
GPIO[78]
SOUT_3
—
—
EIRQ[26]
SIUL
DSPI_3
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
—
119
143
PCR[79]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[79]
—
—
—
SIN_3
EIRQ[27]
SIUL
—
—
—
DSPI_3
SIUL
I/O
—
—
—
I
I
Slow
Medium
—
121
145
I/O
O
O
—
I
Slow
Medium
—
133
157
Port F
F[0]
PCR[80]
ALT0
ALT1
ALT2
ALT3
—
GPIO[80]
DBG_0
CS3_3
—
EIRQ[28]
SIUL
FlexRay_0
DSPI_3
—
SIUL
Doc ID 18340 Rev 3
43/104
Package pinouts and signal descriptions
Table 7.
Port
pin
F[1]
F[2]
F[3]
F[4]
F[5]
F[6]
F[7]
F[8]
F[9]
44/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[81]
ALT0
ALT1
ALT2
ALT3
—
GPIO[81]
DBG_1
CS2_3
—
EIRQ[29]
SIUL
FlexRay_0
DSPI_3
—
SIUL
I/O
O
O
—
I
Slow
Medium
—
135
159
PCR[82]
ALT0
ALT1
ALT2
ALT3
GPIO[82]
DBG_2
CS1_3
—
SIUL
FlexRay_0
DSPI_3
—
I/O
O
O
—
Slow
Medium
—
137
161
PCR[83]
ALT0
ALT1
ALT2
ALT3
GPIO[83]
DBG_3
CS0_3
—
SIUL
FlexRay_0
DSPI_3
—
I/O
O
I/O
—
Slow
Medium
—
139
167
PCR[84]
ALT0
ALT1
ALT2
ALT3
—
—
MDO[3]
—
—
—
nexus_0
—
—
—
O
—
Slow
Fast
—
4
4
PCR[85]
ALT0
ALT1
ALT2
ALT3
—
—
MDO[2]
—
—
—
nexus_0
—
—
—
O
—
Slow
Fast
—
5
13
PCR[86]
ALT0
ALT1
ALT2
ALT3
GPIO[86]
—
MDO[1]
—
SIUL
—
nexus_0
—
I/O
—
O
—
Slow
Fast
—
8
16
PCR[87]
ALT0
ALT1
ALT2
ALT3
GPIO[87]
—
MCKO
—
SIUL
—
nexus_0
—
I/O
—
O
—
Slow
Fast
—
19
27
PCR[88]
ALT0
ALT1
ALT2
ALT3
GPIO[88]
—
MSEO1
—
SIUL
—
nexus_0
—
I/O
—
O
—
Slow
Fast
—
20
28
PCR[89]
ALT0
ALT1
ALT2
ALT3
GPIO[89]
—
MSEO0
—
SIUL
—
nexus_0
—
I/O
—
O
—
Slow
Fast
—
23
31
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
F[10]
F[11]
F[12]
F[13]
F[14]
F[15]
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[90]
ALT0
ALT1
ALT2
ALT3
GPIO[90]
—
EVTO
—
SIUL
—
nexus_0
—
I/O
—
O
—
Slow
Fast
—
24
32
PCR[91]
ALT0
ALT1
ALT2
ALT3
GPIO[91]
EVTI
—
—
SIUL
nexus_0
—
—
I/O
I
—
—
Slow
Medium
—
25
33
PCR[92]
ALT0
ALT1
ALT2
ALT3
GPIO[92]
ETC[3]
—
—
SIUL
eTimer_1
—
—
I/O
I/O
—
—
Slow
Medium
—
106
130
PCR[93]
ALT0
ALT1
ALT2
ALT3
GPIO[93]
ETC[4]
—
—
SIUL
eTimer_1
—
—
I/O
I/O
—
—
Slow
Medium
—
112
136
PCR[94]
ALT0
ALT1
ALT2
ALT3
GPIO[94]
TXD
—
—
SIUL
LINFlex_1
—
—
I/O
O
—
—
Slow
Medium
—
115
139
PCR[95]
ALT0
ALT1
ALT2
ALT3
—
GPIO[95]
—
—
—
RXD
SIUL
—
—
—
LINFlex_1
I/O
—
—
—
I
Slow
Medium
—
113
137
Port G
G[0]
G[1]
PCR[96]
ALT0
ALT1
ALT2
ALT3
—
GPIO[96]
F[0]
—
—
EIRQ[30]
SIUL
FCCU
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
—
38
46
PCR[97]
ALT0
ALT1
ALT2
ALT3
—
GPIO[97]
F[1]
—
—
EIRQ[31]
SIUL
FCCU
—
—
SIUL
I/O
O
—
—
I
Slow
Medium
—
141
173
Doc ID 18340 Rev 3
45/104
Package pinouts and signal descriptions
Table 7.
Port
pin
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
G[8]
G[9]
46/104
SPC56xP54x, SPC56xP60x
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
PCR[98]
ALT0
ALT1
ALT2
ALT3
—
GPIO[98]
—
—
—
SIN_4
SIUL
—
—
—
DSPI_4
I/O
—
—
—
I
Slow
Medium
—
102
126
PCR[99]
ALT0
ALT1
ALT2
ALT3
GPIO[99]
—
SOUT_4
—
SIUL
—
DSPI_4
—
I/O
—
O
—
Slow
Medium
—
104
128
PCR[100]
ALT0
ALT1
ALT2
ALT3
GPIO[100]
—
SCK_4
—
SIUL
—
DSPI_4
—
I/O
—
I/O
—
Slow
Medium
—
100
124
PCR[101]
ALT0
ALT1
ALT2
ALT3
GPIO[101]
—
CS0_4
—
SIUL
—
DSPI_4
—
I/O
—
I/O
—
Slow
Medium
—
85
103
PCR[102]
ALT0
ALT1
ALT2
ALT3
GPIO[102]
—
CS1_4
—
SIUL
—
DSPI_4
—
I/O
—
O
—
Slow
Medium
—
98
122
PCR[103]
ALT0
ALT1
ALT2
ALT3
GPIO[103]
—
CS2_4
—
SIUL
—
DSPI_4
—
I/O
—
O
—
Slow
Medium
—
83
101
PCR[104]
ALT0
ALT1
ALT2
ALT3
—
GPIO[104]
—
CS3_4
—
SIUL
—
DSPI_4
—
I/O
—
O
—
Slow
Medium
—
81
97
PCR[105]
ALT0
ALT1
ALT2
ALT3
—
GPIO[105]
—
—
—
RXD
SIUL
—
—
—
FlexCAN_1
I/O
—
—
—
I
Slow
Medium
—
79
95
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 7.
Port
pin
Package pinouts and signal descriptions
Pin muxing(1) (continued)
PCR
register
Alternate
function
(2),(3)
Functions
(4)
I/O
direction
Peripheral
(5)
Pad speed(6)
Pin
SRC = 0 SRC = 1
LQFP LQFP LQFP
100
144 176(7)
G[10] PCR[106]
ALT0
ALT1
ALT2
ALT3
GPIO[106]
—
TXD
—
SIUL
—
FlexCAN_1
—
I/O
—
O
—
Slow
Medium
—
77
93
G[11] PCR[107]
ALT0
ALT1
ALT2
ALT3
GPIO[107]
—
—
—
SIUL
—
—
—
I/O
—
—
—
Slow
Medium
—
75
91
1. This table concerns Full-featured version. Please refer to “SPC56xP54/60 device configuration difference” table for
difference between Full-featured, and Airbag configuration.
2. ALT0 is the primary (default) function for each port after reset.
3. Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11  ALT3. This is intended to select
the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless of the values
selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
4. Module included on the MCU.
5. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMI[PADSELx] bitfields inside the SIUL module.
6. Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
7. LQFP176 available only as development package.
8. Weak pull down during reset.
Doc ID 18340 Rev 3
47/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3
Electrical characteristics
3.1
Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This can be done by the internal pull-up or pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution:
All of the following parameter values can vary depending on the application and must be
confirmed during silicon validation, silicon characterization or silicon reliability trial.
3.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 8.
Parameter classifications
Classification tag
Note:
48/104
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D
Those parameters are derived mainly from simulations.
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
3.3
Absolute maximum ratings
Table 9.
Absolute maximum ratings(1)
Conditions
Min
Max(2)
Unit
SR Digital ground
—
0
0
V
3.3 V / 5.0 V input/output supply
SR voltage with respect to ground
(VSS_HV)
—
–0.3
6.0
V
Input/output ground voltage with
respect to ground (VSS_HV)
—
–0.1
0.1
V
—
–0.3
6.0
VDD_HV_IOx +
0.3
V
–0.3
—
–0.1
0.1
V
—
–0.3
6.0
VDD_HV_IOx +
0.3
V
–0.3
–0.1
0.1
V
– 0.3
6.0
– 0.3
VDD_HV_IOx +
0.3
VDD_HV_REG
< 2.7 V
– 0.3
VDD_HV_REG
+ 0.3
VDD_HV_REG
> 2.7 V
– 0.3
6.0
ADC ground and low reference
SR voltage with respect to ground
(VSS_HV)
—
–0.1
0.1
V
Slope characteristics on all VDD
SR during power up(5) with respect to
ground (VSS_HV)
—
0.25
250
V/ms
—
–0.3
6.0
–0.3
VDD_HV_IOx +
0.3
VDD_HV_REG
< 2.7 V
VSS_HV_AD
0.3
VDD_HV_AD +
0.3
V
VDD_HV_REG
> 2.7 V
VSS_HV_AD
VDD_HV_AD
V
—
–10
10
mA
Symbol
VSS_HV
VDD_HV_IOx(3)
Parameter
VSS_HV_IOx
SR
VDD_HV_FL
3.3 V / 5.0 V code and data flash
SR memory supply voltage with respect
to ground (VSS_HV)
VSS_HV_FL
SR
Relative to
VDD_HV_IOx
Code and data flash memory ground
with respect to ground (VSS_HV)
VDD_HV_OSC
3.3 V / 5.0 V crystal oscillator
SR amplifier supply voltage with respect
to ground (VSS_HV)
VSS_HV_OSC
3.3 V / 5.0 V crystal oscillator
SR amplifier reference voltage with
respect to ground (VSS_HV)
VDD_HV_REG
—
3.3 V / 5.0 V voltage regulator supply
SR voltage with respect to ground
Relative to
(VSS_HV)
VDD_HV_IOx
VDD_HV_AD
VSS_HV_AD
TVDD(4)
VIN
VINAN
IINJPAD
3.3 V / 5.0 V ADC supply and high
SR reference voltage with respect to
ground (VSS_HV)
Voltage on any pin with respect to
SR ground (VSS_HV_IOx) with respect to
ground (VSS_HV)
Relative to
VDD_HV_IOx
—
V
V
Relative to
VDD_HV_IOx
V
SR Analog input voltage
SR
Injected input current on any pin
during overload condition
Doc ID 18340 Rev 3
49/104
Electrical characteristics
Table 9.
SPC56xP54x, SPC56xP60x
Absolute maximum ratings(1) (continued)
Symbol
Parameter
Conditions
Min
Max(2)
Unit
IINJSUM
SR
Absolute sum of all injected input
currents during overload condition
—
–50
50
mA
IVDD_LV
SR
Low voltage static current sink
through VDD_LV
—
—
155
mA
SR Storage temperature
—
–55
150
°C
SR Junction temperature under bias
—
–40
150
°C
TSTG
TJ
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3. The difference between each couple of voltage supplies must be less than 300 mV, |VDD_HV_IOy – VDD_HV_IOx | < 300 mV.
4. Ensure a monotonic supply ramp starting at ground level
5. Guaranteed by device validation
Figure 5 shows the constraints of the different power supplies.
Figure 5.
Power supplies constraints
VDD_HV_xxx
6.0V
-0.3V
VDD_HV_IOx
-0.3V
6.0V
The SPC56xP54/60 supply architecture provides an ADC supply that is managed
independently of standard VDD_HV supply. Figure 6 shows the constraints of the ADC power
supply.
50/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Figure 6.
Electrical characteristics
Independent ADC supply(d)
VDD_HV_AD
6.0V
-0.3V
VDD_HV_REG
2.7V
-0.3V
6.0V
3.4
Recommended operating conditions
Table 10.
Recommended operating conditions (5.0 V)
Symbol
VSS_HV
VDD_HV_IOx(2)
Parameter
SR Digital ground
SR
5.0 V input/output supply
voltage
VSS_HV_IOx
SR Input/output ground voltage
VDD_HV_FL
5.0 V code and data flash
SR
memory supply voltage
VSS_HV_FL
SR
Code and data flash
memory ground
VDD_HV_OSC
5.0 V crystal oscillator
SR
amplifier supply voltage
VSS_HV_OSC
SR
5.0 V crystal oscillator
amplifier reference voltage
Conditions
Min
Max(1)
Unit
—
0
0
V
—
4.5
5.5
V
—
0
0
V
—
4.5
5.5
Relative to
VDD_HV_IOx
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
—
0
0
—
4.5
5.5
Relative to
VDD_HV_IOx
—
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
V
d. Device design targets the removal of this conditions. To be confirmed by design during device validation.
Doc ID 18340 Rev 3
51/104
Electrical characteristics
Table 10.
SPC56xP54x, SPC56xP60x
Recommended operating conditions (5.0 V) (continued)
Symbol
VDD_HV_REG
Parameter
5.0 V voltage regulator
SR
supply voltage
VDD_HV_AD
SR
VSS_HV_AD
SR
VDD_LV_CORx
(3),(4)
VSS_LV_CORx(3)
TA
Min
Max(1)
—
4.5
5.5
Relative to
VDD_HV_IOx
ADC ground and low
reference voltage
Unit
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
—
4.5
5.0 V ADC supply and high
Relative to
reference voltage
V
– 0.1
VDD_HV_REG DD_HV_REG
5.5
V
—
—
0
0
V
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
—
–40
125
°C
VDD_LV_REGCOR(3),(4) SR Internal supply voltage
VSS_LV_REGCOR(3)
Conditions
SR
Ambient temperature under
bias
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 11.
Recommended operating conditions (3.3 V)
Symbol
VSS_HV
VDD_HV_IOx(2)
Parameter
SR Digital ground
SR
3.3 V input/output supply
voltage
VSS_HV_IOx
SR Input/output ground voltage
VDD_HV_FL
SR
VSS_HV_FL
SR
Code and data flash
memory ground
VDD_HV_OSC
SR
3.3 V crystal oscillator
amplifier supply voltage
VSS_HV_OSC
SR
52/104
3.3 V code and data flash
memory supply voltage
3.3 V crystal oscillator
amplifier reference voltage
Conditions
Min
Max(1)
Unit
—
0
0
V
—
3.0
3.6
V
—
0
0
V
—
3.0
3.6
Relative to
VDD_HV_IOx
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
—
0
0
—
3.0
3.6
Relative to
VDD_HV_IOx
—
Doc ID 18340 Rev 3
V
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
0
0
V
SPC56xP54x, SPC56xP60x
Table 11.
Electrical characteristics
Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
3.3 V voltage regulator
SR
supply voltage
VDD_HV_REG
Conditions
Min
Max(1)
—
3.0
3.6
Relative to
VDD_HV_IOx
—
VDD_HV_AD
SR
VSS_HV_AD
SR
3.3 V ADC supply and high
reference voltage
ADC ground and low
reference voltage
VSS_LV_REGCOR
VDD_LV_CORx(3),(4)
VSS_LV_CORx(3)
TA
V
VDD_HV_IOx – 0.1 VDD_HV_IOx + 0.1
3.0
Relative to
V
– 0.1
VDD_HV_REG DD_HV_REG
5.5
V
5.5
—
0
0
V
—
—
—
V
SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
—
–40
125
°C
VDD_LV_REGCOR(3),(4) SR Internal supply voltage
(3)
Unit
SR
Ambient temperature under
bias
1. Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full functionality.
In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2. The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | < 100 mV.
3. To be connected to emitter of external NPN. Low voltage supplies are not under user control—these are produced by an
on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must be shorted to
high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast
emitter.
4. The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the low
voltage supply to the data flash memory module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Figure 7 shows the constraints of the different power supplies.
Doc ID 18340 Rev 3
53/104
Electrical characteristics
Figure 7.
SPC56xP54x, SPC56xP60x
Power supplies constraints(e)
VDD_HV_xxx
5.5V
3.3V
3.2V
VDD_HV_IOx
3.2V
3.3V
5.5V
The SPC56xP54/60 supply architecture provides an ADC supply that is managed
independently of standard VDD_HV supply. Figure 8 shows the constraints of the ADC power
supply.
e. IO AC and DC characteristics are guaranteed only in the range 3.0V–3.6V when PAD3V5V is low, and in the
range 4.5V–5.5V when PAD3V5V is high.
54/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Figure 8.
Electrical characteristics
Independent ADC supply
VDD_HV_AD
5.5V
3.0V
VDD_HV_REG
3.0V
3.5
Thermal characteristics
Table 12.
Thermal characteristics for 144-pin LQFP
Symbol
Parameter
D
RJA
RJB
Conditions
D
Thermal resistance junction-to-ambient,
natural convection(1)
D
junction-to-board(2)
Thermal resistance
RJCtop
D
Thermal resistance junction-to-case (top)
JB
D
Junction-to-board, natural convection(4)
JC
5.5V
D
Junction-to-case, natural
convection(5)
(3)
Typical value
Unit
Single layer board—1s
53.4
°C/W
Four layer board—2s2p
43.9
°C/W
Four layer board—2s2p
29.6
°C/W
Single layer board—1s
9.3
°C/W
Operating conditions
29.8
°C/W
Operating conditions
1.3
°C/W
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.
Doc ID 18340 Rev 3
55/104
Electrical characteristics
Table 13.
Thermal characteristics for 100-pin LQFP
Symbol
Parameter
D
RJA
SPC56xP54x, SPC56xP60x
D
Conditions
Thermal resistance junction-to-ambient,
natural convection(1)
(2)
Single layer board—1s
47.3
°C/W
Four layer board—2s2p
35.6
°C/W
Four layer board—2s2p
19.1
°C/W
9.1
°C/W
Operating conditions
19.1
°C/W
Operating conditions
1.1
°C/W
RJB
D
Thermal resistance junction-to-board
RJCtop
D
Thermal resistance junction-to-case (top)(3) Single layer board—1s
JB
JC
D
D
Junction-to-board, natural convection
Junction-to-case, natural convection
(4)
(5)
Typical value Unit
1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification
for this package.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the board and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
5. Thermal characterization parameter indicating the temperature difference between the case and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JC.
3.5.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
Equation 1
TJ = TA + (RJA × PD)
where:
TA
= ambient temperature for the package (oC)
RJA
= junction to ambient thermal resistance (oC/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2
RJA = RJC + RCA
where:
56/104
RJA
= junction to ambient thermal resistance (°C/W)
RJC
= junction to case thermal resistance (°C/W)
RCA
= case to ambient thermal resistance (°C/W)
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
RJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (JT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3
TJ = TT + (JT × PD)
where:
TT
= thermocouple temperature on top of the package (°C)
JT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp.
47-54.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled
Applications, Electronic Packaging and Production, pp. 53-58, March 1998.
3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San
Diego, 1999, pp. 212-220.
Doc ID 18340 Rev 3
57/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3.6
Electromagnetic interference (EMI) characteristics
Table 14.
EMI testing specifications
Parameter
Symbol
Conditions
VDD = 5 V;
TA = 25 °C
VRE_TEM
Radiated
emissions,
electric field
150 kHz–30 MHz
RBW 9 kHz, Step
Size 5 kHz
30 MHz–1 GHz
RBW 120 kHz,
Step Size 80 kHz
fOSC/fBUS
Frequency
Unit
8 MHz crystal
150 kHz–150 MHz
64 MHz bus
150–1000 MHz
No PLL frequency
IEC Level
modulation
18
150 kHz–150 MHz
18
150–1000 MHz
12
IEC Level
M
—
Conditions
Value
Unit
2000
V
8 MHz crystal
64 MHz bus
±2% PLL
frequency
modulation
Electrostatic discharge (ESD) characteristics
Table 15.
ESD ratings(1),(2)
Parameter
dBV
12
M
—
dBV
3.7
Symbol
Level
(Max)
VESD(HBM)
SR Electrostatic discharge (Human Body Model)
—
VESD(CDM)
SR Electrostatic discharge (Charged Device Model)
—
750 (corners)
V
500 (other)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification
3.8
Power management electrical characteristics
3.8.1
Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast to be connected as shown in
Figure 9. Table 16 contains all approved NPN ballast components. Capacitances should be
placed on the board as near as possible to the associated pins. Care should also be taken
to limit the serial inductance of the VDD_HV_REG, BCTRL and VDD_LV_CORx pins to less than
LReg, see Table 17.
Note:
The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is not
possible to provide VDD_LV_COR through external regulator.
For the SPC56xP54/60 microcontroller, capacitors, with total values not below CDEC1,
should be placed between VDD_LV_CORx/VSS_LV_CORx close to external ballast transistor
emitter. 4 capacitors, with total values not below CDEC2, should be placed close to
microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
58/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitors with total values not below
CDEC3, should be placed between the VDD_HV_REG/VSS_HV_REG pins close to ballast
collector. Capacitors values have to take into account capacitor accuracy, aging and
variation versus temperature.
All reported information are valid for voltage and temperature ranges described in
recommended operating condition, Table 10 and Table 11.
Figure 9.
Voltage regulator configuration
VDD_HV_REG
SPC56xP54/60
CDEC3
BJT(1)
BCTRL
VDD_LV_COR
CDEC2
CDEC1
1. Refer to Table 16.
Table 16.
Approved NPN ballast components
Manufacturer
Approved derivatives(1)
ON Semi
BCP68
NXP
BCP68-25
Infineon
BCP68-25
BCX68
Infineon
BCX68-10;BCX68-16;BCX68-25
BC868
NXP
BC868
Infineon
BC817-16;BC817-25;BC817SU;
NXP
BC817-16;BC817-25
ST
BCP56-16
Infineon
BCP56-10;BCP56-16
ON Semi
BCP56-10
NXP
BCP56-10;BCP56-16
Part
BCP68
BC817
BCP56
1. For automotive applications please check with the appropriate transistor vendor for automotive grade
certification
Doc ID 18340 Rev 3
59/104
Electrical characteristics
Table 17.
SPC56xP54x, SPC56xP60x
Voltage regulator electrical characteristics
Value
Symbol
C
Parameter
Conditions
Unit
Min
Output voltage under
VDD_LV_REGCOR CC P maximum load run supply
current configuration
CDEC1
SR —
Post-trimming
1.15
—
1.32
V
BJT from Table 16. 3
capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF
19.5
30
—
µF
BJT BC817, one capacitance
of 22 µF
14.3
22
Resulting ESR of all three
capacitors of CDEC1
BJT from Table 16. 3x10 µF.
Absolute maximum value
between 100 kHz and
10 MHz
—
—
50
m
Resulting ESR of the unique
capacitor CDEC1
BJT BC817, 1x 22 µF.
Absolute maximum value
between 100 kHz and
10 MHz
10
—
40
m
External decoupling/stability
ceramic capacitor
4 capacitances (i.e. X7R or
X8R capacitors) with nominal 1200 1760
value of 440 nF
—
nF
3 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to
be equal or greater than
CDEC1
19.5
30
—
µF
—
—
—
15
nH
External decoupling/stability
ceramic capacitor
µF
SR —
RREG
CDEC2
SR —
CDEC3
External decoupling/stability
SR — ceramic capacitor on
VDD_HV_REG
SR —
LReg
3.8.2
Typ Max
Resulting ESL of VDD_HV_REG,
BCTRL and VDD_LV_CORx pins
Voltage monitor electrical characteristics
The device implements a Power On Reset module to ensure correct power-up initialization,
as well as three low voltage detectors to monitor the VDD and the VDD_LV voltage while
device is supplied:
60/104
●
POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state
●
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
●
LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
●
LVDLVCOR monitors low voltage digital power domain
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 18.
Electrical characteristics
Low voltage monitor electrical characteristics
Symbol
Parameter
Conditions(1)
Value
Unit
Min
Max
—
1.5
2.7
V
TA = 25°C
1.0
—
V
VPORH
T
Power-on reset threshold
VPORUP
P
Supply for functional POR module
VREGLVDMOK_H
P
Regulator low voltage detector high threshold
—
—
2.95
V
VREGLVDMOK_L
P
Regulator low voltage detector low threshold
—
2.6
—
V
VFLLVDMOK_H
P
Flash memory low voltage detector high threshold
—
—
2.95
V
VFLLVDMOK_L
P
Flash memory low voltage detector low threshold
—
2.6
—
V
VIOLVDMOK_H
P
I/O low voltage detector high threshold
—
—
2.95
V
VIOLVDMOK_L
P
I/O low voltage detector low threshold
—
2.6
—
V
VIOLVDM5OK_H
P
I/O 5V low voltage detector high threshold
—
—
4.4
V
VIOLVDM5OK_L
P
I/O 5V low voltage detector low threshold
—
3.8
—
V
VMLVDDOK_H
P
Digital supply low voltage detector high
—
—
1.15
V
VMLVDDOK_L
P
Digital supply low voltage detector low
—
1.08
—
V
1. VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
3.9
Power Up/Down sequencing
To prevent an overstress event or a malfunction within and outside the device, the
SPC56xP54/60 implements the following sequence to ensure each module is started only
when all conditions for switching it ON are available:
1.
A POWER_ON module working on voltage regulator supply controls the correct startup of the regulator. This is a key module ensuring safe configuration for all voltage
regulator functionality when supply is below 1.5V. Associated POWER_ON (or POR)
signal is active low.
–
Several low voltage detectors, working on voltage regulator supply monitor the
voltage of the critical modules (voltage regulator, I/Os, flash memory and low
voltage domain). LVDs are gated low when POWER_ON is active.
–
A POWER_OK signal is generated when all critical supplies monitored by the LVD
are available. This signal is active high and released to all modules including I/Os,
flash memory and RC16 oscillator needed during power-up phase and reset
phase. When POWER_OK is low the associated modules are set into a safe state.
Doc ID 18340 Rev 3
61/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 10. Power-up typical sequence
VPORH
VDD_HV_REG
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VMLVDOK_H
VDD_LV_REGCOR
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
~1us
Internal Reset Generation Module
FSM
Figure 11.
1.2V
0V
P0
P1
1.2V
0V
Power-down typical sequence
VLVDHV3L
VDD_HV_REG
VPORH
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
62/104
P0
Doc ID 18340 Rev 3
1.2V
0V
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 12. Brown-out typical sequence
VLVDHV3L
VLVDHV3H
3.3V
VDD_HV_REG
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
IDLE
3.10
P0
P1
1.2V
0V
NVUSRO register
Portions of the device configuration, such as high voltage supply, and watchdog
enable/disable after reset are controlled via bit values in the non-volatile user options
register (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
3.10.1
NVUSRO[PAD3V5V] field description
Table 19 shows how NVUSRO[PAD3V5V] controls the device configuration.
Table 19.
PAD3V5V field description(1)
Value(2)
Description
0
High voltage supply is 5.0 V
1
High voltage supply is 3.3 V
1. See the device reference manual for more information on the NVUSRO register.
2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
Doc ID 18340 Rev 3
63/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3.11
DC electrical characteristics
3.11.1
DC electrical characteristics (5 V)
Table 20 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V,
NVUSRO[PAD3V5V]=0) as described in Figure 13.
Figure 13. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
Table 20.
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
Parameter
Conditions
Min
Max
Unit
VIL
D Minimum low level input voltage
—
–0.1(1)
—
V
VIL
P Maximum level input voltage
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
V
(1)
D Maximum high level input voltage
—
—
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_S
P Slow, high level output voltage
IOH = –3 mA
0.8VDD_HV_IOx
—
V
VOL_M
P Medium, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_M
P Medium, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
VOL_F
P Fast, low level output voltage
IOL = 3 mA
—
0.1 VDD_HV_IOx
V
VOH_F
P Fast, high level output voltage
IOH = –3 mA
0.8 VDD_HV_IOx
—
V
—
0.1 VDD_HV_IOx
V
0.8 VDD_HV_IOx
—
V
VIH
VOL_SYM P
Symmetric, low level output
voltage
IOL = 3 mA
VOH_SYM P
Symmetric, high level output
voltage
IOH = –3 mA
64/104
Doc ID 18340 Rev 3
VDD_HV_IOx + 0.1
V
SPC56xP54x, SPC56xP60x
Table 20.
Electrical characteristics
DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0) (continued)
Symbol
Parameter
Conditions
Min
Max
VIN = VIL
–130
—
VIN = VIH
—
–10
VIN = VIL
10
—
VIN = VIH
—
130
Unit
IPU
P Equivalent pull-up current
IPD
P Equivalent pull-down current
IIL
P
Input leakage current
(all bidirectional ports)
TA = –40 to 125 °C
–1
1
µA
IIL
P
Input leakage current
(all ADC input-only ports)
TA = –40 to 125 °C
–0.5
0.5
µA
CIN
D Input capacitance
—
—
10
pF
—
D RESET, equivalent pull-up current
VIN = VIL
–130
IPU
VIN = VIH
—
–10
—
D
VIN = VIL
10
IPD
VIN = VIH
—
130
RESET, equivalent pull-down
current
µA
µA
µA
µA
1. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
Doc ID 18340 Rev 3
65/104
Electrical characteristics
Table 21.
SPC56xP54x, SPC56xP60x
Supply current (5.0 V, NVUSRO[PAD3V5V]=0)
Value
Symbol
Parameter
Conditions
Max
64 MHz
90
120
16 MHz
21
37
40 MHz
35
55
64 MHz
48
72
16 MHz
24
41
40 MHz
42
64
64 MHz
58
85
VDD_LV_CORE
externally forced at 1.3 V
64 MHz
85
113
HALT Mode(5)
VDD_LV_CORE
externally forced at 1.3 V
—
5.5
15
STOP Mode(6)
VDD_LV_CORE
externally forced at 1.3 V
—
4.5
13
Flash memory supply current
during read
VDD_HV_FL at 5.0 V
—
—
14
Flash memory supply current
during erase operation on 1
flash memory module
VDD_HV_FL at 5.0 V
—
—
42
—
3
4
8 MHz
2.6
3.2
RUN — Maximum Mode(1)
VDD_LV_CORE
externally forced at 1.3 V
ADC Freq = 32 MHz
PLL Freq = 64 MHz
RUN - Platform consumption,
single core(2)
T
VDD_LV_CORE
externally forced to 1.3V
IDD_LV_CORE
RUN - Platform consumption,
dual core(3)
Supply
current
P
IDD_FLASH
T
Unit
Typ
RUN — Maximum Mode(4)
IDD_ADC
T
ADC supply current —
Maximum Mode
VDD_HV_AD at 5.0 V
ADC Freq = 16 MHz
IDD_OSC
T
OSC supply current
VDD_OSC at 5.0 V
mA
1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM
enabled. I/O supply current excluded.
2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz
on, PLL64MHz OFF(except for code running at 64MHz).
Code is performing continous data transfet from Flash to RAM.
3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,
PLL64MHz OFF(except for code running at 64MHz).
Code is performing continous data transfet from Flash to RAM.
4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM
enabled. I/O supply current excluded.
5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in
power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL
are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
66/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
3.11.2
Electrical characteristics
DC electrical characteristics (3.3 V)
Table 22 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V,
NVUSRO[PAD3V5V]=1) as described in Figure 14.
Figure 14. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
PDIx = ‘1’
(GPDI register of SIUL)
PDIx = ‘0’
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)(1)
Table 22.
Symbol
Parameter
Conditions
Min
Max
Unit
VIL
D Minimum low level input voltage
—
–0.1(2)
—
V
VIL
P Maximum low level input voltage
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
V
D Maximum high level input voltage
—
—
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_S
P Slow, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
0.5
V
VOH_M
P Medium, high level output voltage IOH = –2 mA
VDD_HV_IOx – 0.8
—
V
VOL_F
P Fast, high level output voltage
IOL = 1.5 mA
—
0.5
V
VOH_F
P Fast, high level output voltage
IOH = –1.5 mA
VDD_HV_IOx – 0.8
—
V
—
0.5
V
VDD_HV_IOx – 0.8
—
V
VIN = VIL
–130
—
VIN = VIH
—
–10
VIH
VOL_SYM P
Symmetric, high level output
voltage
IOL = 1.5 mA
VOH_SYM P
Symmetric, high level output
voltage
IOH = –1.5 mA
IPU
P Equivalent pull-up current
Doc ID 18340 Rev 3
VDD_HV_IOx +
0.1(2)
V
µA
67/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)(1) (continued)
Table 22.
Symbol
Parameter
Conditions
Min
Max
VIN = VIL
10
—
VIN = VIH
—
130
Unit
IPD
P Equivalent pull-down current
IIL
P
Input leakage current
(all bidirectional ports)
TA = –40 to 125 °C
—
1
µA
IIL
P
Input leakage current
(all ADC input-only ports)
TA = –40 to 125 °C
—
0.5
µA
CIN
D Input capacitance
—
—
10
pF
—
D RESET, equivalent pull-up current
VIN = VIL
–130
IPU
VIN = VIH
—
–10
—
D
VIN = VIL
10
IPD
VIN = VIH
—
130
RESET, equivalent pull-down
current
µA
µA
µA
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
68/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 23.
Electrical characteristics
Supply current (3.3 V, NVUSRO[PAD3V5V]=1)
Value
Symbol
Parameter
Conditions
Max
64 MHz
90
120
16 MHz
21
37
40 MHz
35
55
64 MHz
VDD_LV_CORE
externally forced to 1.3V 16 MHz
48
72
24
41
40 MHz
42
64
64 MHz
58
85
VDD_LV_CORE
externally forced at
1.3 V
64 MHz
85
113
HALT Mode(5)
VDD_LV_CORE
externally forced at
1.3 V
—
5.5
15
STOP Mode(6)
VDD_LV_CORE
externally forced at
1.3 V
—
4.5
13
Flash memory supply current
during read
VDD_HV_FL at 3.3 V
—
—
14
Flash memory supply current
during erase operation on 1
flash memory module
VDD_HV_FL at 3.3 V
—
—
42
—
3
4
8 MHz
2.4
3
RUN — Maximum Mode(1)
T
RUN - Platform consumption,
dual core(3)
Supply
current
P
IDD_FLASH
VDD_LV_CORE
externally forced at
1.3 V
ADC Freq = 32 MHz
PLL Freq = 64 MHz
RUN - Platform consumption,
single core(2)
IDD_LV_CORE
D
Unit
Typ
RUN — Maximum Mode(4)
IDD_ADC
T
ADC supply current —
Maximum Mode
VDD_HV_AD at 3.3 V
ADC Freq = 16 MHz
IDD_OSC
T
OSC supply current
VDD_OSC at 3.3 V
mA
1. Maximum mode configuration: Code fetched from Flash executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM
enabled. I/O supply current excluded.
2. RAM, Code and Data Flash powered, code fetched from Flash executed by single core, all peripherals gated; IRC16MHz
on, PLL64MHz OFF(except for code running at 64MHz).
Code is performing continous data transfet from Flash to RAM.
3. RAM, Code and Data Flash powered, code fetched from Flash executed by dual core, all peripherals gated; IRC16MHz on,
PLL64MHz OFF(except for code running at 64MHz).
Code is performing continous data transfet from Flash to RAM.
4. Maximum mode configuration: Code fetched from RAM executed by dual core, SIUL, PIT, ADC_0, eTimer_0/1,
LINFlex_0/1, STM, INTC_0/1, DSPI_0/1/2/3/4, FlexCAN_0/1, FlexRay (static consumption), CRC_0/1, FCCU, SRAM
enabled. I/O supply current excluded.
5. HALT mode configuration, only for the “P” classification: Code Flash memory in low power mode, data Flash memory in
power down mode, OSC/PLL are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
6. STOP mode configuration, only for the “P” classification: Code and data Flash memories in power down mode, OSC/PLL
are OFF, FIRC is ON, Core clock gated, all peripherals are disabled.
Doc ID 18340 Rev 3
69/104
Peripherals supply current (5 V and 3.3 V)(1)
Value
Symbol
Parameter
Conditions
Total (static + dynamic)
consumption:
• FlexCAN in loop-back mode
• XTAL@ 8 MHz used as CAN
engine clock source
• Message sending period is 580
µs
Unit
Typ
Max
21.6 * fperiph
28.1* fperiph
Doc ID 18340 Rev 3
IDD_BV(CAN)
T CAN (FlexCAN)
supply current on
VDD_BV
500 Kbyte/s
IDD_BV(SCI)
T SCI (LINFlex) supply
current on VDD_BV
Total (static + dynamic) consumption:
• LIN mode
• Baudrate: 115.2 Kbyte/s
10.8 * fperiph
14.1 * fperiph
IDD_BV(SPI)
T SPI (DSPI) supply
current on VDD_BV
Ballast dynamic consumption (continuous
communication):
• Baudrate: 2 Mbit/s
• Transmission every 8 µs
• Frame: 16 bits
4.8 * fperiph
6.3 * fperiph
IDD_BV(ADC)
T ADC supply current
on VDD_BV
VDD = 5.5 V
Ballast dynamic consumption
(continuous conversion)
120 * fperiph
156 * fperiph
IDD_HV_ADC(ADC) T ADC supply current
on VDD_HV_ADC
VDD = 5.5 V
Analog dynamic consumption
(continuous conversion)
T eTimer supply current PWM signals generation on Dynamic consumption does not
on VDD_BV
all 1 channel @10kHz
change varying the frequency
IDD_BV(FlexRay)
T FlexRay supply
current on VDD_BV
Static consumption
1. Operating conditions: fperiph = 8 MHz to 64 MHz
0.005 * fperiph + 2.8 0.007 * fperiph + 3.4 mA
1.8
2.4
mA
4.2 * fperiph
5.5 * fperiph
µA
SPC56xP54x, SPC56xP60x
IDD_BV(eTimer)
µA
Electrical characteristics
70/104
Table 24.
SPC56xP54x, SPC56xP60x
3.11.3
Electrical characteristics
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 25.
Table 25.
I/O supply segment
Supply segment
Package
1
2
3
4
5
6
7
LQFP144
pin8 – pin20
pin23 –
pin38
pin39 –
pin55
pin58 –
pin68
pin73 –
pin89
pin92 –
pin125
pin128 –
pin5
LQFP100
pin15 –
pin26
pin27 –
pin38
pin41 –
pin46
pin51 –
pin61
pin64 –
pin86
pin89 – pin10
—
Table 26.
Symbol
ISWTSLW(2)
ISWTMED
(2)
ISWTFST(2)
I/O consumption
C
Dynamic I/O current
CC D for SLOW
CL = 25 pF
configuration
Dynamic I/O current
CC D for MEDIUM
CL = 25 pF
configuration
Dynamic I/O current
CC D for FAST
CL = 25 pF
configuration
CL = 25 pF, 4 MHz
Typ
Max
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
20
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
16
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
29
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
17
VDD = 5.0 V ± 10%,
PAD3V5V = 0
—
—
110
VDD = 3.3 V ± 10%,
PAD3V5V = 1
—
—
50
—
—
2.3
—
—
3.2
—
—
6.6
—
—
1.6
—
—
2.3
—
—
4.7
—
—
6.6
—
—
13.4
—
—
18.3
—
—
5
—
—
8.5
—
—
11
mA
mA
mA
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Root medium square C = 100 pF, 2 MHz
L
CC D I/O current for SLOW
CL = 25 pF, 2 MHz
configuration
CL = 25 pF, 4 MHz
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF, 2 MHz
CL = 25 pF, 13 MHz
VDD = 5.0 V ± 10%,
PAD3V5V = 0
IRMSMED
Unit
Min
CL = 25 pF, 2 MHz
IRMSSLW
Value
Conditions(1)
Parameter
CL = 25 pF, 40 MHz
Root medium square
CL = 100 pF, 13 MHz
I/O current for
CC D
MEDIUM
CL = 25 pF, 13 MHz
configuration
VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz
PAD3V5V = 1
CL = 100 pF, 13 MHz
Doc ID 18340 Rev 3
mA
71/104
Electrical characteristics
Table 26.
Symbol
SPC56xP54x, SPC56xP60x
I/O consumption (continued)
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
—
—
22
—
—
33
—
—
56
—
—
14
—
—
20
CL = 100 pF, 40 MHz
—
—
35
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
70
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
65
CL = 25 pF, 40 MHz
CL = 25 pF, 64 MHz
IRMSFST
Root medium square C = 100 pF, 40 MHz
L
CC D I/O current for FAST
CL = 25 pF, 40 MHz
configuration
CL = 25 pF, 64 MHz
IAVGSEG
VDD = 5.0 V ± 10%,
PAD3V5V = 0
Sum of all the static
SR D I/O current within a
supply segment
mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
3.12
Main oscillator electrical characteristics
The SPC56xP54/60 provides an oscillator/resonator driver.
Table 27.
Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0)
Symbol
fOSC
Parameter
SR Oscillator frequency
gm
P
Transconductance
VOSC
T
Oscillation amplitude on EXTAL pin
tOSCSU
T
Start-up
time(1),(2)
Min
Max
Unit
4
40
MHz
6.5
25
mA/V
1
—
V
8
—
ms
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of EXTAL
Table 28.
Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1)
Symbol
fOSC
Parameter
SR Oscillator frequency
Min
Max
Unit
4
40
MHz
gm
P
Transconductance
4
20
mA/V
VOSC
T
Oscillation amplitude on EXTAL pin
1
—
V
tOSCSU
T
Start-up time(1),(2)
8
—
ms
1. The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive
capacitive loads can cause long start-up time.
2. Value captured when amplitude reaches 90% of EXTAL
72/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 29.
Electrical characteristics
Input clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fOSC
SR
Oscillator frequency
4
—
40
MHz
fCLK
SR
Frequency in bypass
—
—
64
MHz
trCLK
SR
Rise/fall time in bypass
—
—
1
ns
tDC
SR
Duty cycle
47.5
50
52.5
%
3.13
FMPLL electrical characteristics
Table 30.
PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
Parameter
Conditions
Unit
min
max
4
40
MHz
fref_crystal
fref_ext
D
PLL reference frequency range(1)
fpll_in
D
Phase detector input frequency range
(after pre-divider)
—
4
16
MHz
fFMPLLOUT
D
Clock frequency range in normal mode
—
4
120
MHz
fFREE
P
Free running frequency
20
150
MHz
fsys
D
On-chip PLL frequency
—
16
64
MHz
tCYC
D
System clock period
—
—
1 / fsys
ns
fLORL
fLORH
Loss of reference frequency window(2)
Lower limit
1.6
3.7
D
Upper limit
24
56
fSCM
D
—
20
150
MHz
fSYS maximum
–4
4
% fCLKOUT
fPLLIN = 16 MHz
(resonator),
fPLLCLK at 64 MHz,
4000 cycles
—
10
ns
Crystal reference
Measured using
clock division —
typically /16
MHz
Self-clocked mode frequency(3),(4)
(9)
Short-term jitter
CLKOUT
period
Long-term jitter (avg.
jitter(5),(6),(7),(8) over 2 ms interval)
CJITTER
T
tlpll
D
PLL lock time (10), (11)
—
—
200
µs
tdc
D
Duty cycle of reference
—
40
60
%
fLCK
D
Frequency LOCK range
—
–6
6
% fsys
fUL
D
Frequency un-LOCK range
—
–18
18
% fsys
fCS
fDS
Center spread
±0.25
±4.0(12)
D
Modulation Depth
Down Spread
–0.5
–8.0
fMOD
D
—
70
Modulation frequency(13)
—
%fsys
kHz
1. Considering operation with PLL not bypassed.
Doc ID 18340 Rev 3
73/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
2. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
3. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
4. fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced
mode.
5. This value is determined by the crystal manufacturer and board design.
6. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
7. Proper PC board layout procedures must be followed to achieve specifications.
8. Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER
and either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
9. Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits.
11. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
12. This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
13. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.14
16 MHz RC oscillator electrical characteristics
Table 31.
16 MHz RC oscillator electrical characteristics
Symbol
fRC
Parameter
Conditions
Min
Typ
Max
Unit
TA = 25 °C
—
16
—
MHz
—
–6
—
6
%
P
RC oscillator frequency
RCMVAR
P
Fast internal RC oscillator variation
over temperature and
supply with respect to fRC at TA = 25 °C
in high-frequency configuration
RCMTRIM
T
Post Trim Accuracy: The variation of
the PTF(1) from the 16 MHz
TA = 25 °C
–1
—
1
%
RCMSTEP
T
Fast internal RC oscillator trimming
step
TA = 25 °C
—
1.6
—
%
1. PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
3.15
Analog-to-Digital converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital
Converter.
74/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 15. ADC characteristics and error definitions
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(2) The ideal transfer curve
(5)
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
3.15.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high-frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuate the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a highimpedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the source
impedance value of the transducer or circuit supplying the analog signal to be measured.
Doc ID 18340 Rev 3
75/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
The filter at the input pins must be designed taking into account the dynamic characteristics
of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and CP2 substantially two switched capacitances, with a
frequency equal to the ADC conversion rate, it can be seen as a resistive path to ground.
For instance, assuming a conversion rate of 1 MHz, with CS + CP2 equal to 3 pF, a
resistance of 330 k is obtained (REQ = 1 / (fc × (CS + CP2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS + CP2) and the sum of RS + RF
, the external circuit must be designed to respect the Equation 4:
Equation 4
RS + RF 1
V A  ---------------------  --- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive
path. Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
Figure 16. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
CP1
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
76/104
Doc ID 18340 Rev 3
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 17. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
RF
Current Limiter
RL
CF
VA
CP1
Channel
Selection
Extended
Switch
Sampling
RSW1
RSW2
RAD
CP3
CP2
CS
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch close).
Figure 18. Transient behavior during sampling phase
Voltage Transient on CS
VCS
VA
VA2
V <0.5 LSB
1
2
1 < (RSW + RAD) CS << TS
2 = RL (CS + CP1 + CP2)
VA1
TS
Doc ID 18340 Rev 3
t
77/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
In particular two different transient periods can be distinguished:
●
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
CP  CS
 1 =  R SW + R AD   ---------------------CP + CS
Equation 5 can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
Equation 6
 1   R SW + R AD   C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:
Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 
●
A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
Equation 8
 2  R L   C S + C P1 + C P2 
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraint on
RL sizing is obtained:
Equation 9
8.5   2 = 8.5  R L   C S + C P1 + C P2   TS
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):
Equation 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
78/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Figure 19. Spectral representation of input signal
Analog Source Bandwidth (VA)
TC 2 RFCF (Conversion Rate vs. Filter Pole)
fF  f0 (Anti-aliasing Filtering Condition)
Noise
2 f0 fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
Sampled Signal Spectrum (fC = conversion Rate)
f0
f
fC
f
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period TC is longer than the sampling time
TS, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time TS, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
Equation 11
VA
C P1 + C P2 + C F
--------- = ------------------------------------------------------C P1 + C P2 + C F + C S
V A2
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
Equation 12
C F  2048  C S
Doc ID 18340 Rev 3
79/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3.15.2
ADC conversion characteristics
Table 32.
ADC conversion characteristics
Symbol
VINAN
fCK
fs
tADC_S
Parameter
Value
Conditions(1)
Unit
Min
Typ
Max
SR Analog input voltage(2)
—
VSS_HV_AD
0.3
—
VSS_HV_AD
+ 0.3
V
ADC Clock frequency
(depends on ADC
SR configuration)
(The duty cycle depends
on AD_clk(3) frequency)
—
3(4)
—
60
MHz
SR Sampling frequency
—
—
—
1.53
MHz
fADC = 20 MHz,
INPSAMP = 3
125
—
—
ns
fADC = 9 MHz,
INPSAMP = 255
—
—
28.2
µs
0.650
—
—
µs
D
Sample time(5)
fADC = 20 MHz(7),
INPCMP = 1
tADC_C
P
Conversion time(6)
CS(8)
D
ADC input sampling
capacitance
—
—
—
2.5
pF
CP1(8)
D
ADC input pin capacitance
1
—
—
—
3
pF
CP2(8)
D
ADC input pin capacitance
2
—
—
—
1
pF
CP3(8)
D
ADC input pin capacitance
3
—
—
—
1
pF
RSW1(8)
Internal resistance of
analog source
VDD_HV_AD = 5 V ±10%
—
—
0.6
k
D
VDD_HV_AD = 3.3 V ±10%
—
—
3
k
RSW2(8)
VDD_HV_AD = 5 V ±10%
—
—
2.15
k
D
VDD_HV_AD = 3.3 V ±10%
—
—
3.6
k
RAD(8)
D
Internal resistance of
analog source
Internal resistance of
analog source
—
—
—
2
k
–5
—
5
mA
IINJ
T
Input current injection
Current injection on one ADC
input, different from the
converted one. Remains within
TUE spec.
INL
P
Integral Non Linearity
No overload
—
±1.5
—
LSB
DNL
P
Differential Non Linearity
No overload
–1.0
—
1.0
LSB
OFS
T
Offset error
—
—
±1
—
LSB
GNE
T
Gain error
—
—
±1
—
LSB
TUE
P
Total unadjusted error
without current injection
–2.5
—
2.5
LSB
80/104
16 precision channels
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 32.
Electrical characteristics
ADC conversion characteristics (continued)
Symbol
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
TUE
T
Total unadjusted error with
16 precision channels
current injection
–3
—
3
LSB
TUE
T
Total unadjusted error with
10 standard channels
current injection
–4
—
4
LSB
1. VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage from
VSS_HV_AD to VDD_HV_AD.
2. VINAN may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
3. AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
4. When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the
sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tADC_S depend on programming.
6. This parameter includes the sample time tADC_S.
7. 20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
8. See Figure 16.
3.16
Flash memory electrical characteristics
Table 33.
Program and erase specifications
Value
Symbol
Parameter
Conditions
Min Typ(1)
Unit
Initial
Max(3)
max(2)
Twprogram
P Word Program (32 bits) Time(4)
Data Flash
—
30
70
500
µs
Tdwprogram
P Double Word (64 bits) Program Time(4)
Code Flash
—
18
50
500
µs
P Bank Program (64
TBKPRG
TMDPRG
KB)(4), (5)
P Bank Program (1056
Data Flash
—
0.49
1.2
4.1
s
KB)(4), (5)
Code Flash
—
2.6
6.6
66
s
KB)(4)
Code Flash
—
1.3
1.65
33
s
200
500
5000
ms
700
800
P Module Program (512
Code Flash
T16kpperase
P 16 KB Block Pre-program and Erase Time
T32kpperase
P 32 KB Block Pre-program and Erase Time
Code Flash
—
300
600
5000
ms
T64kpperase
P 64 KB Block Pre-program and Erase Time
Code Flash
—
400
900
5000
ms
Code Flash
—
600
1300
5000
ms
Code Flash
20
—
—
—
ms
Data Flash
10
Data Flash
T128kpperase P 128 KB Block Pre-program and Erase Time
tESRT
—
P Erase Suspend Request Rate(6)
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
Doc ID 18340 Rev 3
81/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Typical bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will require
more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
6. Time between erase suspend resume and next erase suspend.
Table 34.
Flash memory module life
Value
Symbol
Parameter
Conditions
Unit
Min
Typ
P/E
Number of program/erase cycles per block
C for 16 KB blocks over the operating
temperature range (TJ)
—
100000
100000
cycles
P/E
Number of program/erase cycles per block
C for 32 KB blocks over the operating
temperature range (TJ)
—
10000
100000
cycles
P/E
Number of program/erase cycles per block
C for 64 KB blocks over the operating
temperature range (TJ)
—
10000
100000
cycles
P/E
Number of program/erase cycles per block
C for 128 KB blocks over the operating
temperature range (TJ)
—
1000
100000
cycles
Blocks with 0 – 1000
P/E cycles
20
—
years
Blocks with 10000 P/E
cycles
10
—
years
Blocks with 100000 P/E
cycles
5
—
years
Retention
C
Minimum data retention at 85 °C average
ambient temperature(1)
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.
Table 35.
Flash read access timing
Symbol
C
Fmax
C
Fmax
C
Parameter
Maximum working frequency for Code Flash
at given number of WS in worst conditions
Maximum working frequency for Data Flash at
given number of WS in worst conditions
Conditions(1)
Max
2 wait states
66
0 wait states
22
8 wait states
66
MHz
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
82/104
Doc ID 18340 Rev 3
Unit
MHz
SPC56xP54x, SPC56xP60x
Electrical characteristics
3.17
AC specifications
3.17.1
Pad AC specifications
Table 36.
Output pin transition times
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min Typ Max
Ttr
CC D Output transition time output pin(2) CL = 25 pF
SLOW configuration
T
CL = 50 pF
Ttr
—
50
—
—
100
—
—
125
—
—
40
—
—
50
—
—
75
—
—
10
—
—
20
—
—
40
—
—
12
—
—
25
—
—
40
—
—
4
—
—
6
—
—
12
—
—
4
—
—
7
CL = 100 pF
—
—
12
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
4
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
5
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
VDD = 3.3 V ± 10%,
PAD3V5V = 1
CL = 100 pF
D
Ttr
—
D
VDD = 5.0 V ± 10%,
PAD3V5V = 0
CC D Output transition time output
MEDIUM configuration
T
pin(2)
CL = 25 pF
CL = 50 pF
D
CL = 100 pF
D
CL = 25 pF
T
CL = 50 pF
D
CL = 100 pF
CC D Output transition time output pin(2) CL = 25 pF
FAST configuration
CL = 50 pF
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
CL = 100 pF
CL = 25 pF
CL = 50 pF
Tsim
(3)
CC T Symmetric, same drive strength
between N and P transistor
VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
ns
ns
ns
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2. CL includes device and package capacitances (CPKG < 5 pF).
3. Transition timing of both positive and negative slopes will differ maximum 50%
3.18
AC timing characteristics
3.18.1
RESET pin characteristics
The SPC56xP54/60 implements a dedicated bidirectional RESET pin.
Doc ID 18340 Rev 3
83/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 20. Start-up reset requirements(f)
VDD
VDDMIN
VRESET
VIH
VIL
device reset forced by VRESET
device start-up phase
TPOR
Figure 21. Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
f.
The output drive provided is open drain and hence must be terminated by an external resistor of value 1 k
84/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 37.
Electrical characteristics
RESET electrical characteristics
Symbol
C
Value
Conditions(1)
Parameter
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
—
0.4
—
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
—
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
—
—
0.5
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
10
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
—
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
—
—
40
—
—
—
40
ns
—
500
—
—
ns
Monotonic VDD_HV supply ramp
—
—
1
ms
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
10
—
250
VOL
Ttr
WFRST
CC P Output low level
Output transition time
CC D output pin(3)
MEDIUM configuration
SR P RESET input filtered pulse
WNFRST SR P
RESET input not filtered
pulse
TPOR
maximum delay before
internal reset is released
CC D
after all VDD_HV reach
nominal supply
|IWPU|
Weak pull-up current
CC P
absolute value
VDD = 5.0 V ± 10%, PAD3V5V =
1(4)
V
ns
µA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device
reference manual).
3. CL includes device and package capacitance (CPKG < 5 pF).
4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Doc ID 18340 Rev 3
85/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
3.18.2
IEEE 1149.1 interface timing
Table 38.
JTAG pin AC electrical characteristics
No.
Symbol
C
Parameter
Conditions Min Max Unit
1
tJCYC
CC D TCK cycle time
—
100
—
ns
2
tJDC
CC D TCK clock pulse width (measured at VDD_HV_IOx/2)
—
40
60
ns
3
tTCKRISE
CC D TCK rise and fall times (40% – 70%)
—
—
3
ns
4
tTMSS, tTDIS CC D TMS, TDI data setup time
—
5
—
ns
5
tTMSH, tTDIH CC D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
CC D TCK low to TDO data valid
—
—
40
ns
7
tTDOI
CC D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
CC D TCK low to TDO high impedance
—
40
—
ns
9
tBSDV
CC D TCK falling edge to output valid
—
—
50
ns
10
tBSDVZ
CC D TCK falling edge to output valid out of high impedance
—
—
50
ns
11
tBSDHZ
CC D TCK falling edge to output high impedance
—
—
50
ns
12
tBSDST
CC D Boundary scan input valid to TCK rising edge
—
50
—
ns
13
tBSDHT
CC D TCK rising edge to boundary scan input invalid
—
50
—
ns
Figure 22. JTAG test clock input timing
TCK
2
3
2
1
86/104
3
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 23. JTAG test access port timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Doc ID 18340 Rev 3
87/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 24. JTAG boundary scan timing
TCK
9
11
Output
Signals
10
Output
Signals
12
13
Input
Signals
3.18.3
Nexus timing
Table 39.
Nexus debug port timing(1)
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
32
—
—
ns
1
tMCYC
CC D MCKO cycle time
2
tMDOV
CC D MCKO edge to MDO data valid
–
0.1 × tMCYC
—
0.25 × tMCYC
ns
3
tMSEOV
CC D MCKO edge to MSEO data valid
–
0.1 × tMCYC
—
0.25 × tMCYC
ns
4
tEVTOV
CC D MCKO edge to EVTO data valid
–
0.1 × tMCYC
—
0.25 × tMCYC
ns
5
tTCYC
CC D TCK cycle time
64(2)
—
—
ns
88/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Nexus debug port timing(1) (continued)
Table 39.
Value
No.
6
7
Symbol
C
Parameter
Unit
Min
Typ
Max
tNTDIS
CC D TDI data setup time
6
—
—
ns
tNTMSS
CC D TMS data setup time
6
—
—
ns
tNTDIH
CC D TDI data hold time
10
—
—
ns
tNTMSH
CC D TMS data hold time
10
—
—
ns
8
tTDOV
CC D TCK low to TDO data valid
—
—
35
ns
9
tTDOI
CC D TCK low to TDO data invalid
6
—
—
ns
1. All values need to be confirmed during device validation.
2. Lower frequency is required to be fully compliant to standard.
Figure 25. Nexus output timing
1
MCKO
2
3
4
MDO
MSEO
EVTO
Output Data Valid
Figure 26. Nexus event trigger and test clock timings
TCK
EVTI
EVTO
5
Doc ID 18340 Rev 3
89/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 27. Nexus TDI, TMS, TDO timing
TCK
6
7
TMS, TDI
9
8
TDO
3.18.4
External interrupt timing (IRQ pin)
Table 40.
External interrupt timing(1)
No.
Symbol
C
Parameter
Conditions
Min
Max
Unit
1
tIPWL
CC
D IRQ pulse width low
—
4
—
tCYC
2
tIPWH
CC
D IRQ pulse width high
—
4
—
tCYC
3
tICYC
CC
D IRQ edge to edge time(2)
—
4 + N (3)
—
tCYC
1. IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200pF with SRC = 0b00.
2. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3. N= ISR time to clear the flag.
90/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 28. External interrupt timing
IRQ
1
2
3
3.18.5
DSPI timing
Table 41.
DSPI timing(1)
No.
1
Symbol
C
Parameter
Conditions
tSCK CC D DSPI cycle time
Min
Max
Master (MTFE = 0)
60
—
Slave (MTFE = 0)
60
—
Unit
ns
2
tCSC CC D PCS to SCK delay
—
16
—
ns
3
tASC CC D After SCK delay
—
26
—
ns
4
tSDC CC D SCK duty cycle
—
5
tA
6
tDIS
0.4 × tSCK 0.6 × tSCK
ns
CC D Slave access time
SS active to SOUT valid
—
30
ns
CC D Slave SOUT disable time
SS inactive to SOUT High-Z or
invalid
—
16
ns
7
tPCSC CC D PCSx to PCSS time
—
13
—
ns
8
tPASC CC D PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
35
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
35
—
Master (MTFE = 1, CPHA = 1)
35
—
Master (MTFE = 0)
–5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
–5
—
Master (MTFE = 0)
—
12
Slave
—
36
Master (MTFE = 1, CPHA = 0)
—
12
Master (MTFE = 1, CPHA = 1)
—
12
9
10
11
tSUI
tHI
ns
CC D Data setup time for inputs
CC D Data hold time for inputs
ns
tSUO CC D Data valid (after SCK edge)
ns
Doc ID 18340 Rev 3
91/104
Electrical characteristics
Table 41.
No.
12
DSPI timing(1) (continued)
Symbol
tHO
SPC56xP54x, SPC56xP60x
C
Parameter
Conditions
Min
Max
Master (MTFE = 0)
–2
—
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
–2
—
CC D Data hold time for outputs
ns
1. All timing are provided with 50pF capacitance on output, 1ns transition time on input signal
Figure 29. DSPI classic SPI timing — master, CPHA = 0
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
92/104
First Data
Unit
Last Data
11
Data
Last Data
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 30. DSPI classic SPI timing — master, CPHA = 1
CSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Figure 31. DSPI classic SPI timing — slave, CPHA = 0
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Doc ID 18340 Rev 3
93/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 32. DSPI classic SPI timing — slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Figure 33. DSPI modified transfer format timing — master, CPHA = 0
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
94/104
First Data
Last Data
Data
11
Data
Last Data
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Electrical characteristics
Figure 34. DSPI modified transfer format timing — master, CPHA = 1
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Figure 35. DSPI modified transfer format timing — slave, CPHA = 0
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Doc ID 18340 Rev 3
95/104
Electrical characteristics
SPC56xP54x, SPC56xP60x
Figure 36. DSPI modified transfer format timing — slave, CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 37. DSPI PCS strobe (PCSS) timing
8
7
PCSS
PCSx
96/104
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Package characteristics
4
Package characteristics
4.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2
Package mechanical data
4.2.1
LQFP144 mechanical outline drawing
Figure 38. LQFP144 package mechanical drawing
Seating plane
C
A
A2 A1
c
b
0.25 mm
gage plane
ccc
C
k
D
D1
A1
D3
L1
108
73
72
109
E3 E1
144
Pin 1
identification
L
E
37
1
36
e
Doc ID 18340 Rev 3
ME_1A
97/104
Package characteristics
Table 42.
SPC56xP54x, SPC56xP60x
LQFP144 mechanical data
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.8740
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
—
17.500
—
—
0.6890
—
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
—
17.500
—
—
0.6890
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0 °
3.5 °
7.0°
3.5 °
0.0 °
7.0 °
(2)
ccc
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Tolerance
98/104
Doc ID 18340 Rev 3
0.0031
SPC56xP54x, SPC56xP60x
4.2.2
Package characteristics
LQFP100 mechanical outline drawing
Figure 39. LQFP100 package mechanical drawing
0.25 mm
0.10 inch
GAGE PLANE
k
D
L
D1
L1
D3
51
75
C
76
50
b
E3 E1 E
100
26
Pin 1
1
identification
25
ccc
C
e
A1
A2
A
SEATING PLANE
C
1L_ME
Table 43.
LQFP100 mechanical data
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
Doc ID 18340 Rev 3
99/104
Package characteristics
Table 43.
SPC56xP54x, SPC56xP60x
LQFP100 mechanical data (continued)
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.000
—
—
0.4724
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.000
—
—
0.4724
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0 °
3.5 °
7.0 °
0.0 °
3.5 °
7.0 °
ccc(2)
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Tolerance
100/104
Doc ID 18340 Rev 3
0.0031
SPC56xP54x, SPC56xP60x
5
Ordering information
Ordering information
Figure 40. Ordering information scheme(g)
Example code:
Product identifier Core Family Memory Package Temperature Custom vers. Conditioning
SPC56
A
P
60
L3
C
EFA
Y
Y = Tray
R = Tape and Reel
X = Tape and Reel 90°
A = 5 V, 64 MHz
B = 3,3 V, 64 MHz
A = “Airbag” feature set
F = “Full feature” set
E = Data flash memory
B = –40 to 105 °C
C = –40 to 125 °C
L5 = LQFP144
L3 = LQFP100
60 = 1 MB
54 = 768 KB
P = SPC56xP54/60 family
A = Dual core e200z0h
0 = Single core e200z0h
SPC56 = Power Architecture in 90nm
g. Not all configurations are available on the market. Please contact your ST Sales Rappresentative to get the list of orderable
commercial part number.
Doc ID 18340 Rev 3
101/104
Revision history
6
SPC56xP54x, SPC56xP60x
Revision history
Table 44 summarizes revisions to this document.
Table 44.
Date
Revision
21-Dec-2010
1
Initial release
2
In the Feature list:
Revised the first bullet.
Changed “Up to 82 GPIO” to “Up to 80 GPIO”
Changed “and 82 GPIO” to “and 49 GPIO”
Changed “FlexRay module“ to “1 FlexRay™ module”.
Added Section 1.5, Feature details
Table 4: SPC56xP54/60 series block summary, added FlexRay entry.
In the “LQFP176 pinout (top view)” figure:
– Pin 104 now is TDI, was PB[5]
– Pin 107 now is TDO, was PB[4]
– Pin 71 now is NC, was OKOUT
– Pin 72 now is NC, was OKOUT_B
– Pin 87 now is NC, was NBYPASS_HV
– Pin 88 now is NC, was IPP_LIVI_B_VDDIO
Table 7: Pin muxing:
PB[6] was clk_out_div5, is now clk_out_div256
Removed PB[4] and PB[5] rows
In the A[3] row, changed ABS[2] to ABS[1]
Section 3.11, DC electrical characteristics, added “Peripherals supply
current (5 V and 3.3 V)” table
Table 14: EMI testing specifications, removed all references to SAE
Replaced both Table 12: Thermal characteristics for 144-pin LQFP and
Table 13: Thermal characteristics for 100-pin LQFP
Table 30: PLLMRFM electrical specifications (VDDPLL = 1.08 V to
1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH), changed the max value
of fSYS from 120 to 64
Table 33: Program and erase specifications:
Removed all TBC
changed the initial max value of TBKPRG (Code Flash) from 3.3 to
6.6 s
changed the max value of TBKPRG (Data Flash) from 1.9 to 4.1 s
changed the max value of Twprogram (Data Flash) from 300 to 500 µs
Added tESRT row
Table 17: Voltage regulator electrical characteristics, updated
VDD_LV_REGCOR values
Updated Table 18: Low voltage monitor electrical characteristics
Updated Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0) and
Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1)
Removed “NVUSRO[OSCILLATOR_MARGIN] field description”
section.
Removed ordarable parts tables.
18-Oct-2011
102/104
Document revision history
Substantive changes
Doc ID 18340 Rev 3
SPC56xP54x, SPC56xP60x
Table 44.
Date
15-May-2012
Revision history
Document revision history (continued)
Revision
Substantive changes
3
Removed “Enhanced Full-featured” version.
In the cover page, added “(1 × Master/Slave, 1 × Master Only)“ at the
end of the bullet “2 LINFlex modules (LIN 2.1)”
Table 2: SPC56xP54/60 device comparison, updated the value of
“LINFLEX module” to “2 (1 × Master/Slave, 1 × Master only)”
Section 1.5.4: On-chip flash memory with ECC
replaced two occurrences of “3 wait states” to “2 wait states”
replaced 60 MHz to 64 MHz
Section 1.5.21: Serial communication interface module (LINFlex),
updated first bullet to “Supports LIN Master mode (on both modules),
LIN Slave mode (on one module) and UART mode”
Section 1.5.24: Analog-to-digital converter (ADC), removed bullet
concerning the analog watchdogs from Normal mode features.
Table 5: Supply pins, removed VREG_BYPASS row.
Table 6: System pins:
added VREG_BYPASS row
added a footnote about RESET
Table 9: Absolute maximum ratings:
changed typical value of TVDD to 0.25 and added a footnote
added VINAN entry
Updated Section 3.8.1: Voltage regulator electrical characteristics
Updated Table 14: EMI testing specifications
Table 18: Low voltage monitor electrical characteristics, changed
maximum value of VMLVDDOK_H to 1.15
Table 20: DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V]=0),
added IPU and IPD rows for RESET pin.
Table 21: Supply current (5.0 V, NVUSRO[PAD3V5V]=0):
added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP
mode
updated values and parameter classification of IDD_FLASH
Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1),
added IPU and IPD rows for RESET pin.
Table 23: Supply current (3.3 V, NVUSRO[PAD3V5V]=1):
added maximum values of IDD_LV_CORE for: RUN, HALT, and STOP
mode
updated values and parameter classification of IDD_FLASH
Added Table 26: I/O consumption
Table 31: 16 MHz RC oscillator electrical characteristics, changed
minimum and maximum values of RCMVAR respectively to -6 and 6.
Renamed Figure 16: Input equivalent circuit (precise channels) (was
“Input equivalent circuit”)
Added Figure 17: Input equivalent circuit (extended channels)
Section 3.15.1: Input impedance and ADC accuracy, updated
Equation 4 and Equation 10
Table 32: ADC conversion characteristics, added VINAN, CP3 and RSW2
rows
Doc ID 18340 Rev 3
103/104
SPC56xP54x, SPC56xP60x
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
104/104
Doc ID 18340 Rev 3