P-Channel Logic Level Enhancement NIKO-SEM P2003EVG Mode Field Effect Transistor SOP-8 Lead-Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -30 20mΩ -9A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -30 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current TC = 70 °C Pulsed Drain Current -9 ID 1 -8 IDM TC = 25 °C Power Dissipation -50 2.5 PD TC = 70 °C Operating Junction & Storage Temperature Range A W 1.3 Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJc 25 °C / W Junction-to-Ambient RθJA 50 °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) 2 PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -30 VGS(th) VDS = VGS, ID = -250µA -1 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V Zero Gate Voltage Drain Current IDSS Gate Threshold Voltage On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Forward Transconductance1 gfs V -1.5 -3 ±100 nA VDS = -24V, VGS = 0V -1 VDS = -20V, VGS = 0V, TJ = 125 °C -10 VDS = -5V, VGS = -10V -50 µA A VGS = -4.5V, ID = -7A 25 35 VGS = -10V, ID = -9A 15 20 VDS = -10V, ID = -9A 24 mΩ S OCT-20-2004 1 P-Channel Logic Level Enhancement NIKO-SEM P2003EVG Mode Field Effect Transistor SOP-8 Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 200 Qg 17 Total Gate Charge 2 Gate-Source Charge2 Gate-Drain Charge 2 1610 VGS = 0V, VDS = -15V, f = 1MHz Qgs VDS = 0.5V(BR)DSS, VGS = -10V, 5 Qgd ID = -9A 6 Turn-On Delay Time2 td(on) 2 tr VDS = -15V, RL = 1Ω 10 td(off) ID ≅ -1A, VGS = -10V, RGS = 6Ω 18 Rise Time Turn-Off Delay Time Fall Time2 2 pF 410 24 nC 5.7 tf nS 5 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -2.1 Pulsed Current ISM -4 Forward Voltage1 VSD 3 IF = -1A, VGS = 0V -1.2 A V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P2003EVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. OCT-20-2004 2 P-Channel Logic Level Enhancement P2003EVG Mode Field Effect Transistor SOP-8 Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature 100 V GS = 0V 10 -Is - Reverse Drain Current(A) NIKO-SEM T A = 125° C 1 25° C 0.1 -55° C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 -VSD - Body Diode Forward Voltage(V) 1.0 1.2 OCT-20-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG SOP-8 Lead-Free OCT-20-2004 4 P-Channel Logic Level Enhancement NIKO-SEM P2003EVG Mode Field Effect Transistor SOP-8 Lead-Free SOIC-8(D) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. A 4.8 4.9 5.0 H 0.5 0.715 0.83 B 3.8 3.9 4.0 I 0.18 0.254 0.25 C 5.8 6.0 6.2 J D 0.38 0.445 0.51 K 1.27 E 0.22 0° 4° 8° L F 1.35 1.55 1.75 M G 0.1 0.175 0.25 N OCT-20-2004 5