EMIF04-EAR01F2 4-line IPAD™, EMI filter and ESD protection Features ■ EMI (I/O) low-pass filter ■ High efficiency in EMI filtering ■ High density capacitor ■ Very low PCB space occupation: 1.92 x 1.42 mm² ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression on external pins (IEC 61000-4-2 level 4) Flip Chip (11 bumps) Figure 1. Pin configuration (bump side) ■ High reliability offered by monolithic integration 1 2 3 ■ High reduction of parasitic elements through integration and wafer level packaging I1 GND O1 A O2 B Complies with the following standards ■ ■ I2 IEC 61000-4-2 Level 4, on output pins – 15 kV (air discharge) I3 GND O3 C IEC 61000-4-2 Level 1, on input pins – 2 kV (air discharge) I4 GND O4 D Applications Figure 2. Where EMI filtering in ESD sensitive equipment is required: ■ Earpiece and headset for mobile phones ■ PDAs ■ MP3 players I1 I2 I3 Description I4 The EMIF04-EAR01F2 is a 4-line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF04 Flip Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up 15 kV. April 2008 Schematic R C R C R C R C O1 O2 O3 04 GND = A2, C2, D2 TM: IPAD is a trademark of STMicroelectronics. Rev 2 1/7 www.st.com 7 Characteristics 1 EMIF04-EAR01F2 Characteristics Table 1. Symbol Absolute maximum ratings (Tamb = 25 °C) Parameter and test conditions Value Output pins (A3, B3, C3, D3) ESD discharge IEC61000-4-2, air discharge Unit 15 VPP kV Input pins (A1, B1, C1, D1) ESD discharge IEC61000-4-2, air discharge 2 Maximum junction temperature Tj 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Table 2. Symbol Electrical characteristics (Tamb = 25 °C) Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current IR IRM VCL VBR VRM R Series resistance between input and output C Capacitance Symbol 2/7 IPP Test conditions VBR IR = 1 mA IRM VRM = 3 V per line IRM IR VRM VBR VCL V IPP Min. Typ. 14 Max. Unit 18 V 500 nA R Tolerance ± 30% 10 Ω C VLINE = 0 V, VOSC = 30 mV, F = 1 MHz Tolerance ± 20% 5.8 nF EMIF04-EAR01F2 Figure 3. 0.00 Characteristics S21 (db) all lines attenuation Figure 4. Analog cross talk dB dB 0.00 -10.00 -20.00 -10.00 -30.00 -20.00 -40.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 F (Hz) -90.00 F (Hz) -50.00 10.0M 30.0M Line 1 Line 3 Figure 5. 100.0M 300.0M 1.0G -100.00 3.0G 100.0k Line 2 Line 4 1.0M 100.0M 1.0G Xtalk ESD response to IEC 61000-4-2 (+15 kV air discharge) on one output Figure 6. ESD response to IEC 61000-4-2 (-15 kV air discharge) on one output 5 V/div 5 V/div 80 ns/div 80 ns/div Figure 7. 10.0M Line capacitance versus reverse applied voltage Cline (nF) 9 F = 1 Mhz V osc = 30 mVRMS Tj = 25° C 8 7 6 5 4 3 2 1 V line (V) 0 0 1 2 3 4 5 6 7 8 9 3/7 Ordering information scheme 2 EMIF04-EAR01F2 Ordering information scheme Figure 8. Ordering information scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 µm, bump = 310 µm 3 Packaging information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 9. Flip Chip package dimensions 310 µm ± 50 210 µm 1.92mm ± 50 µm 4/7 210 µm 1.42mm ± 50 µm 500 µm ± 50 500 µm ± 50 650 µm ± 65 EMIF04-EAR01F2 Packaging information Figure 10. Footprint recommendations Figure 11. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (Y = year ww = week) Copper pad Diameter 250 µm recommended, 300 µm max Solder stencil opening: 330 µm E x x z y ww Solder mask opening recommendation: 340 µm min for 300 µm copper pad diameter Figure 12. Flip Chip tape and reel specifications Dot identifying Pin A1 location 3.5 ± 0.1 1.56 ST E xxx yww 2.02 ST E xxx yww Note: ST E All dimensions in mm xxx yww 8 ± 0.3 0.73 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 4 ± 0.1 User direction of unreeling Note: More information is available in the application note: AN2348:"Flip Chip: Package description and recommendations for use" AN1751: “EMI filters: Recommendations and measurements” 5/7 Ordering information 4 Ordering information Table 3. 5 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF04-EAR01F2 GK Flip Chip 3.8 mg 5000 Tape and reel 7” Revision history Table 4. 6/7 EMIF04-EAR01F2 Document revision history Date Revision Changes 06-Oct-2006 1 Initial release. 28-Apr-2008 2 Updated ECOPACK statement. Updated figures Figure 9, and Figure 12. Reformatted to current standards. EMIF04-EAR01F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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