R2A20121SP Synchronous Phase Shift Full-Bridge Control IC REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Features • • • • • High frequency operation; oscillator frequency = 2 MHz Max Full-bridge phase-shift switching circuit with adjustable delay times Integrated secondary synchronous rectification control with adjustable delay times Pulse by pulse current limit Package: TSSOP-20 Illustrative Circuit VIN Vout + − DC 5 V DC 5 V DC 5 V DC 5 V DC 5 V Vbias (DC 12 V) VCC OUT OUT CS RAMP -A -B OUT -C OUT OUT OUT -D -E -F COMP R2A20121 VREF GND RT SYNC SS FB (+) FB (−) DELAY DELAY DELAY -3 -1 -2 HAT3043C HAT3042C HAT3004R Note: The above circuit is reference example. Please confirm the operation when designing the system. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 1 of 27 R2A20121SP Pin Arrangement SYNC 1 20 RT RAMP 2 19 GND CS 3 18 OUT-A COMP 4 17 OUT-B FB (+) 5 16 OUT-C FB (−) 6 15 OUT-D SS 7 14 OUT-E DELAY-1 8 13 OUT-F DELAY-2 9 12 VCC DELAY-3 10 11 VREF (Top view) Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SYNC Function Synchronization I/O for the oscillator RAMP CS COMP FB (+) FB (–) SS DELAY-1 DELAY-2 DELAY-3 VREF VCC OUT-F OUT-E OUT-D OUT-C OUT-B OUT-A GND RT Current sense signal input for the full-bridge control loop Current sense signal input for OCP Error amplifier output Error amplifier plus input Error amplifier minus input Timing capacitor for soft-start Delay time adjustor for the full-bridge control signal (OUT-A and B) Delay time adjustor for the full-bridge control signal (OUT-C and D) Delay time adjustor for the secondary control signal (OUT-E and F) 5 V/20 mA Output IC power supply input Secondary control signal Secondary control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Ground level for the IC Timing resistor for the oscillator REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 2 of 27 R2A20121SP Block Diagram VCC H UVLO L VCC > 8.4 V→High UVL 5V GENERATOR VREF VREF H GOOD L VREF > 4.6 V→High VREF RT START-UP COUNTER 32 CLOCK Current Ref. Generator OSCILLATOR FB (−) OUT-A VREF DELAY ERROR AMP VREF − VREF Q SYNC. I/O CIRCUIT BIAS DELAY RES SYNC VREF GOOD DELAY-1 OUT-B VREF 500 µ R SQ + DELAY OUT-C FB (+) COMPARATOR DELAY-2 VREF − + COMP DELAY OUT-D 1.135 V RAMP + − CLAMP CIRCUIT 1.55 V 1.46 V VREF GOOD VREF R Q S Zero Delay 4V 10 µ SS VREF GOOD VREF DELAY CS + 1.4 V PULSE BY PULSE − Zero Delay DELAY GND Note: Note that all switches in the block diagram are turned on when control signal is high. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 3 of 27 OUT-E DELAY-3 VREF OUT-F R2A20121SP Absolute Maximum Ratings (Ta = 25°C) Item Power supply voltage Peak output current DC output current VREF output current COMP sink current DELAY set current RT set current VREF terminal voltage Terminal group 1 voltage Operating junction temperature Storage temperature Symbol Vcc Ipk-out Idc-out Iref-out Isink-comp Iset-delay Iset-rt Vter-ref Vter-1 Tj-opr Tstg Notes: 1. 2. 3. 4. 5. Ratings 20 ±50 ±5 –20 2 0.3 0.3 –0.3 to 6 –0.3 to (Vref + 0.3) –40 to +125 –55 to +150 Rated voltages are with reference to the GND pin. Shows the transient current when driving a capacitive load. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). VREF pin voltage must not exceed VCC pin voltage. Terminal group 1 is defined the pins; CS, RAMP, COMP, FB (+), FB (–), SS, RT, SYNC, DELAY-1 to 3, OUT-A to F 6. θja; 228°C/W Board condition; Glass epoxy 55 mm × 45 mm × 1.6 mm, 10% wiring density. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 4 of 27 Unit V mA mA mA mA mA mA V V °C °C Notes 1 2, 3 3 3 3 3 3 1, 4 1, 5 6 R2A20121SP Electrical Characteristics (Ta = 25°C, Vcc = 12 V, RT = 33 kΩ, Rdelay = 51 kΩ, unless otherwise specified.) Item SUPPLY VREF OSCILLATOR SYNC Note: Symbol Min Typ Max Unit Test Conditions Start threshold VH 7.7 8.4 9.1 V Shutdown threshold VL 7.4 8.0 8.6 V UVLO hysteresis dVUVL 0.3 0.4 0.5 V Start-up current Is — 90 150 µA Vcc = 7.5 V Operating current Icc — 7 10 mA No load on VREF pin Output voltage Vref 4.9 5.0 5.1 V Line regulation Vref-line — 0 10 mV Vcc = 10 V to 16 V Load regulation Vref-load — 6 20 mV Iref = –1 mA to –20 mA Temperature stability dVref/dTa — ±80 * 1 — ppm/°C Oscillator frequency fosc — 960 * 1 — kHz Switching frequency fsw 412 480 547 kHz Line stability fsw-line –1.5 0 1.5 % Vcc = 10 V to 16 V Temperature stability dfsw/dTa — ±0.1 * — %/°C Ta = –40 to 105°C RT voltage VRT 2.5 2.7 2.9 V Input threshold VTH-SYNC 2.5 2.85 3.2 V Output high VOH-SYNC 3.5 4.0 — V RSYNC = 33 kΩ to GND RSYNC = 33kΩ to VREF 1 Output low VOL-SYNC — 0.05 0.15 V Minimum input pulse TI-MIN 50 — — ns Output pulse width TO-SYNC — 500 — ns 1. Reference values for design. Not 100% tested in production. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 5 of 27 Ta = –40 to 105°C Measured on OUT-A, -B R2A20121SP Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.) ERROR AMPLIFIER Item Input offset voltage Symbol Vos Min –2 Typ 3 Max 8 Unit mV FB (+) input current FB (–) input current Open-loop DC gain Unity gain bandwidth Output source current IFB (+) IFB (–) Av BW ISOURCE –2.0 –2.0 — — –650 0 0 1 80 * 1 2* –500 2.0 2.0 — — –390 µA µA dB MHz µA Output sink current ISINK 2.0 6.5 — mA FB (+) = 1.25 V, FB (–) = 1.75 V, COMP = 2 V Output high voltage VOH-EO 3.7 3.9 — V FB (+) = 1.25 V, FB (–) = 0.75 V, COMP; Open Output low voltage VOL-EO — 0.1 0.4 V FB (+) = 1.25 V, FB (–) = 1.75 V, COMP; Open VCLAMP-EO –0.16 –0.07 0.0 V FB (+) = 1.25 V, FB (–) = 0.75 V, COMP; Open, SS = 1 V VRAMP IRAMP ISINK-RAMP Dmin Dmax Tpd Tdis TD1, 2, 3 TD2_1, _2, _3 VD1, 2, 3 1.035 –5 8 — — — 40 22 70 1.9 1.135 –0.8 26 1 5 0** 1 5 97.0 * * 30 80 33.5 100 2.0 1.235 5 — — — 60 120 45 130 2.1 V µA mA % % ns ns ns ns V Output clamp voltage * PHASE MODULATOR 4 RAMP offset voltage RAMP bias current 1 RAMP sink current * Minimum phase shift Maximum phase shift 2 Delay to OUT-C, -D * 1 RAMP discharge time * 3 DELAY-1, -2, -3 * 1 3 DELAY2-1, -2, -3 * * Terminal voltage DELAY Notes: 1. Reference values for design. Not 100% tested in production. 2. Tpd is defined as; 1V RAMP 50% 0V 5V 50% OUT-C/D 0V Tpd 3. TD1, 2, 3 are defined as; TD1 TD1 OUT-A 50% OUT-B For primary control OUT-C TD2 TD2 OUT-D OUT-E For secondary control TD3 OUT-F TD3 4. VCLAMP-EO = VCOMP – SS voltage (1 V) 5. Maximum/Minimum phase shift is defined as; D= T2 × 2 × 100 (%) T1 OUT-A OUT-B T2 T2 OUT-D OUT-C T1 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 6 of 27 T1 Test Conditions FB (–) and COMP are shorted. VFB (+) = 1.25 V FB (+) = FB (–) = 1.25 V FB (+) = FB (–) = 1.25 V FB (+) = 1.25 V, FB (–) = 0.75 V, COMP = 2 V RAMP = 0.3 V RAMP = 1 V, COMP = 0 V RAMP = 1 V, COMP = 0 V RAMP = 0 V, COMP = 2.1 V COMP = 1.6 V Delay set R = 51 k Delay set R = 180 k Delay set R = 51 k R2A20121SP Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 33 k, Rdelay = 51 k, unless otherwise specified.) Item SOFT START OVER Symbol Min Typ Max Unit Source current ISS –14 –10 –6 µA SS high voltage VOH-SS 3.9 4.0 4.1 V Pulse-by-pulse current limit threshold VCS-PP 1.26 1.4 1.54 V CURRENT PROTECTION Delay to OUT pins * OUTPUT High voltage 2 Test Conditions SS = 1 V Tpd-cs — 40 80 ns CS = 0 V to 1.57 V VOH-OUT 4.3 4.8 — V IOUT = –5 mA Low voltage VOL-OUT — 0.1 0.4 V IOUT = 5 mA Rise time tr — 5 15 ns COUT = 33 pF tf — 5 15 ns COUT = 33 pF TD4 — 3 20 ns Fall time Timing offset * 3 Notes: 1. Reference values for design. Not 100% tested in production. 2. Tpd-cs is defined as; 1.57 V 50% CS 0 50% OUT-C/D Tpd-cs 3. TD4 is defined as; OUT-D OUT-C 50% OUT-E 50% TD4 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 7 of 27 50% OUT-F 50% TD4 R2A20121SP Timing Diagram Note: All voltage, current, time shown in the diagram is typical value. Full Bridge and Secondary Control COMP RAMP + 1.135 V (Internal signal) 1.135 V RAMP CS TD1 TD1 OUT-A OUT-B OUT-C TD2 TD2 OUT-D TD3 OUT-E TD3 OUT-F VIN OUT-A DRIVE MA MC DRIVE OUT-C OUT-B DRIVE MB MD DRIVE OUT-D RAMP DRIVE OUT-E External Power Stage REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 8 of 27 ME MF DRIVE OUT-F R2A20121SP Start-up and Shutdown 8.4 V 8V VCC 5V VREF 0V RES (Internal signal) VREF GOOD (Internal signal) 32 counts High Low 4.0 V SS 0V DISCHARGE (Internal signal) High Low From Error Amp COMP COMPARATOR − + FOR PHASE MODULATION 1.135 V RAMP Current information CLAMP VREF 4.0 V SS Iss 10 µA SS IN Css DISCHARGE Soft-start Block REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 9 of 27 R2A20121SP Functional Description Note: All voltage, current, time shown in the diagram is typical value unless otherwise noted. UVLO UVLO (Under Voltage Lockout Operation) is a function that halts operation of the IC in the event of a low IC power supply voltage. When IC operation is halted, the 5 V internal voltage generation circuit (VREF) halts, and therefore operation of circuitry using VREF as the operating power supply halts. Circuit blocks other than UVLO use VREF as their operating power supply. Therefore, the power supply current of the IC becomes equal to the current dissipated by the UVLO circuit. The following graphs show the relationship between the VCC input current and VCC input voltage, and between VREF and the VCC input voltage. ICC ICC Is VCC 0 7.5 V 8.0 V 8.4 V 0 8.0 V 8.4 V 12 V 20 V VREF 5V VCC 20 V Figure 1 Start-up Counter When the VREFGOOD signal (internal signal) goes to the logic low level, the R2A20121 starts operating as a controller. The VREFGOOD signal is created from VREFGOOD circuit output via a 32-clock startup counter. VCC H L VREF 5V Generator UVLO From Oscillator VREF GOOD H L VREF GOOD Start-up Counter 32 clock Circuit Bias Figure 2 Therefore, the start of IC operation is a 32-count later than UVLO release. When the oscillator frequency is set to 1 MHz, this represents a delay of 32 µs. This delay enables operation to be halted until VREF (5 V) stabilizes when UVLO is released. Note that the start-up counter operates when VREF rises is performed, but does not operate when VREF falls is performed (there is no logic delay due to the start-up counter). 8.4 V 8.0 V VCC 4.6 V VREF 4.4 V 32 counts RES (Internal signal) VREF GOOD (Internal signal) Start of operation Figure 3 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 10 of 27 Operation halted R2A20121SP Oscillator The oscillation frequency of the oscillator is set by means of a resistance connected between the RT pin and GND. The following graph shows the relationship between the external resistance and the oscillation frequency. The typical value of the oscillation frequency is given by the following equation. 1 25 [pF] × RT [Ω] + 150 [ns] fosc = [Hz] fosc vs. RT 10000 R2A20121 fosc (kHz) SYNC 1000 (2.7 V) RT GND 100 RT 10 10 100 RT (kΩ) 1000 Figure 4 Place the resistor for connection to the RT pin as close to the pin as is possible. Please design the pattern so that the level of cross-talk from other signals is minimized. Synchronized Operation Parallel synchronized operation is possible by connecting the SYNC pins of R2A20121s. In this case, up to four slave ICs can be connected to one master IC. A value of at least twice the master RT value should be set for the slave IC RT values. R2A20121 SLAVE R2A20121 MASTER (2.7 V) RT RT SYNC SYNC RT (2.7 V) 2 × RT GND GND R2A20121 SLAVE SYNC RT GND Max 4 slaves Figure 5 Parallel Synchronized Operation REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 11 of 27 (2.7 V) 2 × RT R2A20121SP External synchronized operation is possible by supplying a synchronization signal to the SYNC pins of R2A20121s. In this case, a frequency not exceeding 1/2 that of the master clock should be set for the R2A20121s. A maximum master clock frequency of 2 MHz should be used. See the figure below for the input waveform conditions. R2A20121 SLAVE TTL or CMOS MASTER MASTER CLOCK SYNC RT (2.7 V) GND RT R2A20121 SLAVE SYNC RT (2.7 V) GND RT Figure 6 External Synchronized Operation TCYCLE Item TI-MIN TIH-SYNC TIL-SYNC 500 ns Min TI-MIN 50 ns Min TIL-MIN 100 ns Min VIH-SYNC 3.2 V to VREF VIL-SYNC 0 V to 2.5 V TIL-MIN Figure 7 SYNC Pin Input Conditions REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 12 of 27 Input Range TCYCLE R2A20121SP Noise Margin When a synchronization signal is given to an SYNC terminal of the R2A20121, the oscillation frequency of the IC may occur abnormality by the slew rate of the synchronization signal and the noise level of the VREF terminal. The following graph shows the relationship between the slew rate of the synchronization signal and the VREF noise level. In the case of synchronized operation, a VREF capacitor should be chosen with reference to the following graph. R2A20121 Noise Margin 11 10 SYNC Slew Rate [V/µs] 9 8 Area of normal operation 7 6 5 4 3 2 1 0 100 150 200 250 300 VREF Noise Level [mVp-p] 350 Note: The upper graph is a measurement result by our evaluation jig. Please confirm enough evaluation because the influence of the noise is different with each board. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 13 of 27 400 R2A20121SP RAMP Capacitance Setting Method The following graph shows the relationship between the RAMP capacitance and discharge time. A RAMP capacitance should be chosen with reference to the following graph. R2A20121 Discharge Time vs. RAMP Capacitance 140 120 Discharge Time [ns] 100 80 60 40 20 RAMP Capacitance [pF] REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 14 of 27 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 R2A20121SP Synchronous Phase Shift Full-Bridge Control The R2A20121 is provided with full-bridge control outputs OUT-A through OUT-D, and secondary-side synchronous rectification control outputs OUT-E and OUT-F. ZVS (Zero Voltage Switching) can be performed by adjusting timing delays TD1 and TD2 between the OUT-A through OUT-D outputs by means of an external resistance. OUT-E and OUT-F have an output timing suitable for secondary-side full-wave rectification, and so can be used in either current doubler or center tap applications. The following figure shows full-bridge ZVS + current doubler operation using an ideal model. RES pulse (Internal signal) SA Full-Bridge control switch (on when high) TD1 SB SC TD2 SD Synchronous rectification control switch (on when high) Transformer primary both-side voltage SE TD3 SF VIN 0 −VIN Transformer VIN/N secondary 0 −VIN/N both-side voltage Subinterval : Time : 1 t0 2 t1 3 t2 4 t3 5 t4 t5 Figure 8 • Subinterval: 1 In interval 1, SA and SD are turned on, and VIN is generated on the transformer primary side. On the transformer secondary side, a value proportional to the winding ratio is generated, and the primary-side power is transmitted to the load side. At this time, secondary-side switch SE is off and SF is on. L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Subinterval: 1 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 15 of 27 R2A20121SP • Subinterval: 2 As SD is turned off at point t1, the primary-side current flows into resonant capacitance Cr2. At this time Cr2 is charged, and therefore the potential of V12 rises. Considering that the exciting current and the L1 and L2 ripple currents are considerable smaller than Io, the following is an approximate equation for the slope of V12. dV12 dt = 0.5 Io N • 1 Cr2 [ V/s ] …………………… (1) Here, N is the ratio of the primary coil to the secondary coil (N = N1/N2), and Io is the output current. As SE and SF are on, the transformer secondary side is in the shorted state, and the value of the current flowing up to that time is retained. L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Subinterval: 2 • Subinterval: 3 SC is turned on at point t2. ZVS operation can be attained by setting the SD off (t1) → SC on (t2) delay to the optimal value. This delay time can be expressed by equation (2). TD2 = N 0.5 Io • Cr2 • VIN [s] …………………… (2) After SC is turned on, the transformer primary side is in the shorted state, and therefore the current value immediately after SC was turned on is retained. L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Subinterval: 3 • Subinterval: 4 As SA is turned off at point t3, the primary-side current discharges resonant capacitance Cr1, and the potential of V11 falls. A negative potential is applied to resonant inductor Lr, and a flux reset starts. At this time, since the series resonance circuit is composed of Cr1 and Lr, the V11 waveform changes to a sine wave. The resonance frequency is given by equation (3). fr = 1 [Hz] …………………… (3) 2 π √ (Cr1 • Lr) L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Subinterval: 4 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 16 of 27 R2A20121SP • Subinterval: 5 When synchronous switch SF is turned off at point t4, the current flowing in SF up to that time continues to flow through the SF body diode. SF turn-off must be performed before completion of the resonant inductor Lr flux reset. If SF is not off on completion of the Lr flux reset, power transmission will be performed with the transformer secondary-side shorted, and therefore an excessive current will flow in the transformer primary and secondary sides, and parts may be damaged. Also, if the SF body diode is on for a long period, loss will be high. Therefore, optimal timing should be set by means of the R2A20121's delay adjustment pin, DELAY-3. Lr reset time tr is given by equation (4) when the resonance voltage peak value is within the input voltage. Treset (Lr) | vpp ≤ VIN = 1 1 • fr 4 = 0.5 π √ (Lr • Cr1) [s] ………… (4) Here, vpp is the resonance voltage peak value. vpp = Io 2 • 1 • N √ (Lr / Cr1) [V] …………………… (5) L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Subinterval: 5 • Time: t5 SB is turned on at point t5. The SB switching loss can be minimized by turning on SB when the SB both-side voltages are at a minimum (when the resonance voltage is at a peak). The SB turn-on timing can be set with TD1 of the R2A20121. The time when the resonance voltage is at a peak is given by equation (4). From t5 onward, operation is on the same principle as in Subinterval 1 through Subinterval 5. L1 VIN SA SE SC V11 V12 VOUT Lr Cr1 SB SD Cr2 SF L2 Time: t5 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 17 of 27 R2A20121SP Delay Setting Inter-output delays (TD1, TD2, TD3) are set by means of a resistance connected between the DELAY-1 (-2, -3) pin and GND. The following graph shows the relationship between the external resistance and delay. The typical value of the delay set time is given by the following equation. TD = 0.5 [pF] × RD [Ω] + 8 [ns] [s] When the RD value is small, the set time will be larger than the above calculated value due to the effect of internal delay, etc., and therefore a constant setting should be made with reference to the following graph. TD (ns) R2A20121 TD vs. RD 1.00E+03 1.00E+02 (2.0 V) 1.00E+01 RD 1.00E+00 DELAY-1 (DELAY-2) (DELAY-3) GND 1 10 1000 100 RD (kΩ) Figure 9 Place the resistor for connection to the DELAY-1,2,3 pin as close to the pin as is possible. Please design the pattern so that the level of cross-talk from other signals is minimized. DELAY-3 (TD3) There is a condition that secondary-side control output OUT-E and OUT-F delay TD3 is 0 s (typical) in order to prevent shorting of the transformer secondary side. The relationship between TD3 and the IC operating state is shown in the following table. Mode Light load Pulse by pulse OCL Definition COMP < 1.55 V CS ≥ 1.4 V Operation of OUT-E, OUT-F TD3 = 0 TD3 = 0 Notes 1, 3 2, 3 Notes: 1. Light-load detection is performed by means of the error amplifier output voltage. Light-load detection characteristics are as shown in the following diagram. VREF Error Light Load 500 µ Amp. TD3 Detector − FB (−) − TD3 + + set value FB (+) COMP − Comparator + RAMP 1.135 V 0 1.46 V 1.55 V COMP voltage Light Load Detector Characteristics 2. TD3 of the next OUT-E or OUT-F after the pulse-by-pulse current limiter (PBP OCL) operates is 0 s (typical). When OUT-C and OUT-D are subsequently inverted by the Phase Shift Comparator, not the PBP OCL, TD3 is restored to the value set by means of the DELAY-3 pin. 3. If once the SS terminal is not exceed 3.9 V after an IC started, the IC continues maintaining a state in TD3 = 0. When an external part is attached to the SS terminal, please be careful. REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 18 of 27 R2A20121SP Application Note: All voltage, current, time shown in the diagram are typical value. Sample application circuits are given here. Confirmatory experiments should be carried out when applying these examples to products. Slope Compensation In order to improve the unstable operation characteristic of current mode, voltage slopes in a current sense signal can be superimposed. The following is a possible slope compensation method. R2A20121 5 V (VREF) OUT-A OUT-B OUT-D OUT-C Comparator − + 1.135 V Current sense signal Compensated signal RAMP S Q R RES Figure 10 Driving a Pulse Transformer OUT-A through OUT-F of this IC are CMOS outputs that use Vref as their power supply. When directly driving a pulse transformer, the Vref voltage fluctuates according to the exciting current. As Vref fluctuation may make internal circuit operation unstable, direct drive of a pulse transformer should be avoided. • Case 1 (NG) The figure below shows a case where a pulse transformer is driven directly. Vref voltage fluctuation occurs due to the exciting current. R2A20121 Vref value fluctuates due to this exiting current Vref Cref Internal Circuitry OUT-E Case 1 (NG) • Case 2 The figure below shows an example in which a current amplifier is added by means of transistors. A reverse current due to the exciting current is prevented by a blocking diode, and therefore capacitance CB is charged. In this way, fluctuation of the Cref potential is suppressed and stable operation can be achieved. As well as a buffer implemented by means of a transistor, standard logic IC or buffer IC connection is also possible. The buffer circuit power supply method should be implemented in the same way. Blocking diode R2A20121 CB Vref Cref Internal Circuitry OUT-E Case 2 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 19 of 27 R2A20121SP • Case 3 The figure below shows an example of a drive power supply method using emitter following. For the same reason as described above, fluctuation of the Cref potential is suppressed and stable operation can be achieved. VCC R2A20121 CB VREF Cref Internal Circuitry OUT-E Case 3 Supplying Power from an External Power Supply It is also possible to use an external source as the power supply for the R2A20121 as shown in figure 11. The VREFGOOD circuit controls whether the IC is operating or stopped. The threshold voltage of the VREFGOOD circuit is 4.6 V (typ.) on the rising edge and 4.4 V on the falling edge. Since the IC’s characteristics vary with the value of the external voltage, this voltage must be provided by a high-precision 5-V source. Vcc Vext 5 V ± 2% VREF R2A20121 Figure 11 REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 20 of 27 R2A20121SP Characteristic Curves UVL Voltage vs. Ambient Temperature Characteristics 9.0 8.8 VH [V] 8.4 VH/VL 8.6 8.2 VL 8.0 7.8 7.6 7.4 −40 −25 0 25 50 Ta 75 100 125 [°C] Standby Current vs. Ambient Temperature Characteristics 140 Vcc = 7.5 V 120 100 Is [µA] 80 60 40 20 0 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 21 of 27 [°C] 75 100 125 R2A20121SP Operating Current vs. Ambient Temperature Characteristics 12 10 Icc [mA] 8 6 4 2 0 −40 −25 0 25 50 Ta 75 100 125 [°C] VREF Output Voltage vs. Ambient Temperature Characteristics 5.20 5.15 5.10 VREF [V] 5.05 5.00 4.95 4.90 4.85 4.80 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 22 of 27 [°C] 75 100 125 R2A20121SP Error Amplifier Offset Voltage vs. Ambient Temperature Characteristics 10.0 8.0 [mV] 6.0 4.0 Vos 2.0 0.0 −2.0 −4.0 −6.0 −40 −25 0 25 50 Ta 75 100 125 [°C] Error Amplifier Source Current vs. Ambient Temperature Characteristics −100 FB (+) = 1.25 V, FB (−) = 0.75 V, COMP = 2 V [µA] −300 ISOURCE −200 −400 −500 −600 −700 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 23 of 27 [°C] 75 100 125 R2A20121SP Error Amplifier Sink Current vs. Ambient Temperature Characteristics 20 FB (+) = 1.25 V, FB (−) = 1.75 V, COMP = 2 V 18 16 ISINK [mA] 14 12 10 8 6 4 2 0 −40 −25 0 25 50 Ta 75 100 125 [°C] Soft-start Pin Current vs. Ambient Temperature Characteristics −5 SS = 1 V −6 −7 [µA] −8 −9 Iss −10 −11 −12 −13 −14 −15 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 24 of 27 [°C] 75 100 125 R2A20121SP Switching Frequency vs. Ambient Temperature Characteristics 580 560 540 fsw [kHz] 520 500 480 460 440 420 400 380 −40 −25 0 25 50 Ta 75 100 125 100 125 [°C] TD1 Delay vs. Ambient Temperature Characteristics 50 45 40 TD1 [ns] 35 30 25 20 15 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 25 of 27 [°C] 75 R2A20121SP Current Sense Delay Time vs. Ambient Temperature Characteristics 70 60 Tpd [ns] 50 40 30 20 10 0 −40 −25 0 25 Ta 50 [°C] 75 100 125 Overcurrent Protection Delay Time vs. Ambient Temperature Characteristics 100 Tpd_cs [ns] 80 60 40 20 0 −40 −25 0 25 50 Ta REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 26 of 27 [°C] 75 100 125 R2A20121SP Package Dimensions JEITA Package Code P-TSSOP20-4.4x6.5-0.65 RENESAS Code PTSP0020JB-A *1 Previous Code TTP-20DAV MASS[Typ.] 0.07g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 11 c HE *2 E bp Terminal cross section ( Ni/Pd/Au plating ) Index mark Reference Dimension in Millimeters Symbol 1 e bp L1 x M A Z 10 *3 A1 θ L y Detail F REJ03D0914-0100 Rev.1.00 Sep 29, 2008 Page 27 of 27 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 6.50 6.80 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.4 0.5 0.6 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. 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