SAMSUNG S3C72N2

S3C72N2/C72N4/P72N4
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4
offers an excellent design solution for a wide variety of applications that require LCD functions.
Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast
response to internal and external events. In addition, the S3C72N2/C72N4 's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.
OTP
The S3C72N2/C72N4 microcontroller is also available in OTP (One Time Programmable) version, S3P72N4 .
The S3P72N4 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM.
The S3P72N4 is comparable to S3C72N2/C72N4, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
FEATURES
Memory
Interrupts
— 288 × 4-bit RAM
— Two internal vectored interrupts
— 2048 × 8-bit ROM (S3C72N2)
— Two external vectored interrupts
— 4096 × 8-bit ROM (S3C72N4)
— Two quasi-interrupts
I/O Pins
Memory-Mapped I/O Structure
— Input only: 4 pins
— Data memory bank 15
— I/O: 12 pins
— Output: 8 pins sharing with segment driver
outputs
Two Power-Down Modes
— Idle mode (only CPU clock stops)
— Stop mode (main or sub system oscillation stops)
LCD Controller/Driver
— Maximum 16-digit LCD direct drive capability
Oscillation Sources
— 32 segment, 4 common pins
— Crystal, ceramic, or RC for main system clock
— Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
— Crystal or external oscillator for subsystem clock
8-Bit Basic Timer
— Programmable interval timer
— Watchdog timer
8-Bit Timer/Counter
— Programmable 8-bit timer
— Main system clock frequency: 4.19 MHz (typical)
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)
— External event counter
Operating Temperature
— Arbitrary clock frequency output
— – 40 °C to 85 °C
Watch Timer
Operating Voltage Range
— Real-time and interval time measurement
— 2.0 V to 5.5 V at 4.19 MHz
— Four frequency outputs to BUZ pin
— 1.8 V to 5.5 V at 3 MHz
— Clock source generation for LCD
Bit Sequential Carrier
Package Type
— Support 16-bit serial data transfer in arbitrary
format
— 64-pin QFP
1-2
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watchdog
Timer
INT0, INT1, INT2
RESET
P1.3/TCL0
P2.0/TCLO0
P6.0-P6.3/
KS0-KS3
P8.0-P8.7
SEG24-SEG31
8-Bit Timer/
Counter0
Interrupt
Control
Block
Basic
Timer
Watch
Timer
P2.3/BUZ
Xin Xout
XTin XTout
Interrupt
Control
Block
Internal
Interrupts
Instruction
Register
LCD
Driver/
Controller
Program
Counter
BIAS
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
P8.0-P8.7/
SEG24-SEG31
I/O Port 6
Output Port 8
Instruction Decoder
Program
Status
Word
Arithmetic
and
Logic Unit
Stack
Pointer
288 x 4-Bit
Data Memory
2/4 KByte
Program
Memory
Input
Port 1
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
I/O Port 2
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
I/O Port 3
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
64
63
62
61
60
59
58
57
56
55
54
53
52
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
PIN ASSIGNMENTS
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
VDD
VSS
Xout
Xin
TEST
XTin
XTout
RESET
S3C72N2
S3C72N4
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
20
21
22
23
24
25
26
27
28
29
30
31
32
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 1-2. S3C72N2/C72N4 64-QFP Pin Assignment
1-4
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72N2/C72N4 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
4-bit input port.
1-bit or 4-bit read and test is possible.
4-bit pull-up resistors are software
assignable.
17
18
19
20
INT0
INT1
INT2
TCL0
Input
A-4
P1.0
P1.1
P1.2
P1.3
I
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
4-bit pull-up resistors are software
assignable.
21
22
23
24
TCLO0
–
CLO
BUZ
Input
D
P3.0
P3.1
P3.2
P3.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
Each individual pin can be specified as
input or output. 4-bit pull-up resistors are
software assignable.
25
26
27
28
LCDCK
LCDSY
Input
D
P6.0–P6.3
I/O
4-bit I/O ports. Pins are individually
software configurable as input or output.
1-bit and 4-bit read/write and test is
possible. 4-bit pull-up resistors are
software assignable.
29–32
KS0–KS3
Input
D
P8.0–P8.7
O
Output port for 1-bit data (for use as
CMOS driver only)
40–33
SEG24–
SEG31
Output
H-1
SEG0–SEG23
O
LCD segment signal output
64–41
–
Output
H
SEG24–SEG31
O
LCD segment signal output
40–33
P8.0–P8.7
Output
H-1
COM0–COM3
O
LCD common signal output
1–4
–
Output
H
VLC0–VLC2
–
LCD power supply.
Built-in voltage dividing resistors
6–8
–
–
–
BIAS
–
LCD power control
5
–
–
–
LCD clock output for display expansion
25
P3.0
Input
D
LCDCK
I/O
1-5
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
Table 1-1. S3C72N2/C72N4 Pin Descriptions (Continued)
Pin Name
LCDSY
TCL0
TCLO0
Pin
Type
I/O
I
I/O
Description
Number
Share
Pin
Reset
Value
Circuit
Type
LCD synchronization clock output for
LCD display expansion
26
P3.1
Input
D
External clock input for timer/counter 0
20
P1.3
Input
A-4
Timer/counter 0 clock output
21
P2.0
Input
D
INT0
INT1
I
External interrupt. The triggering edge for
INT0 and INT1 is selectable. Only INT0 is
synchronized with the system clock.
17
18
P1.0
P1.1
Input
A-4
INT2
I
Quasi-interrupt with detection of rising
edge signals.
19
P1.2
Input
A-4
KS0–KS3
I/O
Quasi-interrupt input with falling edge
detection.
29–32
P6.0–P6.3
Input
D
CLO
I/O
CPU clock output
23
P2.2
Input
D
BUZ
I/O
2, 4, 8 or 16 kHz frequency output for
buzzer sound with 4.19 MHz main system
clock or 32.768 kHz subsystem clock.
24
P2.3
Input
D
XIN, XOUT
–
Crystal, ceramic or RC oscillator pins for
main system clock. (For external clock
input, use XIN and input XIN’s reverse
phase to XOUT)
12,11
–
–
–
XTIN, XTOUT
–
Crystal oscillator pins for subsystem
clock. (For external clock input, use XTIN
and input XTIN’s reverse phase to XTOUT)
14,15
–
–
–
VDD
–
Main power supply
9
–
–
–
VSS
–
Ground
10
–
–
–
RESET
–
Reset signal
16
–
Input
B
TEST
–
Test signal input (must be connected to
VSS)
13
–
–
–
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
1-6
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL
P-CHANNEL
DATA
OUT
IN
N-CHANNEL
N-CHNNEL
OUTPUT
DISABLE
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type C
VDD
VDD
PULL-UP
RESISTOR
PULL-UP
RESISTOR
P-CHANNEL
RESISTOR
ENABLE
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
IN
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A-4 (P1)
P-CHANNEL
CIRCUIT
TYPE C
I/O
CIRCUIT TYPE A
Figure 1-6. Pin Circuit Type D (P2, P3, and P6)
1-7
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
VLC0
VDD
VLC1
LCD SEGMENT/
COMMON DATA
OUT
IN
SCHMITT TRIGGER
VLC2
Figure 1-9. Pin Circuit Type B (RESET)
Figure 1-7. Pin Circuit Type H (SEG/COM)
VDD
VLC0
VLC1
LCD SEGMENT/
& PORT 8 DATA
OUT
VLC2
Figure 1-8. Pin Circuit Type H-1 (P8)
1-8
S3C72N2/C72N4/P72N4
13
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72N2/C72N4 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
STANDARD ELECTRICAL CHARACTERISTICS
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
MISCELLANEOUS TIMING WAVEFORMS
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL0 timing
— Input timing for RESET
— Input timing for external interrupts
STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
Table 13-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Supply Voltage
VDD
–
Input Voltage
VI1
Output Voltage
VO
Output Current High
I OH
Output Current Low
I OL
Rating
Units
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
All I/O ports
– 0.3 to VDD + 0.3
One I/O port active
– 15
mA
All I/O ports active
– 30
One I/O port active
+ 30 (Peak value)
+ 15 (note)
Total value for ports 2 and 3
+ 60 (Peak value)
+ 20
Total value for port 6
+ 50
+ 20
Operating Temperature
Storage Temperature
(note)
(note)
TA
–
– 40 to + 85
Tstg
–
– 65 to + 150
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ×
°C
Duty .
Table 13-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
All input pins except those
specified below for VIH2, VIH3
0.7 VDD
–
VDD
VIH2
Ports 1, 6, and RESET
0.8 VDD
–
VDD
VIH3
XIN, XOUT, and XTIN
VDD – 0.1
–
VDD
Input low
VIL1
Ports 2 and 3
–
–
0.3 VDD
voltage
VIL2
Ports 1, 6 and RESET
–
–
0.2 VDD
VIL3
XIN, XOUT, and XTIN
–
–
0.1
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 2, 3, 6 and BIAS
VDD – 1.0
–
–
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 only
VDD – 2.0
–
–
Input high
voltage
Output high
voltage
13-2
V
V
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 2, 3, 6
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL = 100 µA; Port 8 only
–
–
1
ILIH1
VIN = VDD
All input pins except those
specified below for ILIH2
–
–
3
ILIH2
VIN = VDD
XIN, XOUT and XTIN
ILIL1
VIN = 0 V
All input pins except XIN, XOUT,
and XTIN
ILIL2
VIN = 0 V
XIN, XOUT, and XTIN
Output high
leakage
current
ILOH1
VOUT = VDD
All output pins
Output low
leakage
current
ILOL
VOUT = 0 V
All output pins
Pull-up
resistor
RL1
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 6
25
50
100
VDD = 3 V
50
100
200
VIN = 0 V; VDD = 5 V
100
250
400
200
500
800
120
170
220
−
3
6
VDD = 3 V
5
15
VDD = 5 V
3
6
VDD = 3 V
5
15
± 45
± 90
Output low
voltage
Input high
leakage
current
Input low
leakage
current
RL2
µA
20
–
–
–3
– 20
–
–
3
µA
–3
KΩ
RESET
VDD = 3 V
LCD voltage
dividing
resistor
RLCD
COM output
RCOM
impedance
SEG output
RSEG
impedance
COM output
voltage
deviation
VDC
TA = 25 °C
VDD = 5 V
VDD = 5 V (VLC0-COMi)
–
mV
Io = ± 15uA (i= 0-3)
13-3
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 5 V (VLC0-SEGi)
Min
Typ
Max
Units
–
± 45
± 90
mV
V
SEG output
voltage
deviation
VDS
VLC0 Output
VLC0
TA = 25 °C
0.6VDD
– 0.2
0.6VDD
0.6VDD
+ 0.2
VLC1 Output
voltage
VLC1
TA = 25 °C
0.4VDD
– 0.2
0.4VDD
0.4VDD
+ 0.2
VLC2 Output
voltage
VLC2
TA = 25 °C
0.2VDD
– 0.2
0.2VDD
0.2VDD
+ 0.2
Io = ± 15uA (i= 0-31)
voltage
13-4
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current (1)
Symbol
IDD1
(2)
IDD2 (2)
IDD3
IDD4
IDD5
IDD6 (3)
Conditions
Main operating:
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
Main idle mode;
VDD = 5 V ± 10%
CPU = fx/4
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
Sub operating:
VDD = 3 V ± 10%
CPU = fxt/4,
SCMOD = 1001B
32 kHz crystal oscillator
Sub idle mode:
VDD = 3 V ± 10%
CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator
Stop mode:
VDD = 5V ± 10%
CPU=fxt/4, SCMOD = 1101B
Stop mode:
VDD = 5 V ± 10%
Min
Typ
Max
Units
–
3.5
2.5
8
5.5
mA
1.6
1.2
4
3
1
0.9
2.5
2
0.5
0.4
1.0
0.8
–
15
30
–
6
15
–
0.5
3
–
µA
CPU = fx/4, SCMOD = 0100B
NOTES:
1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors
2.
3.
and through LCD voltage dividing resistors.
Data includes the power consumption for sub-system clock oscillation.
When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction.
13-5
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
Table 13-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
Test Condition
Min
Typ
Max
Units
–
0.4
–
6.0
MHz
Stabilization time (2)
Stabilization occurs
when VDD is equal to
the minimum oscillator
voltage range.
–
–
4
ms
Oscillation frequency
–
0.4
–
6.0
MHz
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 4.5 V
–
–
30
(1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
VDD = 5 V
R = 20 KΩ, VDD = 5 V
R = 39 KΩ, VDD = 3 V
0.4
−
2.0
1.0
2
MHz
Oscillation frequency
(1)
C1
Crystal
Oscillator
Parameter
XIN
C2
XOUT
C1
(1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XIN
XOUT
XOUT
R
XIN input frequency
Frequency (1)
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
13-6
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
Table 13-4. Subsystem Clock Oscillator Characteristics
(TA = – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XT IN
Parameter
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 4.5 V to 5.5 V
–
1.0
2
s
VDD = 1.8 V to 4.5 V
–
–
10
–
32
–
100
KHz
–
5
–
15
µs
Oscillation frequency
XT OUT
(1)
C1
C2
Stabilization time (2)
External
Clock
Test Condition
XT IN XT OUT
XTIN input frequency
(1)
XTIN input high and
low level width (tXTL,
tXTH)
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
Table 13-5. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O capacitance
13-7
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
Table 13-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction cycle
Symbol
tCY
time (1)
TCL0 input
f TI0
tTIH0, tTIL0
low width
Interrupt input
tINTH, tINTL
high, low width
RESET Input Low
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
0.95
–
64
With subsystem clock (fxt)
114
122
125
0
–
1.5
MHz
1
MHz
–
–
µs
–
–
µs
–
–
µs
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
frequency
TCL0 input high,
Conditions
tRSL
VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
INT0
(2)
INT1, INT2, KS0–KS3
10
Input
10
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
13-8
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
CPU CLOCK
Main OSC. Freq.
1.5 MHz
1.0475 MHz
6 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Normal operation
Data retention supply current
IDDDR
Release signal set time
Oscillator stabilization wait
time
(1)
Conditions
Min
Typ
Max
Unit
1.5
–
6.5
V
VDDDR = 2.0 V
–
0.1
1
µA
tSREL
Normal operation
0
–
–
µs
tWAIT
Released by RESET
–
217 / fx
–
ms
Released by interrupt
–
(2)
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-9
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
t SREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
tSREL
t WAIT
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
13-10
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
0.8 VDD
0.2 VDD
Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / xf
tXL
t XH
Xin
VDD – 0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at Xin
1 / fxt
t XTL
t XTH
XTin
VDD – 0.1 V
0.1 V
Figure 13-6. Clock Timing Measurement at XTin
13-11
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
1 / f TI0
tTIL0
t TIH0
TCL0
0.8 V DD
0.2 V DD
Figure 13-7. TCL0 Timing
tRSL
RESET
0.2 VDD
Figure 13-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
KS0 to KS3
t INTH
0.8 VDD
0.2 VDD
Figure 13-9. Input Timing for External Interrupts and Quasi-Interrupts
13-12
S3C72N2/C72N4/P72N4
14
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The S3C72N2/C72N4 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 14-1.
23.90 ± 0.3
20.00 ± 0.2
0-8°
14.00 ± 0.2
64-QFP-1420F
+0.10
- 0.05
0.80 ± 0.20
0.10 MAX
#64
(1.00
)
17.90 ± 0.3
0.15
#1
0.05~0.25
+0.10
1.00
0.40 - 0.05
±
(1.00)
2.65 ± 0.10
0.15MAX
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 14-1. 64-QFP-1420F Package Dimensions
S3C72N2/C72N4/P72N4
15
S3P72N4 OTP
S3P72N4 OTP
OVERVIEW
The S3P72N4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C72N2/C72N4 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by a serial data format.
The S3P72N4 is fully compatible with the S3C72N2/C72N4, both in function and in pin configuration. Because of
its simple programming requirements, the S3P72N4 is ideal for use as an evaluation chip for the S3C72N4.
15-1
S3C72N2/C72N4/P72N4
64
63
62
61
60
59
58
57
56
55
54
53
52
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
S3P72N4 OTP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
S3P72N4
(Top View)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
20
21
22
23
24
25
26
27
28
29
30
31
32
COM0
COM1
COM2
COM3
BIAS
VLC0
SDAT/VLC1
SCLK/VLC2
VDD/VDD
VSS/VSS
Xout
Xin
VPP/TEST
XTin
XTout
RESET/RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
Figure 15-1. S3P72N4 Pin Assignments (64-QFP)
15-2
S3C72N2/C72N4/P72N4
S3P72N4 OTP
Table 15-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
Pin Name
During Programming
Pin Name
Pin No.
I/O
Function
VLC1
SDAT
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
VLC2
SCLK
8
I/O
Serial clock pin. Input only pin.
13
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
16
I
Chip initialization
9/10
I
Logic power supply pin. VDD should be tied to
+5 V during programming.
TEST
VPP (TEST)
RESET
RESET
VDD / VSS
VDD / VSS
Table 15-2. Comparison of S3P72N4 and S3C72N2/C72N4 Features
Characteristic
S3P72N4
S3C72N2/C72N4
Program Memory
4-Kbyte EPROM
2-K / 4-Kbyte mask ROM
Operating Voltage (VDD)
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
–
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P72N4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-3. Operating Mode Selection Criteria
VDD
5V
Vpp
(TEST)
REG/
R/W
MEM
Address
(A15-A0)
Mode
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means low level; "1" means high level.
15-3
S3P72N4 OTP
S3C72N2/C72N4/P72N4
Table 15-4. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
VIH1
All input pins except those
specified below for VIH2, VIH3
0.7 VDD
–
VDD
VIH2
Ports 1, 6, and RESET
0.8 VDD
–
VDD
VIH3
XIN, XOUT, and XTIN
VDD – 0.1
–
VDD
Input low
VIL1
Ports 2 and 3
–
–
0.3 VDD
voltage
VIL2
Ports 1, 6 and RESET
–
–
0.2 VDD
VIL3
XIN, XOUT, and XTIN
–
–
0.1
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 2, 3, 6 and BIAS
VDD – 1.0
–
–
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 only
VDD – 2.0
–
–
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 2, 3, 6
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL = 100 µA; Port 8 only
–
–
1
ILIH1
VIN = VDD
All input pins except those
specified below for ILIH2
–
–
3
ILIH2
VIN = VDD
XIN, XOUT and XTIN
–
–
20
ILIL1
VIN = 0 V
All input pins except XIN, XOUT,
and XTIN
–
–
–3
ILIL2
VIN = 0 V
XIN, XOUT, and XTIN
–
–
– 20
Output high
leakage
current
ILOH1
VOUT = VDD
All output pins
–
–
3
Output low
leakage
current
ILOL
VOUT = 0 V
All output pins
–
–
–3
Input high
voltage
Output high
voltage
Output low
voltage
Input high
leakage
current
Input low
leakage
current
15-4
V
V
V
µA
µA
µA
S3C72N2/C72N4/P72N4
S3P72N4 OTP
Table 15-4. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Pull-up
resistor
Symbol
RL1
RL2
Conditions
Min
Typ
Max
Units
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 6
25
50
100
KΩ
VDD = 3 V
50
100
200
VIN = 0 V; VDD = 5 V
100
250
400
200
500
800
120
170
220
–
3
6
VDD = 3 V
5
15
VDD = 5 V
3
6
VDD = 3 V
5
15
–
± 45
± 90
mV
–
± 45
± 90
mV
V
RESET
VDD = 3 V
LCD voltage
dividing
resistor
RLCD
COM output
RCOM
impedance
SEG output
RSEG
impedance
TA = 25 °C
VDD = 5 V
VDD = 5 V (VLC0-COMi)
COM output
voltage
deviation
VDC
SEG output
voltage
deviation
VDS
VLC0 Output
VLC0
TA = 25 °C
0.6VDD
– 0.2
0.6VDD
0.6VDD
+ 0.2
VLC1 Output
voltage
VLC1
TA = 25 °C
0.4VDD
– 0.2
0.4VDD
0.4VDD
+ 0.2
VLC2 Output
voltage
VLC2
TA = 25 °C
0.2VDD
– 0.2
0.2VDD
0.2VDD
+ 0.2
Io = ± 15uA (i= 0-3)
VDD = 5 V (VLC0-SEGi)
Io = ± 15uA (i= 0-31)
voltage
15-5
S3P72N4 OTP
S3C72N2/C72N4/P72N4
Table 15-4. D.C. Electrical Characteristics (Concluded)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current (1)
Symbol
IDD1
(2)
IDD2 (2)
IDD3
IDD4
IDD5
IDD6 (3)
Conditions
Main operating:
VDD = 5 V ± 10%
CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
Main idle mode;
VDD = 5 V ± 10%
CPU = fx/4
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
Sub operating:
VDD = 3 V ± 10%
CPU = fxt/4,
SCMOD = 1001B
32 kHz crystal oscillator
Sub idle mode:
VDD = 3 V ± 10%
CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator
Stop mode:
VDD = 5V ± 10%
CPU=fxt/4, SCMOD = 1101B
Stop mode:
VDD = 5 V ± 10%
Min
Typ
Max
Units
–
3.5
2.5
8
5.5
mA
1.6
1.2
4
3
1
0.9
2.5
2
0.5
0.4
1.0
0.8
–
15
30
–
6
15
–
0.5
3
–
µA
CPU = fx/4, SCMOD = 0100B
NOTES:
1. D.C. electrical values for supply current (IDD1 to IDD6) do not include current drawn through internal pull-up resistors
2.
3.
and through LCD voltage dividing resistors.
Data includes the power consumption for sub-system clock oscillation.
When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The mainsystem clock oscillation stops by the STOP instruction.
15-6
S3C72N2/C72N4/P72N4
S3P72N4 OTP
CPU CLOCK
Main OSC. Freq.
1.5 MHz
1.0475 MHz
6 MHz
4.19 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 15-2. Standard Operating Voltage Range
15-7
S3P72N4 OTP
S3C72N2/C72N4/P72N4
I OL (mA)
35.00
VDD = 5.5 V
VDD = 4.5 V
3.500/div
VDD = 3.3 V
VDD = 2.2 V
.0000
.0000
.2000/div
Figure 15-3. Port 2 IOL vs VOL Curve
15-8
2.000
VOL (V)