TI SMJ416160

SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
D
D
D
D
D
D
D
D
D
D
D
Organization . . . 1 048 576 by 16 Bits
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
’41x160-70
’41x160-80
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
70 ns
18 ns
35 ns
80 ns
20 ns
40 ns
READ OR
WRITE
CYCLE
MIN
130 ns
150 ns
Enhanced Page-Mode Operation for Faster
Memory Access
CAS-Before-RAS ( CBR) Refresh
Long Refresh Period
– ’416160 – 4 096-Cycle Refresh in 32 ms
(Maximum)
– ’418160 – 1 024-Cycle Refresh in 8 ms
(Maximum)
3-State Unlatched Output
Low Power Dissipation
All Inputs / Outputs Are TTL Compatible
Packaging
50-Lead, 650-Mil-Wide Ceramic Flatpack
Operating Free-Air Temperature Range
–55°C to 125°C
description
The SMJ41x160 series is a set of 16 777 216-bit
dynamic random-access memories (DRAMs)
organized as 1 048 576 words of 16 bits each.
They employ state-of-the-art technology for high
performance, reliability, and low power at low cost.
These devices feature maximum RAS access
times of 70 ns and 80 ns. All addresses and
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The SMJ41x160 series is offered in a 50-lead,
650-mil-wide ceramic flatpack and is characterized for operation from –55°C to 125°C.
HKD PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
NC
NC
NC
W
RAS
A11†
A10†
A0
A1
A2
A3
VCC
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
NC
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
† A10 and A11 are NC for SMJ418160.
PIN NOMENCLATURE
A0 – A11
DQ0 – DQ15
LCAS
UCAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-V Supply
Ground
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
logic symbol†
RAM 1M × 16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10‡
A11‡
21
22
23
24
27
28
29
30
31
32
20
19
20D8/21D0
A
0
1 048 575
20D15/21D7
20D16
20D17
20D18
20D19
C20[ROW]
G23/[REFRESH ROW]
RAS
LCAS
18
24[PWR DWN]
C21
G24
35
&
31
23C22
C21
G34
UCAS
34
&
31
23C32
Z31
24,25EN27
W 17
OE 33
DQ0 2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
3
4
5
7
8
9
10
41
42
DQ9
43
DQ10
DQ11 44
46
DQ12
47
DQ13
48
DQ14
49
DQ15
23,21D
34,25EN37
25
A,22D
∇26,27
A, Z26
A,32D
∇36,37
A, Z36
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
‡ A10 and A11 are NC for SMJ418160.
2
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SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
’416160 functional block diagram
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
8
Column Decode
256K Array
256K Array
A7
A8 –
A11
12
4
256K Array
R
o
w
256K Array
32
D
e
c
o
d
e
32
Row Address
Buffers
32
Sense Amplifiers
Column Address
Buffers
256K Array
32
I/O
Buffers
16 of 32
Selection
DataIn
Reg.
DataOut
Reg.
16
16
DQ0 – DQ15
256K Array
12
’418160 functional block diagram
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
Column Address
Buffers
256K Array
256K Array
A9
Row Address
Buffers
256K Array
R
o
w
256K Array
32
D
e
c
o
d
e
32
10
256K Array
32
32
I/O
Buffers
16 of 32
Selection
DataIn
Reg.
DataOut
Reg.
16
16
DQ0 – DQ15
256K Array
10
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SMJ416160, SMJ418160
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DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
operation
dual CAS
Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins
(DQ0– DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge.
All address-setup and -hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter tCAC) is measured from each individual xCAS to its corresponding DQx pin.
In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time
(see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early-write cycles, the data is latched on the first xCAS falling edge. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing
into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP .
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without
intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the device to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather
than when xCAS goes low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time (tRAH) has been satisfied, usually
well in advance of the falling edge of xCAS. In this case, data is obtained after access time from xCAS low (tCAC)
maximum if access time from column address (tAA) maximum has been satisfied. In the event that column
addresses for the next page cycle are valid at the time xCAS goes high, minimum-access time for the next cycle
is determined by access time from rising edge of the last xCAS (tCPA).
address: A0 – A11 (’416160) and A0 – A9 (’418160)
Twenty address bits are required to decode one of the 1 048 576 storage-cell locations. For the SMJ416160,
12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits
are set up on A0 through A7 and latched onto the chip by the first xCAS. For the SMJ418160, ten row-address
bits are set up on A0 – A9 and latched onto the chip by RAS. Ten column-address bits are set up on A0 – A9 and
latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and
xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xCAS
is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
4
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SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
data in (DQ0 – DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first xCAS occurrence with setup and hold times referenced to this signal. In
a delayed-write or read-modify-write cycle, xCAS is low already and the data is strobed in by W with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0 – DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval tCAC. tCAC begins with
the negative transition of xCAS as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh ’416160
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal-read or -write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
RAS-only refresh ’418160
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 1 024 rows (A0 – A9). A normal-read or -write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding
it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
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1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
V
Low-level input voltage (see Note 2)
–1
0.8
V
Supply voltage
0
V
V
TA
Operating free-air temperature
– 55
125
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
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SMJ416160, SMJ418160
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SMJ416160
TEST CONDITIONS†
PARAMETER
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current (leakage)
ICC1‡§
Read- or write-cycle current
ICC2
’416160 - 70
IOH = – 5 mA
VO = 0 V to VCC,
VCC = 5.5 V,
Minimum cycle
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and xCAS high
Standby current
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
VCC = 5.5 V,
xCAS high
MIN
’416160 - 80
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and xCAS high
MIN
MAX
2.4
UNIT
V
0.4
0.4
V
± 10
± 10
µA
± 10
± 10
µA
80
70
mA
2
2
mA
1
1
mA
ICC3§
Average refresh current (RAS only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
80
70
mA
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
80
70
mA
ICC7‡¶
Standby current, outputs enabled
RAS = VIH,
xCAS = VIL,
Data out = enabled
5
5
mA
tPC = MIN,
xCAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while xCAS = VIH
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DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SMJ418160
TEST CONDITIONS†
PARAMETER
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current (leakage)
ICC1‡§
Read- or write-cycle current
ICC2
’418160 - 70
IOH = – 5 mA
VO = 0 V to VCC,
VCC = 5.5 V,
Minimum cycle
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and xCAS high
Standby current
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
VCC = 5.5 V,
xCAS high
MIN
’418160 - 80
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and xCAS high
MIN
MAX
2.4
UNIT
V
0.4
0.4
V
± 10
± 10
µA
± 10
± 10
µA
180
170
mA
2
2
mA
1
1
mA
ICC3§
Average refresh current (RAS only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
180
170
mA
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
180
170
mA
ICC7‡¶
Standby current, outputs enabled
RAS = VIH,
xCAS = VIL,
Data out = enabled
5
5
mA
tPC = MIN,
xCAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while xCAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11#
8
pF
Ci(OE)
Input capacitance, OE
8
pF
Ci(RC)
Input capacitance, xCAS and RAS
8
pF
Ci(W)
Input capacitance, W
8
pF
Co
Output capacitance
10
pF
# A10 and A11 are NC for SMJ418160.
NOTE 3: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
8
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DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x160 - 70
PARAMETER
MIN
MAX
’41x160 - 80
MIN
MAX
UNIT
tAA
tCAC
Access time from column address
35
40
ns
Access time from xCAS low
18
20
ns
tCPA
tRAC
Access time from column precharge
40
45
ns
Access time from RAS low
70
80
ns
tOEA
tOFF
Access time from OE low
18
20
ns
20
ns
Output disable time after xCAS high (see Note 5)
0
18
0
tOEZ Output disable time after OE high (see Note 5)
0
18
0
20
ns
NOTES: 4. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data
state prior to the specified access time as the outputs are driven when xCAS and OE are low.
5. tOFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE or xCAS high.
timing requirements
’41x160- 70
’41x160- 80
MIN
MIN
MAX
MAX
UNIT
tRC
tWC
Cycle time, read (see Note 6)
130
150
ns
Cycle time, write (see Note 6)
130
150
ns
tRWC
tPC
Cycle time, read-write (see Note 6)
181
205
ns
Cycle time, page-mode read or write (see Notes 6 and 7)
45
50
ns
tPRWC
tRASP
Cycle time, page-mode read-write (see Note 6)
96
105
ns
Pulse duration, RAS low, page mode (see Note 8)
70 100 000
80 100 000
ns
tRAS
tCAS
Pulse duration, RAS low, nonpage mode (see Note 8)
70
10 000
80
10 000
ns
Pulse duration, xCAS low (see Note 9)
18
10 000
20
10 000
ns
tRP
tWP
Pulse duration, RAS high (precharge)
50
60
ns
Pulse duration, W low
10
10
ns
tASC
tASR
Setup time, column address before xCAS going low
0
0
ns
Setup time, row address before RAS going low
0
0
ns
tDS
tRCS
Setup time, data (see Note 10)
0
0
ns
Setup time, W high before xCAS going low
0
0
ns
tCWL
tRWL
Setup time, W low before xCAS going high
18
20
ns
Setup time, W low before RAS going high
18
20
ns
tWCS
tCAH
Setup time, W low before xCAS going low (early-write operation only)
0
0
ns
Hold time, column address after xCAS low
15
15
ns
tDH
tRAH
Hold time, data (see Note 10)
15
15
ns
Hold time, row address after RAS low
10
10
ns
tRCH
tRRH
Hold time, W high after xCAS high (see Note 11)
0
0
ns
Hold time, W high after RAS high (see Note 11)
0
0
ns
15
15
ns
tWCH
Hold time, W low after xCAS low (early-write operation only)
NOTES: 6. All cycle times assume tT = 5 ns, referenced to VIH(MIN) and VIL(MAX) .
7. To assure tPC min, tASC should be ≥ to tCP .
8. In a read-write cycle, tRWD and tRWL must be observed.
9. In a read-write cycle, tCWD and tCWL must be observed.
10. Referenced to the later of xCAS or W in write operations
11. Either tRRH or tRCH must be satisfied for a read cycle.
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DYNAMIC RANDOM-ACCESS MEMORIES
SGMS720D – APRIL 1995 – REVISED SEPTEMBER 1997
timing requirements (continued)
’41x160- 70
’41x160- 80
MIN
MIN
MAX
MAX
UNIT
tCLCH
tRHCP
Hold time, xCAS low to xCAS going high
5
5
ns
Hold time, RAS low after xCAS precharge
40
45
ns
tOEH
tROH
Hold time, OE command
18
20
ns
Hold time, RAS referenced to OE
10
10
ns
tCP
tAWD
Delay time, xCAS high (precharge)
10
10
ns
Delay time, column address to W going low (read-write operation only)
63
70
ns
tCHR
tCRP
Delay time, RAS low to xCAS going high (CBR refresh only)
10
10
ns
Delay time, xCAS high to RAS going low
5
5
ns
tCSH
tCSR
Delay time, RAS low to xCAS going high
70
80
ns
5
5
ns
tCWD
tOED
Delay time, xCAS low to W going low (read-write operation only)
46
50
ns
Delay time, OE to data
18
20
tRAD
tRAL
Delay time, RAS low to column address (see Note 12)
15
Delay time, column address to RAS going high
35
40
tCAL
tRCD
Delay time, column address to xCAS going high
35
40
Delay time, RAS low to xCAS low (see Note 12)
20
tRPC
tRSH
Delay time, RAS high to xCAS going low
0
0
ns
Delay time, xCAS low to RAS going high
18
20
ns
tRWD
tCPW
Delay time, RAS low to W going low (read-write operation only)
98
110
ns
Delay time, W going low after xCAS precharge (read-write operation only)
68
75
tREF
Delay time, xCAS low to RAS going low (CBR refresh only)
Refresh time interval
35
52
15
20
ns
40
ns
ns
ns
60
ns
ns
’416160
32
32
’418160
8
8
ms
tT
Transition time (see Note 13)
3
30
3
30
ns
NOTES: 12. The maximum value is specified only to ensure access time.
13. Transition times (rise and fall) should be a minimum of 3 ns and a maximum of 30 ns. This is ensured by design but not tested.
10
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PARAMETER MEASUREMENT INFORMATION
1.31 V
5V
RL = 218 Ω
R1 = 828 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
R2 = 295 Ω
(b) ALTERNATE LOAD CIRCUIT
VIH / VOH MIN
VIL / VOL MAX
(c) VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and fixture capacitance.
B. The ac timing parameters are specified with reference to the minimum valid high-level voltage
and the maximum valid low-level voltage for each signal. This corresponds to 2.4 V and 0.8 V
for inputs; 2.4 V and 0.4 V for outputs with the given load circuit.
Figure 1. Load Circuits and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRP
tRCD
tCAS
UCAS
tCLCH
(see Note A)
tCP
tCRP
LCAS
tCSH
tRSH
tRAD
tRAH
tASC
tCAL
tASR
Address
tRAL
Row
Column
Don’t Care
tRRH
tCAH
tRCS
W
DQ0 – DQ15
tRCH
tCAC
(see Note B)
tAA
Don’t Care
Don’t Care
tOFF
See Note D
Valid Data Out
See Note C
tRAC
tROH
OE
NOTES: A.
B.
C.
D.
Don’t Care
Don’t Care
tOEA
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
12
tOEZ
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PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
tRP
tRCD
tCAS
UCAS
tCLCH
(see Note A)
LCAS
tCP
tASR
tCRP
tCSH
tRSH
tRAH
tASC
tCAL
Address
Row
tRAL
Column
Don’t Care
tCAH
tCWL
tRAD
tRWL
W
Don’t Care
Don’t Care
tWP
tDH
(see Note B)
DQ0 – DQ15
Don’t Care
Don’t Care
Valid Data In
tDS (see Note B)
tOED
tOEH
OE
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Referenced to the first xCAS or W, whichever occurs last
C. xCAS order is arbitrary.
Figure 3. Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
tRP
tRCD
tCSH
tCRP
tCAS
UCAS
tRSH
tCLCH
(see Note A)
LCAS
tRAD
tCP
tASR
tRAH
tASC
tCAL
tRAL
Address
Column
Row
Don’t Care
tCAH
tWCS
tWCH
W
tCWL
tRWL
tWP
DQ0 – DQ15
Don’t Care
Don’t Care
Valid Data In
tDH
tDS
OE
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
Figure 4. Early-Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tRCD
tCAS
UCAS
tCSH
tCRP
tCLCH
(see Note A)
tCP
tRSH
tRAD
LCAS
tRAH
tASC
tASR
Address
Column
Row
Don’t Care
tCAH
tAWD
tRWL
tCWD
tRCS
W
tCWL
tWP
Don’t Care
Don’t Care
tRWD
See Note B
Valid Out
DQ8 – DQ15
Don’t Care
tAA
tRAC
tDH
tCAC
(see Note C)
tDS
tOEZ
tOEA
OE
Don’t Care
tOED
See Note B
Valid Out
DQ0 – DQ7
NOTES: A.
B.
C.
D.
Valid In
Don’t Care
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORIES
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRCD
tCRP
UCAS
tRHCP
tRSH
tCLCH
(see Note A)
tPC
tCSH
tCAS
tCP
tASR
LCAS
tRAH
tCAL
tASC
tRAL
tCAH
Address
Row
Don’t Care
Column
Column
Don’t Care
tRAD
W
tRRH
tRCH
Don’t
Care
Don’t
Care
tCAC
(see Note B)
tAA
tCPA
(see Note C)
tRCS
tRAC
tOFF
See Note D
Valid
Out
DQ8 – DQ15
tOEZ
tAA
See Note D
Valid
Out
DQ0 – DQ7
Valid
Out
tOEA
OE
Don’t Care
tOEA
Don’t Care
NOTES: A.
B.
C.
D.
E.
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
Access time is tCPA- or tAA-dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
16
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
UCAS
tRHCP
tPC
tCLCH
(see Note A)
tRCD
tCP
tCSH
LCAS
tCRP
tCAS
tASR
tCAH
tASC
tCAL
tRAH
Address
tRAL
Column
Row
Don’t Care
Don’t Care
Column
tRAD
tCWL
tCWL
tWCH
tRWL
tWP
See Note B
tDS
W
Don’t Care
DQ8 –
DQ15
Don’t Care
Don’t Care
Don’t Care
Valid In
tDH
DQ0 –
DQ7
See Note B
Valid In
Valid In
Don’t Care
tOED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Referenced to the first xCAS or W, whichever occurs last
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing
specifications are not violated.
D. xCAS order is arbitrary.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRCD
tRSH
tCRP
tPRWC
tCAS
UCAS
tCP
tCLCH
(see Note A)
LCAS
tASR
tASC
tCAH
tRAD
Address
Row
Column
Column
tCWD
tAWD
tRAH
tCWL
tWP
tRWL
tCPW
tRWD
W
tCAC
tAA
tRCS
tDS
tAA
tRAC
tCPA
(see Note B)
tDH
(see Note C)
Valid In
DQ0 – DQ15
Valid Out
tOEA
tOEH
Valid Out
Valid In
tOEH
tOEZ
tOED
OE
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
Access time is tCPA- or tAA-dependent.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
xCAS order is arbitrary.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F. tCAC is measured from xCAS to its corresponding DQx.
NOTES: A.
B.
C.
D.
E.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tCRP
tT
xCAS†
See Note A
Don’t Care
tASR
Address
Don’t Care
tRPC
tRAH
Don’t Care
Row
Row
Don’t Care
W
Hi-Z
DQ0 – DQ15
Don’t Care
OE
† LCAS or UCAS
NOTE A: All xCAS must be high.
Figure 9. RAS-Only Refresh-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
tRAS
tRAS
Refresh Cycle
tRP
RAS
tRP
tCHR
tCAS
xCAS†
tASR
tRAH
Address
tASC
tCAH
Row
Don’t Care
Col
tRRH
tRCS
W
Don’t Care
tRAC
tCAC
tAA
DQ0 – DQ15
tOFF
Valid Data
tOEZ
OE
tOEA
† LCAS or UCAS
Figure 10. Hidden-Refresh-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tRPC
xCAS†
tCSR
tCHR
tT
W
Don’t Care
Address
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ15
† LCAS or UCAS
NOTE A: Any xCAS can be used.
Figure 11. Automatic-xCBR-Refresh-Cycle Timing
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MECHANICAL DATA
HKD (R-CDFP-F50)
CERAMIC DUAL FLATPACK
0.665 (16,90)
0.634 (16,10)
1
50
0.031 (0,80)
0.843 (21,40)
0.811 (20,60)
0.766 (19,45)
0.746 (18,95)
0.020 (0,50)
0.012 (0,30)
25
26
0.370 (9,40)
0.250 (6,35)
0.015 (0,38) MIN
(4 Places)
Lid
0.140 (3,55)
0.110 (2,80)
0.009 (0,23)
0.004 (0,10)
0.030 (0,76) MIN
0.587 (14,90)
0.555 (14,10)
0.026 (0,66) MIN
4081537/B 10/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The leads will be gold plated.
22
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