STL57N65M5 N-channel 650 V, 0.061 Ω typ., 22.5 A MDmesh™ V Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet — production data Features Order code VDS @ TJmax RDS(on) max ID STL57N65M5 710 V 0.069 Ω 22.5 A(1) 3 3 3 ' $ 1. The value is rated according to Rthj-case and limited by package ■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance "OTTOMVIEW 0OWER&,!4X(6 Applications ■ Switching applications Figure 1. Description This device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Internal schematic diagram $ ' 3 !-V Table 1. Device summary Order code Marking Package Packaging STL57N65M5 57N65M5 PowerFLAT™ 8x8 HV Tape and reel January 2013 This is information on a product in full production. Doc ID 022996 Rev 2 1/16 www.st.com 16 Contents STL57N65M5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ........................... 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 8 Doc ID 022996 Rev 2 STL57N65M5 1 Electrical ratings Electrical ratings Table 2. Symbol Absolute maximum ratings Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 22.5 A ID (1) ID (1) Drain current (continuous) at TC = 100 °C 22 A (1),(2) Drain current (pulsed) 90 A ID (3) Drain current (continuous) at Tamb = 25 °C 4.3 A ID (3) Drain current (continuous) at Tamb = 100 °C 2.7 A Total dissipation at Tamb = 25 °C 2.8 W Total dissipation at TC = 25 °C 189 W IDM PTOT (3) PTOT (1) IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 9 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 960 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit 0.66 °C/W 45 °C/W dv/dt (4) Tstg Tj Storage temperature Max. operating junction temperature 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. When mounted on FR-4 board of inch², 2oz Cu. 4. ISD ≤ 22.5 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD=400 V Table 3. Symbol Rthj-case Rthj-amb(1) Thermal data Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max 1. When mounted on FR-4 board of inch², 2oz Cu. Doc ID 022996 Rev 2 3/16 Electrical characteristics 2 STL57N65M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS On /off states Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 Min. Typ. Max. Unit 650 V IDSS Zero gate voltage VDS = 650 V drain current (VGS = 0) VDS = 650 V, TC=125 °C 1 100 µA µA IGSS Gate-body leakage current (VDS = 0) ±100 nA 4 5 V 0.061 0.069 Ω Min. Typ. Max. Unit - 4200 100 6 - pF pF pF - 97 - pF - 344 - pF - 1.4 - Ω - 96 24 40 - nC nC nC VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onVGS = 10 V, ID = 17.5 A resistance Table 5. Symbol Dynamic Parameter Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance Co(er)(1) Equivalent output capacitance energy related Co(tr)(2) 3 Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 VGS = 0, VDS = 0 to 80% V(BR)DSS Equivalent output capacitance time related RG Intrinsic gate resistance f = 1 MHz open drain Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 520 V, ID = 17.5 A, VGS = 10 V (see Figure 15) 1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS 2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS 4/16 Doc ID 022996 Rev 2 STL57N65M5 Electrical characteristics Table 6. Symbol td(V) tr (V) tf(i) tc(off) Table 7. Symbol Switching times Parameter Test conditions Voltage delay time Voltage rise time Current fall time Crossing time VDD = 400 V, ID = 22.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 19) Parameter Test conditions Source-drain current ISDM (1)(2) Source-drain current (pulsed) trr Qrr IRRM trr Qrr IRRM Typ. - 84 10.8 11 16.5 Min. Typ. Max. Unit - ns ns ns ns Source drain diode ISD(1) VSD (3) Min. Max. Unit - 22.5 90 A A 1.5 V Forward on voltage ISD = 22.5 A, VGS = 0 - Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V (see Figure 16) - 378 7 37 ns µC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 22.5 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 16) - 454 9.5 42 ns µC A 1. The value is rated according to Rthj-case and limited by package 2. Pulse width limited by safe operating area 3. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 022996 Rev 2 5/16 Electrical characteristics STL57N65M5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance !-V )$ ! Zth PowerFLAT 8x8 HV K /P ,IM ERA ITE TION D IN BY TH M IS AX AR 2 E $3 O N A IS δ=0.5 0.2 S 0.1 S -1 10 0.05 0.02 MS 4J # 4C # Figure 4. -2 10 -5 10 6$36 Output characteristics Figure 5. AM14706v1 ID (A) VGS= 9, 10 V VGS= 8 100 Single pulse MS 3INLGE PULSE 0.01 -4 -2 -3 10 10 10 tp (s) Transfer characteristics AM14707v1 ID (A) VDS= 25 V 100 90 80 80 70 VGS= 7 V 60 60 50 40 40 30 20 VGS= 6 V 20 10 0 0 Figure 6. 5 10 15 20 0 3 25 VDS(V) Gate charge vs gate-source voltage Figure 7. !-V 6'3 6 6$3 6$3 6 6$$6 )$! 4 5 6 7 8 9 VGS(V) Static drain-source on-resistance !-V 2$3ON OHM 6'36 6/16 1GN# Doc ID 022996 Rev 2 )$! STL57N65M5 Figure 8. Electrical characteristics Capacitance variations Figure 9. AM14710v1 C (pF) Output capacitance stored energy AM14711v1 Eoss (µJ) 20 10000 Ciss 1000 15 100 Coss 10 10 Crss 5 1 0.1 1 100 10 Figure 10. Normalized gate threshold voltage vs temperature AM05459v1 VGS(th) (norm) 1.10 0 0 VDS(V) ID = 250 µA VDS = VGS 100 400 500 600 VDS(V) Figure 11. Normalized on-resistance vs temperature AM05460v1 RDS(on) (norm) 2.1 VGS= 10V ID= 17.5 A 1.9 1.00 200 300 1.7 1.5 1.3 0.90 1.1 0.80 0.9 0.7 0.70 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Normalized BVDSS vs temperature AM10399v1 VDS (norm) 1.08 0.5 -50 -25 25 50 75 100 TJ(°C) Figure 13. Switching losses vs gate resistance (1) AM15563v1 E (μJ) Eon VDD=400V VGS=10V ID=22.5A 700 ID = 1mA 1.06 0 600 1.04 500 1.02 400 Eoff 1.00 300 0.98 200 0.96 100 0.94 0.92 -50 -25 0 25 50 75 100 TJ(°C) 0 0 10 20 30 40 RG(Ω) 1. Eon including reverse recovery of a SiC diode Doc ID 022996 Rev 2 7/16 Test circuits 3 STL57N65M5 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 18. Unclamped inductive waveform V(BR)DSS AM01471v1 Figure 19. Switching time waveform Concept waveform for Inductive Load Turn-off Id VD 90%Vds 90%Id Tdelay-off -off IDM Vgs 90%Vgs on ID Vgs(I(t)) )) VDD VDD 10%Id 10%Vds Vds Trise AM01472v1 8/16 Doc ID 022996 Rev 2 Tfall Tcross --over AM05540v2 STL57N65M5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 022996 Rev 2 9/16 Package mechanical data Table 8. STL57N65M5 PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.95 1.00 1.05 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e L 10/16 2.00 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.10 Doc ID 022996 Rev 2 0.60 STL57N65M5 Package mechanical data Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data BOTTOM VIEW b CA B L bbb 0.40 E2 PIN#1 ID D2 C A ccc C A1 0.20±0.008 SIDE VIEW SEATING PLANE 0.08 C D A B E INDEX AREA aaa C TOP VIEW aaa C 8222871_Rev_B Doc ID 022996 Rev 2 11/16 Package mechanical data STL57N65M5 Figure 21. PowerFLAT™ 8x8 HV recommended footprint 0.60 7.70 4.40 7.30 2.00 1.05 Footprint 12/16 Doc ID 022996 Rev 2 STL57N65M5 Packaging mechanical data Figure 22. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) E (1.75±0.1) B0 (8.30±0.1) 5 Packaging mechanical data A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk quantity 3000 pcs 8229819_Tape_revA Figure 23. PowerFLAT™ 8x8 HV package orientation in carrier tape. Doc ID 022996 Rev 2 13/16 Packaging mechanical data STL57N65M5 Figure 24. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA 14/16 Doc ID 022996 Rev 2 STL57N65M5 6 Revision history Revision history Table 9. Document revision history Date Revision 14-May-2012 1 25-Jan-2013 2 Changes First release. – – – – – – – – Modified: ID value and note1 on first page Modified: ID, PTOT, IAR values, and note1, 4 on Table 2 Modified: Rthj-case value on Table 3 Modified: RDS(on) on Table 4 Modified: typical values on Table 5 and 6 Modified: typical and max values on Table 7 Inserted: Section 2.1: Electrical characteristics (curves) Document staus promoted from preliminary data to production data Doc ID 022996 Rev 2 15/16 STL57N65M5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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