DATA SHEET MOS INTEGRATED CIRCUIT µPD75P048 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P048 is a One-Time PROM version of the µPD75048. The µPD75P048 is suitable for small-scale production or experimental production in system development. Detailed functions are described in the following user’s manual. Read this manual when designing your system. µPD75048 User’s Manual: IEU-1278 FEATURES • The µPD75048 compatible • • • • • • • • The µPD75P048 for evaluation/pre-production, while the µPD75048 for mass-production 8064 × 8 bits of one-time programmable ROM 512 × 4 bits of RAM 1024 × 4 bits of EEPROM (Data memory area) Ports 0 to 3 and 6 to 8 with software-selectable pull-up resistors Port 9 with software-selectable pull-down resistors 12 N-channel open drain input/output ports (ports 4, 5, and 10) Low-voltage operation possible (VDD = 2.7 to 6.0 V) ORDERING INFORMATION Part number µPD75P048CW µPD75P048GC-AB8 Caution Package Quality grade 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP ( 14 mm) Standard Standard Pull-up/pull-down resistor mask options are not available. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-3239 (O.D. No. IC-8720) Date Published August 1994 P Printed in Japan The mark ★ shows major revised points. © 1994 µPD75P048 PIN CONFIGURATION (Top View) • 64-pin plastic shrink DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µ PD75P048CW SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREF– AN7 AN6 AN5 AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110 AVSS TI0/P13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS P30/MD0 P31/MD1 P32/MD2 P33/MD3 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 • 64-pin plastic QFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 RESET X1 X2 VPP XT1 XT2 VDD AVDD AVREF+ AVREF– AN7 µ PD75P048GC-AB8 P43 P42 P41 P40 MD3/P33 MD2/P32 MD1/P31 MD0/P30 VSS SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 BUZ/P23 PCL/P22 PPO/P21 2 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AVSS AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6 µPD75P048 ★ PIN IDENTIFICATION P00-03 : Port0 P10-13 : Port1 P20-23 : Port2 P30-33 : Port3 P40-43 : Port4 P50-53 : Port5 P60-63 : Port6 P70-73 : Port7 P80-83 : Port8 P90-93 : Port9 P100-103 : Port10 P110-113 : Port11 KR0-7 : Key Return SCK : Serial Clock SI : Serial Input SO : Serial Output SB0, 1 : Serial Bus 0, 1 RESET : Reset Input TI0 : Timer Input 0 PTO0 : Programmable Timer Output 0 BUZ : Buzzer Clock PCL : Programmable Clock INT0,1,4 : External Vectored Interrupt 0, 1, 4 INT2 : External Test Input 2 X1, 2 : Main System Clock Oscillation 1, 2 XT1, 2 : Subsystem Clock Oscillation 1, 2 MAR : Reference Integration Control MAI : Integration Control MAZ : Autozero Control MFT A/D mode MAT : External Comparate Timing Input PPO : Programmable Pulse Output ... MFT timer mode AN0-7 : Analog Input 0-7 AVREF+ : Analog Reference (+) AVREF- : Analog Reference (-) AVDD : Analog VDD AVSS : Analog VSS VDD : Positive Power Supply VSS : Ground VPP : Programming Power Supply MD0-MD3 : Mode Selection Remarks MFT: Multi-function timer 3 BIT SEQ. BUFFER INTBT TI0/P13 PTO0/P20 TIMER/ COUNTER #0 P00 - P03 PORT 1 P10 - P13 PORT 2 P20 - P23 DATA MEMORY PORT 3 P30/MD0 - P33/MD3 GENERAL REG. PORT 4 P40 - P43 PORT 5 P50 - P53 PORT 6 P60 - P63 PORT 7 P70 - P73 PORT 8 P80 - P83 PORT 9 P90 - P93 SP CY ALU INTT0 SI/SB1/P03 SO/SB0/P02 SCK/P01 PORT 0 PROGRAM COUNTER BANK SERIAL INTERFACE INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0 - KR3/P60 - P63 KR4 - KR7/P70 - P73 BUZ/P23 BLOCK DIAGRAM 4 BASIC INTERVAL TIMER INTERRUPT CONTROL PROM PROGRAM MEMORY 8064 × 8 BITS DECODE AND CONTROL RAM 512 × 4 BITS WATCH TIMER INTW AVDD AVREF+ AVREF– AVSS AN0 - AN3/P110 - P113 AN4 - AN7 A/D CONVERTER fx/2N MULTIFUNCTION TIMER CLOCK OUTPUT CONTROL PCL/P22 CLOCK DIVIDER CPU CLOCK Φ CLOCK GENERATOR SUB XT1 XT2 MAIN X1 STAND BY CONTROL X2 INTMFT VPP VDD VSS RESET PORT 10 P100 - P103 PORT 11 P110 - P113 µPD75P048 MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PPO/P21 EEPROM 1024 × 4 BITS µPD75P048 CONTENTS 1. PIN FUNCTIONS ························································································································· 6 1.1 PORT PINS ·········································································································································· 6 1.2 NON-PORT PINS ································································································································· 8 1.3 PIN INPUT/OUTPUT CIRCUITS ········································································································ 10 2. DIFFERENCES BETWEEN THE µPD75P048 AND THE µPD75048 ······································· 13 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY ····························································· 14 3.1 PROM WRITE AND VERIFY OPERATION MODE ·········································································· 14 3.2 PROM WRITE PROCEDURE ·············································································································· 15 3.3 PROM READ PROCEDURE ················································································································ 16 4. SCREENING OF ONE-TIME PROM MODEL ··········································································· 17 ★ 5. ELECTRICAL SPECIFICATIONS ·································································································· 18 ★ 6. PERFORMANCE CURVE (REFERENCE VALUE) ····································································· 32 ★ 7. PACKAGE DRAWINGS ··············································································································· 34 8. RECOMMENDED SOLDERING CONDITIONS ········································································· 36 ★ APPENDIX A. DEVELOPMENT TOOLS ·························································································· 37 ★ APPENDIX B. RELATED DOCUMENTS ·························································································· 38 ★ 5 µPD75P048 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) Pin Name Input/ Output Shared Pin P00 Input INT4 P01 I/O SCK P02 I/O SO/SB0 F -B P03 I/O SI/SB1 M -C P10 Input INT0 P11 INT1 P12 INT2 P13 TI0 P20 I/O PTO0 P21 PPO P22 PCL P23 BUZ P30 Note 2 P31 Note 2 MD1 P32 Note 2 MD2 P33 Note 2 MD3 I/O MD0 Function 4-bit input port (PORT0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits. When Reset I/O Circuit Type Note 1 × Input B F -A × Input B -C 4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits. × Input E-B Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits. × Input E-B With noise elimination function 4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits. Note 2 I/O – N-ch open-drain 4-bit I/O port (PORT4). Can withstand 10 V. Data input/output pins for the PROM write and verity (Four low-order bits). High impedance M-A P50 - P53 Note 2 I/O – N-ch open-drain 4-bit I/O port (PORT5). Can withstand 10 V. Data input/output pins for the PROM write and verify (Four high-order bits). High impedance M-A P40 - P43 Note 1. The circle ( ) indicates the Schmitt trigger input. 2. Can directly drive LEDs. 6 8-Bit I/O µPD75P048 1.1 PORT PINS (2/2) Pin Name Input/ Output Shared Pin P60 I/O KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 I/O Circuit Type Note Programmable 4-bit I/O port (PORT 6). Pull-up resistors can be provided by software in units of 4 bits. Input F -A 4-bit I/O port (PORT 7). A pull-up resistor can be provided by software in units of 4 bits Input F -A Input E-B Input E-D P80 - P83 I/O – 4-bit I/O port (PORT 8). A pull-up resistor can be provided by software in units of 4 bits. P90 - P93 I/O – 4-bit I/O port (PORT 9). A pull-up resistor can be provided by software in units of 4 bits. P100 I/O MAR P101 MAI P102 MAZ P103 MAT P110 Input AN0 P111 AN1 P112 AN2 P113 AN3 Note The circle ( 8-Bit I/O When Reset Function N-ch open drain 4-bit I/O port (PORT 10). Can withstand 10 V in open-drain mode. 4-bit input port (PORT 11). × × High impedance Input ★ M-A Y ) indicates the Schmitt trigger input. 7 µPD75P048 1.2 NON-PORT PINS (1/2) Pin Name Input/ Output Shared Pin TI0 Input P13 PTO0 I/O PCL When Reset I/O Circuit Type Note Input for receiving external event pulse signal for timer/event counter Input B -C P20 Timer/event counter output Input E-B I/O P22 Clock output Input E-B BUZ I/O P23 Output for arbitrary frequency output (for buzzer output or system clock trimming) Input E-B SCK I/O P01 Serial clock I/O Input F -A SO/SB0 I/O P02 Serial data output Serial bus I/O Input F -B SI/SB1 I/O P03 Serial data input Serial bus I/O Input M -C INT4 Input P00 Edge detection vectored interrupt input (either rising edge or falling edge detection) Input B INT0 Input P10 Edge detection vectored interrupt input (detection edge selectable) Input B -C Edge detection testable input (rising edge detection) Input B -C P11 INT1 INT2 Input P12 KR0 - KR3 I/O P60 - P63 Parallel falling edge detection testable input Input F -A KR4 - KR7 I/O P70 - P73 Parallel falling edge detection testable input Input F -A MAR I/O P100 MAI I/O P101 MAZ I/O MAT Reverse integration signal output High impedance M-A Integration signal output High impedance M-A P102 Auto-zero signal output High impedance M-A I/O P103 Comparator input High impedance M-A PPO I/O P21 AN0 - AN3 Input AN4 - AN7 In MFT integrating A/D converter mode In MFT timer mode P110 - P113 For A /D converter only – Timer pulse output 8-bit analog input Input E-B – Y-A Y-A AVREF+ Input – Reference voltage input (AVDD side) – Z-A AVREF– Input – Reference voltage input (AVSS side) – Z-A AVDD – – Positive power supply – – AVSS – – GND potential – – Note The circle ( ) indicates the Schmitt trigger input. Remark MFT: Multi-Function Timer 8 Function µPD75P048 1.2 NON-PORT PINS (2/2) Pin Name Input/ Output Shared Pin Function When Reset I/O Circuit Type Note 1 X1, X2 Input – Crystal/ceramic resonator connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. – – XT1, XT2 Input – Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test). – – RESET Input – System reset input – B MD0 - MD3 I/O P30 - P33 Input E-B VPP Note 2 – – Normally connected to VDD directly; +12.5 V is applied as the programming voltage during the PROM write/verify cycles. – – VDD – – Positive power supply – – VSS – – GND potential – – Note 1. The circle ( Operation mode selection pins during the PROM write/verify cycles. ) indicates the Schmitt trigger input. 2. The VPP should be connected to VDD directly in normal operation mode. If VPP and VDD pins are not connected, the µPD75P048 does not operate correctly. 9 µPD75P048 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each µPD75P048 pin is shown below in a simplified manner. (1/3) Type A (For Type E-B) Type D (For Type E-B, F-A) VDD VDD Data P-ch P-ch OUT IN Output disable N-ch CMOS input buffer Type B N-ch Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E-B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis Type B-C Type E-D VDD Data Output disable P.U.R. P-ch P.U.R. enable IN/OUT Type D Type A P.D.R. enable IN N-ch P.D.R. P.U.R.: Pull-Up Resistor 10 P.D.R.: Pull-Down Resistor µPD75P048 (2/3) Type F-A Type M-C VDD VDD P.U.R. P.U.R. enable P.U.R. P.U.R. enable P-ch P-ch IN/OUT Data IN/OUT Type D Data Output disable N-ch Output disable Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type Y Type F-B VDD P.U.R. P.U.R. enable P-ch VDD Output disable (P) AVDD IN AVDD P-ch N-ch + Sampling C – P-ch IN/OUT Data Output disable AVSS Reference voltage (from voltage tap of series resistor string) AVSS N-ch Input enable Output disable (N) P.U.R.: Pull-Up Resistor Type M-A Type Y-A IN instruction IN/OUT Data Output disable Input buffer N-ch (Can withstand + 10 V) AVDD IN P-ch N-ch AVDD Sampling C + – AVSS AVSS Middle-voltage input buffer (Can withstand + 10 V) Reference voltage (from voltage tap of series resistor string) P.U.R.: Pull-Up Resistor 11 µPD75P048 (3/3) Type Z-A AVREF+ Reference voltage AVREF– 12 µPD75P048 2. DIFFERENCES BETWEEN THE µPD75P048 AND THE µPD75048 The µPD75P048 is a One-Time PROM version of the µPD75048. The µPD75P048 has the same CPU and internal hardwares. Table 2-1 shows the differences between the µPD75P048 and the µPD75048. Bear in mind the differences between these two products when debugging or developing on an experimental basis your application system by using the one-time PROM model, and then mass-producing the application system by using the mask ROM model. Details for the CPU functions and internal hardwares are available in µPD75048 User’s Manual (IEU-1278). Table 2-1 Differences between the µPD75P048 and the µPD75048 Items Program Memory µPD75P048 µPD75048 One-time PROM Mask ROM • 0000H to 1F7FH • 8064 × 8 bits Pull-up Resistors Ports 0 to 3 and 6 to 8 Software-selectable Ports 4, 5 and 10 Pull-Down Resistors N/A Software-selectable Port 9 On-chip Mask-option P33/MD3 - P30/MD0 P33 - P30 VPP IC XT1 Feedback Resistor Pin Connection 60 - 63 (SDIP) 5 - 8 (QFP) ★ 16 (SDIP) 25 (QFP) Electrical Specification Mask-option ★ Current dissipation differs. For details, refer to Data Sheet of each model. Other ★ Circuit scale and mask layout differ. Consequently, noise immunity and noise radiation differ. Note The noise immunity and noise radiation of the PROM and mask ROM models differ. To replace the PROM mode, which has been used for experimental production of your application system with the mask ROM model for mass production of the application system, be sure to perform thorough evaluation by using the CS model (not ES model) of the mask ROM model. 13 ★ µPD75P048 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY The µPD75P048 contains 8064 bytes of PROM. The following table shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins. Pin Name Function VPP Normally 2.7 to 6 V; 12.5 V is applied during write/verify X1, X2 After a write/verify write, the X1 and X2 clock pins are pulsed. The inverted signal of the X1 should be input to the X2. Note that these pins are also pulsed during a read. MD0 - MD3 (P30 - P33) Operation mode selection pins. P40 - P43 (lower 4 bits) P50 - P53 (higher 4 bits) 8-bit data input/output pins for write and verify VDD Supply voltage. Normally 2.7 to 6 V; 6 V is applied during write/verify Caution The µPD75P048CW/GC do not have a UV erase window, thus the PROM contents cannot be erased with ultra-violet ray. 3.1 PROM WRITE AND VERIFY OPERATION MODE When 6 V and 12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/verify mode. The operation is selected by the MD0 to MD3 pins, as shown in the table. The other pins should be returned to VSS potential via pull-down resistors. Operation Mode Specification Operation Mode VPP VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Clear program memory address to 0 L H H H Write mode L L H H Verify mode H × H H Program inhibit ×: Don’t care. 14 µPD75P048 3.2 PROM WRITE PROCEDURE PROMs can be written at high speed using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 µs. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9). (10) Perform one additional write (duration of 1 ms × number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the VDD and VPP pins back to + 5 volts. (16) Turn off the power. The following figure shows steps (2) to (12). X repetition Write Verify Additional write Input data Output data Input data Address increment VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 15 µPD75P048 3.3 PROM READ PROCEDURE The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) Pull unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 µs. (4) Select the clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (8) Select the program inhibit mode. (9) Select the clear program memory address mode. (10) Return the VDD and VPP pins back to + 5 volts. (11) Turn off the power. The following figure shows steps (2) to (9). VPP VPP VDD VDD+1 VDD VDD X1 P40-P43 P50-P53 Output data MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 16 “L” Output data µPD75P048 4. ★ SCREENING OF ONE-TIME PROM MODEL Because of their structure, the one-time PROM models (µPD75P48CW and µPD75P48GC-AB8) cannot be fully tested by NEC before shipment. It is therefore recommended that you implement screening to verify the PROM after necessary data have been written to it, and after the PROM has been stored at high temperature under the following conditions: Storage Temperature Storage Time 125 ˚C 24 hours 17 µPD75P048 ★ 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Symbol Conditions Supply Voltage VDD Input Voltage VI1 Other than ports 4, 5, 10 VI2 Ports 4, 5, 10 w/pull-up resistor Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL Note Current Ratings Unit -0.3 to +7.0 V -0.3 to VDD+0.3 V -0.3 to VDD+0.3 V -0.3 to +11 V -0.3 to VDD+0.3 V 1 pin -10 mA All pins -30 mA Ports 0, 3, 4, 5 1 pin Peak 30 mA rms 15 mA Other than ports 0, 3, 4, 5 1 pin Peak 20 mA rms 5 mA Total of ports 0, 3 - 9, 11 Peak 170 mA rms 120 mA Peak 30 mA rms 20 mA Total of ports 0, 2, 10 Operating Temperature Topt -10 to +70 °C Storage Temperature Tstg -65 to +150 °C Note rms = Peak value x √Duty Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. EEPROM RATINGS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter Symbol Conditions Ratings Unit Write Times — 100,000 times Data Retention Time — 10 years CAPACITANCE (Ta = 25°C, VDD = 0 V) Parameter Input Capacitance Symbol CI Output Capacitance CO Input/Output CIO 18 Conditions f = 1 MHz MIN. TYP. MAX. 15 pF Pins other than those measured are at 0 V 15 15 pF Unit pF µPD75P048 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Ceramic X1 Item Oscillation frequency(fX) Note 1 VDD = oscillation voltage range Oscillation stabilization time Note 2 After VDD come to MIN. value of oscillation voltage range X2 C1 C2 VDD Crystal X1 Conditions Oscillation frequency (fX) Note 1 X2 C1 C2 Oscillation stabilization time Note 2 MIN. TYP. 2.0 MAX. 5.0 4 2.0 4.19 5.0 VDD = 4.5 to 6.0 V VDD External Clock X1 input frequency (fX) Note 1 X1 X2 µ PD74HCU04 X1 input high-, low-level widths (tXH, tXL) Note 3 2.0 MHz ms MHz 10 ms 30 ms 5.0 100 Note 3 Unit Note 3 250 MHz ns Note 1. Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD has reached the minimum volue of the oscillation voltage range or the STOP mode has been released. 3. When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high curent flows. • Do not extract signals from the oscillation circuit. 19 µPD75P048 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Crystal XT1 Oscillation frequency (fXT) XT2 R C3 Item Conditions Note 1 Oscillation stabilization time Note 2 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s 10 s 32 100 kHz 5 15 µs VDD = 4.5 to 6.0 V C4 VDD External Clock XT1 input frequency (fXT) Note 1 XT1 XT2 XT1 input high-, low-level widths (tXTH, tXTL) Note 1. Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after VDD has reached the minimum value of the oscillation voltage range. Caution When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 20 µPD75P048 DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Symbol Conditions MIN. TYP. MAX. Unit VIH1 Ports 2,3,8,9,11 0.7VDD VDD V VIH2 Ports 0,1,6,7, RESET 0.8VDD VDD V VIH3 Ports 4,5,10 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7VDD 10 V VDD-0.5 VDD V VIH4 X1, X2, XT1, XT2 VIL1 Ports 2-5, 8-11 0 0.3VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1, XT2 0 0.4 V High-Level Output Voltage VOH VDD = 4.5 to 6.0V, IOH = -1 mA VDD-1.0 V IOH = -100 µA VDD-0.5 V Low-Level Output Voltage VOL Low-level Input Voltage High-Level Input Leakage Current ILIH1 Ports 3,4,5 VDD = 4.5 to 6.0V, IOL = 15mA 0.4 2.0 V VDD = 4.5 to 6.0V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2VDD V SB0, 1 Open-drain pull-up resistor ≥ 1 kΩ VI = VDD Other than below 3 µA X1,X2,XT1 20 µA ILIH2 ILIH3 VI = 9V Ports 4,5,10 (open-drain) 20 µA Low-Level Input Leakage Current ILIL1 VI = 0V Other than below -3 µA X1,X2,XT1 -20 µA High-Level Output Leakage Current ILOH1 VO = VDD Other than below 3 µA ILOH2 VO = 9V Ports 4,5,10 (open-drain) 20 µA Low-Level Output Leakage Current ILOL VO = 0V -3 µA Internal Pull-Up Resistor RU1 Ports 0,1,2,3,6,7,8 (except P00) VI = 0V VDD = 5.0V±10% 15 80 kΩ VDD = 3.0V±10% 30 300 kΩ RU2 Ports 4,5,10 VO = VDD-2.0 V VDD = 5.0V±10% 15 70 kΩ VDD = 3.0V±10% 10 60 kΩ Internal Pull-Down Resistor ILIL2 RD Port 9 VIN = VDD VDD = 5.0V±10% 15 VDD = 3.0V±10% 10 40 40 40 70 kΩ 60 kΩ 21 µPD75P048 Parameter Supply Current Symbol IDD1 Note 1 Conditions 4.19MHz crystal MIN. VDD = 5V±10% Note 2 Note 3 TYP. MAX. Unit 5.5 17 mA oscillator VDD = 3V±10% 1.7 5.1 mA IDD2 C1 = C2 = 22pF HALT mode VDD = 5V±10% 900 2700 µA VDD = 3V±10% 450 1400 µA IDD3 32.768kHz Note 4 crystal oscillator Operation mode VDD = 3V±10% 100 300 µA HALT mode VDD = 3V±10% IDD4 IDD5 XT1 = 0V VDD = 5V±10% STOP mode VDD = 3V±10% 35 110 µA 0.5 20 µA 0.3 10 µA 5 µA 20 µA Ta = 25°C IDD6 32.768kHz oscillator STOP mode VDD = 3V±10% Note 5 6 Note 1. Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not included. 2. When µPD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011. 3. When µPD75048 operates in low-speed mode with PCC set to 0000. 4. When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used. 5. When STOP instruction is executed with SCC set to 0000. Note Supply current when EEPROM is accessed is shown in EEPROM Characteristics. 22 µPD75P048 AC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter Symbol Conditions w/main system clock MIN. VDD = 4.5 to 6.0V TYP. MAX. Unit 0.95 32 µs 3.8 32 µs 125 µs CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle) Note 1 tCY TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, LowLevel Widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Note 2 µs INT1, 2, 4 10 µs KR0-7 10 µs 10 µs w/subsystem clock Interrupt Input High-, Low-Level Widths tINTH, tINTL RESET Low-Level Width tRSL 114 INT0 122 Note 1. The CPU clock (Φ) cycle time is detCY vs VDD termined by the oscillation frequency (with main system clock) of the connected oscillator, system clock control register (SCC), and 32 processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics 6 at the main system clock. 5 2. 2tCY or 128/fX depending on the set(IM0). 4 Cycle time tCY [µs] ting of the interrupt mode register Operation quaranteed range 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 23 µPD75P048 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKH1 SI Set-Up Time (vs. SCK ↑) tSIK1 SI Hold Time (vs. SCK ↑ ) tKSI1 SCK ↓→ SO Output Delay Time tKSO1 TYP. MAX. 1600 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns 150 ns 400 RL = 1kΩ, CL = 100pF Note Unit ns VDD = 4.5 to 6.0V 250 ns 1000 ns MAX. Unit TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0V TYP. 800 ns 3200 ns 400 ns tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑) tKSI2 SCK ↓→ SO Output Delay Time tKSO2 VDD = 4.5 to 6.0V MIN. 400 RL = 1kΩ, CL = 100 pF Note VDD = 4.5 to 6.0V Note RL and CL are load resistance and load capacitance of the SO output line. 24 ns 300 ns 1000 ns µPD75P048 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol tKCY3 SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns tSIK3 150 ns SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 tKCY3/2 ns SCK ↓→ SB0, 1 Output Delay Time tKSO3 SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns Note RL = 1kΩ, CL = 100pF VDD = 4.5 to 6.0V 0 250 ns 0 1000 ns SBI MODE (SCK: external clock input (slave)) Parameter Symbol Conditions SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V SCK Ligh-, Low-Level Widths tKL4 tKH4 VDD = 4.5 to 6.0 V SB0, 1 Set-Up Time (vs. SCK ↑ ) MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns tSIK4 100 ns SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 tKCY4/2 ns SCK ↓→ SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns RL = 1kΩ, CL = 100pF Note VDD = 4.5 to 6.0V 0 300 ns 0 1000 ns Note RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines. 25 µPD75P048 A/D CONVERTER (Ta = -10 to +70°C, VDD = 2.7 to 6.0V, AVSS = VSS = 0V) Parameter Symbol Conditions Resolution Absolute Accuracy Conversion Time Sampling Time Note 2 TYP. 8 8 MAX. Unit 8 bit ±1.5 LSB tCONV 168/fX µs tSAMP 44/fX µs AVREF+ V 2.5V ≤ AVREF ≤ VDD Note 1 Note 3 MIN. Analog Input Voltage VIAN AVREF- Analog Supply Voltage AVDD 2.5 VDD V Reference Input Voltage AVREF+ 2.5V ≤ (AVref+) – (AVref-) 2.5 AVDD V Reference Input Voltage AVREF- 2.5V ≤ (AVref+) – (AVref-) 0 1.0 V Analog Input Impedance RAN 1000 AVREF Current AIREF 0.25 Note 1. Absolute accuracy excluding quantization error (± MΩ 2.0 mA 1 –2 LSB) 2. Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1 µs: fX = 4.19 MHz) 3. Time since execution of conversion start instruction until end of sampling (10.5 µs: fX = 4.19 MHz) 26 µPD75P048 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 27 µPD75P048 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKS01 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tSIK2 SB0,1 tKSO2 28 tKSI2 µPD75P048 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKS03,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKS03,4 INTERRUPT INPUT TIMING tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING tRSL RESET 29 µPD75P048 EEPROM CHARACTERISTICS Parameter Symbol Supply current for EEPROM access Note 1 IDD7 Conditions MIN. Note 2 4.19MHz crystal oscillator VDD = 5V+10% C1 = C = 22pF VDD = 3V+10% Note 3 TYP. MAX. Unit 6.5 20 mA 2 6 mA Note 1. Current flowing through the internal pull-up resistor is not included. 2. When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used. 3. When PCC is set to 0000 and the low-speed mode is used. EEPROM WRITE TIME Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock as follows: Oscillation Frequency of Main System Clock (fX) Setting of EEPROM Control Register Write time EWTC1 EWTC0 fX = 2.0 to 5.0 MHz 0 0 212 x 18/fX (17.6 ms) fX = 2.0 to 4.2 MHz 0 1 211 x 18/fX (8.8 ms) fX = 2.0 MHz 1 0 210 x 18/fX Remarks ( ): fX = 4.19 MHz LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –10 to +70°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current Note 1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization Wait Time Note 2 tWAIT Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Released by RESET Released by interrupt request 217/fX ms Note 3 ms Note 1. Does not include current flowing through internal pull-up resistor 2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3. Depends on the setting of the basic interval timer mode register (BTM) as follows: 30 BTM3 BTM2 BTM1 BTM0 – 0 0 0 WAIT time ( ): fX = 4.19 MHz 220/fX (approx. 250 ms) – 0 1 1 217/fX (approx. 31.3 ms) – 1 0 1 215/fX (approx. 7.82 ms) – 1 1 1 213/fX (approx. 1.95 ms) µPD75P048 DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 31 µPD75P048 6. PERFORMANCE CURVE (REFERENCE VALUE) IDD vs VDD (Crystal oscillation) (T a = 25 °C) 10 High-speed mode PCC = 0011 5.0 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 Main system clock HALT mode 1.0 0.5 Subsystem clock operation mode + Main system lock stopped Supply current IDD [mA] ★ Main system clock stopped + Subsystem clock HALT mode 0.1 0.05 Main system clock STOP mode + Subsystem clock oscillation 0.01 X1 0.005 22 pF 0.001 0 1 2 3 4 Supply voltage VDD [V] Note Does not include current flowing through EEPROM. 32 5 X2 XT1 XT2 Crystal oscillator Crystal oscillator 4.19 MHz 32.768 kHz 22 pF 22 pF V DD V DD 6 330 kΩ 22 pF 7 µPD75P048 IDD vs VDD (Crystal oscillation) (T a = 25 °C) 10 5.0 High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 1.0 Main system clock HALT mode 0.5 Supply current IDD [mA] Subsystem clock operation mode + Main system clock stopped Subsystem clock HALT mode + Main system clock stopped 0.1 0.05 Main system clock STOP mode + Subsystem clock oscillation 0.01 X1 0.005 22 pF 0.001 0 1 2 3 4 5 X2 XT1 XT2 Crystal oscillator Crystal oscillator 2.0 MHz 32.768 kHz 22 pF 22 pF V DD V DD 6 330 kΩ 22 pF 7 Supply voltage VDD [V] Note Does not include current flowing through EEPROM. 33 µPD75P048 7. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M R ITEM MILLIMETERS INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 34 µPD75P048 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 F Q 5°±5° S D C detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. 35 µPD75P048 ★ 8. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75P048 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-1207). For other soldering methods and conditions, consult NEC. Table 8-1 Soldering Conditions of Surface-Mount Type µPD75P048GC-AB8: 64-pin plastic QFP ( Soldering Method 14 mm) Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 235°C, time: 30 seconds max. (210°C min.), number of times: 2 max. <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. IR35-00-2 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1 max. <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow. VP15-00-2 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Caution Do not use two or more soldering methods in combination (except the pin partial heating method). Table 8-2 Soldering Conditions of Through-Hole Type µPD75P048CW: 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave soldering (lead parts only) Soldering bath temperature: 260°C max., time: 10 seconds max., Pin Partial Heating Pin temperature: 260oC max., time: 10 seconds max. Caution The wave soldering must be performed at the lead part only. Note that the soldering must not be directly contacted to the board. 36 µPD75P048 ★ APPENDIX A. DEVELOPMENT TOOLS The following development tools are readily available to support development of systems using µPD75P048: Hardware IE-75000-R Note 1 In-circuit emulator for 75X series IE-75001-R IE-75000-R-EM Note 2 Emulation board for IE-75000-R and IE-75001-R EP-75028CW-R Common emulation probe commonly used with µPD75028CW EP-75028GC-R Emulation probe commonly used with µPD75028GC, provided with EV-9200GC-64 PG-1500 EV-9200GC-64, 64-pin conversion socket PROM programmer PROM programmer adapter commonly used with µPD75P036. It is connected PA-75P036CW to PG-1500. PROM programmer adapter commonly used with µPD75P036GC. It is connected PA-75P036GC to PG-1500. Software IE Control Program Host machine PG-1500 Controller PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A Note 3) RA75X Relocatable IBM PC/ATTM (Refer to OS for IBM PC.) Assembler Note 1. Maintenance product 2. Not provided with IE-75001-R. 3. Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks For development tools from other companies, refer to 75X Series Selection Guide (IF-1027). OS for IBM PC As OS for IBM PC, the followings are supported. OS Version PC DOSTM Ver. 5.02 to Ver. 6.1 MS-DOS Ver. 3.30 to Ver. 5.00A 5.0/V IBM DOSTM Note 1 Note 2 J5.02/V Note 2 Note 1. Version later than 5.0 have a task swap function, but this function cannot be used with this software. 2. This supports English mode only. 37 µPD75P048 ★ APPENDIX B. RELATED DOCUMENTS Documents related to device Document Document No. User’s manual IEU-1278 Instruction list — 75X series selection guide IF-1027 Documents related to development tools Doument Hardware Software Document No. IE-75000-R/IE-75001-R user’s manual EEU-1416 IE-75000-R-EM user’s manual EEU-1294 EP-750028CW-R user’s manual EEU-1314 EP-75028GC-R user’s manual EEU-1306 PG-1500 user’s manual EEU-1335 RA75X assembler package user’s manual Operation EEU-1346 Language EEU-1343 PG-1500 controller user’s manual EEU1291 Other related documents Document Document No. Package manual IEI-1213 Semiconductor device - mounting maual IEI-1207 NEC semiconductor device quality grade IEI-1209 NEC semiconductor device reliabiliy quality control — Static electricity discharge (ESD) test — Semiconductor device quality guarantee guide Product guide related to microcomputer - other manufacturers MEI-1202 — Note The documents listed above are subject to change without notice. Be sure to use the latest document for designing. 38 µPD75P048 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 39 µPD75P048 [MEMO] NEC is manufacturing and selling the products under microcomputer (with on-chip EEPROM) patent license with the BULL CP8. This product should not be used for IC cards (SMART CARD). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation.