54FCT/74FCT273 Octal D Flip-Flop General Description Features The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Y Y Y Y Y Y Y Y Y Y ICC reduced to 40.0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com), 32 mA (Mil) NSC 54/74FCT273 is pin and functionally equivalent to IDT 54/74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing Ý5962-87656 Logic Symbols Connection Diagrams Pin Assignment for DIP, Flatpak and SOIC IEEE/IEC TL/F/10146–1 TL/F/10146 – 2 TL/F/10146 – 3 Pin Names D0 –D7 MR CP Q0 – Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs Pin Assignment for LCC TL/F/10146 – 4 FACTTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10146 RRD-B30M105/Printed in U. S. A. 54FCT/74FCT273 Octal D Flip-Flop March 1993 Mode Select-Function Table Inputs Operating Mode Outputs MR CP Dn Reset (Clear) L X X Qn L Load ‘1’ H L H H Load ‘0’ H L L L H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Transition Logic Diagram TL/F/10146 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Terminal Voltage with Respect to GND (VTERM) 54FCT 74FCT Supply Voltage (VCC) 54FCT 74FCT Input Voltage b 0.5 to a 7.0V b 0.5 to a 7.0V Temperature Under Bias (TBIAS) 74FCT 54FCT b 55§ C to a 125§ C b 65§ C to a 135§ C Storage Temperature (TSTG) 74FCT 54FCT b 55§ C to a 125§ C b 65§ C to a 150§ C DC Output Current (IOUT) Output Voltage Operating Temperature (TA) 54FCT 74FCT 4.5V to 5.5V 4.75 to 5.25V 0V to VCC 0V to VCC b 55§ C to a 125§ C 0§ C to a 70§ C Junction Temperature (TJ) CDIP PDIP 175§ C 140§ C Note: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from b 40§ C to a 125§ C. 120 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM FCT circuits outside databook specifications. DC Characteristics for ’FCT Family Devices Typical values are at VCC e 5.0V, 25§ C ambient and maximum loading. For test conditions shown as Max, use the value specified for the appropriate device type: Com: VCC e 5.0V g 5%, TA e 0§ C to a 70§ C; Mil: VCC e 5.0V g 10%, TA e b55§ C to a 125§ C, VHC e VCC b 0.2V Symbol 54FCT/74FCT Parameter Min VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage IIH Typ Units Conditions Max 2.0 V 0.8 V Input High Current 5.0 5.0 mA VCC e Max VI e VCC VI e 2.7V (Note 2) IIL Input Low Current b 5.0 b 5.0 mA VCC e Max VI e 0.5V (Note 2) VI e GND VIK Clamp Diode Voltage IOS Short Circuit Current b 60 b 120 VOH Minimum High Level Output Voltage 2.8 3.0 VHC 2.4 2.4 VCC 4.3 4.3 b 0.7 b 1.2 V mA VCC e Min; IN e b18 mA VCC e Max (Note 1); VO e GND VCC e 3V; VIN e 0.2V or VHC; IOL e b32 mA V 3 VCC e Min VIN e VIH or VIL IOH e b300 mA IOH e b12 mA (Mil) IOH e b15 mA (Com) DC Characteristics for ’FCT Family Devices (Continued) Typical values are at VCC e 5.0V, 25§ C ambient and maximum loading. For test conditions shown as Max, use the value specified for the appropriate device type: Com: VCC e 5.0V g 5%, TA e 0§ C to a 70§ C; Mil: VCC e 5.0V g 10%, TA e b55§ C to a 125§ C, VHC e VCC b 0.2V Symbol Parameter 54FCT/74FCT Min VOL ICC Maximum Low Level Output Voltage Maximum Quiescent Supply Current DICC Quiescent Supply Current; TTL Inputs HIGH ICCD Dynamic Power Supply Current (Note 4) Input Hysteresis on Clock Only IC Total Power Supply Current (Note 6) GND 0.2 GND 0.3 0.3 0.2 0.5 0.5 V 1.0 40.0 mA VCC e Max VIN t VHC, VIN s 0.2V fI e 0 0.5 2.0 mA VCC e Max VIN e 3.4V (Note 3) VIN t VHC VIN s 0.2V mA/MHz VCC Max Outputs Open MR e VCC One Input Toggling 50% Duty Cycle 0.40 200 VCC e 3V; VIN e 0.2V or VHC; IOL e 300 mA Input Hysteresis on Clock Only VCC e Min VIN e VIH or VIL IOL e 300 mA IOL e 48 mA (Mil) IOL e 32 mA (Com) mV 1.5 4.0 VCC e Max Outputs Open MR e VCC VIN t VHC VIN s 0.2V 1.8 6.0 fI e 10 MHz One Bit Toggling 50% Duty Cycle VIN e 3.4V VIN e GND (Note 5) VCC e Max Outputs Open MR e VCC VIN t VHC VIN s 0.2V fI e 2.5 MHz Eight Bits Toggling 50% Duty Cycle VIN e 3.4V VIN e GND mA VH Conditions Max 0.25 VH Units Typ 3.0 7.8 5.0 16.8 200 mV Note 1: Maximum test duration not to exceed one second, not more than one output shorted at one time. Note 2: This parameter guaranteed but not tested. Note 3: Per TTL driven input (VIN e 3.4V); all other inputs at VCC or GND. Note 4: This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Note 5: Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. Note 6: IC e IQUIESCENT a IINPUTS a IDYNAMIC IC e ICC a DICC DHNT a ICCD (fCP/2 a fI NI) ICC e Quiescent Current DICC e Power Supply Curent for a TTL High Input (VIN e 3.4V) DH e Duty Cycle for TTL inputs High NT e Number of Inputs at DH ICCD e Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP e Clock Frequency for Register Devices (Zero for Non-Register Devices) fI e Input Frequency NI e Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 4 AC Electrical Characteristics Symbol Parameter 54FCT/74FCT 74FCT 54FCT TA e a 25§ C VCC e 5.0V TA, VCC e Com RL e 500X CL e 50 pF TA, VCC e Mil RL e 500X CL e 50 pF Units Typ Min Max Min Max tPHL tPLH Propagation Delay Clock to Output 7.0 2.0 13.0 1.5 9.5 ns tPLH tPHL Propagation Delay MR to Output 8.0 2.0 13.0 1.5 10.5 ns tSU Setup Time HIGH or LOW Data to CP 1.5 3.0 3.5 ns th Hold Time HIGH or LOW Data to CP 1.0 2.0 2.0 ns tw Clock Pulse Width HIGH or LOW 4.0 7.0 5.0 ns tw MR Pulse Width HIGH or LOW 4.0 7.0 5.0 ns trec Recovery Time MR to CP 3.0 4.0 4.0 ns fmax Maximum Clock Frequency 90 MHz Note 1: Minimum limits are guaranteed but not tested on Propagation Delays. Capacitance TA e 25§ C, f e 1.0 MHz Typ Max Unit CIN Symbol Input Capacitance Parameter VIN e 0V Conditions 6 10 pF COUT Output Capacitance VOUT e 0V 8 12 pF Note: This parameter is guaranteed by characterization data and not tested. Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74FCT 273 P Temperature Range Family 74FCT e Commercial TTL-Compatible 54FCT e Military TTL-Compatible C QR Special Variations X e Devices shipped in 13× reels QR e Commercial grade device with burn-in QB e Military grade with environmental and burn-in processing shipped in tubes. Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 5 Physical Dimensions inches (millimeters) 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead Small Outline Integrated Circuit (S) NS Package Number M20B 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20B 7 54FCT/74FCT273 Octal D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Lit. Ý 114706 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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