DISCRETE SEMICONDUCTORS DATA SHEET BGY284 power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 Preliminary specification 2003 Aug 20 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 FEATURES • Quad band GSM amplifier • Very small size (8 x 8 mm). • Suited for GPRS class 12 (duty cycle 4 : 8) • Integrated power control loop • 3.5 V nominal supply voltage • 35 dBm controlled output power for GSM850/EGSM900 • 32.5 dBm controlled output power for DCS1800/PCS1900 • Easy on/off and band select by digital control voltage • Internal input and output matching • Specification based on 3GPP TS 45.005. APPLICATIONS • Digital cellular radio systems with Time Division Multiple Access (TDMA) operation (GSM systems) in four frequency bands: 824 to 849 MHz, 880 to 915 MHz, 1710 to 1785 MHz and 1850 to 1910 MHz. DESCRIPTION The BGY284 is a power amplifier module in a SOT775 surface mounted package with a plastic cap. The module consists of two separated line-ups, one for low band (LB,GSM850/EGSM900) and one for high band (HB, DCS1800/PCS1900) with internal power detection function, power control loop, input and output matching. See the simplified internal circuit on page 4. The power control circuit ensures a stable power output set by the level of VDAC and stabilised to compensate variations of supply voltage, input power and temperature, with a control range fully compliant with ETSI time mask and power spectrum requirements QUICK REFERENCE DATA RF performance at Tmb = 25 °C (mounting base temperature); VBAT = 3.5 V; VSTAB = 2.8 V; ZS = ZL = 50 Ω; PD = 0 dBm; δ = 2:8 MODE OF OPERATION Typical pulsed, controlled output power 2003 Aug 20 f (MHz) PL (dBm) η (%) 824 to 849 34 50 880 to 915 34 50 1710 to 1785 31.3 45 1850 to 1910 31.3 45 2 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 PINNING - SOT775 SYMBOL PIN NUMBER PIN TYPE DESCRIPTION GND 1, 13, 15 ground ground VBAT 2, 3 supply battery connection of DCS1800/PCS1900 VBAT 11, 12 supply battery connection of GSM850/EGSM900 line-up RFin,HB 4 input, analog DCS1800/PCS1900 transmit RF input VTXon 5 input, logic power control enable input VDAC 6 input, analog RF power control input VSTAB 7 supply stabilized supply voltage input, logic LB (GSM850/EGSM900) HB (DCS1800/PCS1900) band select input Vband 8 9 not connected RFin,LB 10 input, analog GSM850/EGSM900 transmit RF input RFout,LB 14 output, analog GSM850/EGSM900 transmit RF output RFout,HB 16 output, analog DCS1800/PCS1900 transmit RF output inner pads ground ground Note: VBAT signals (pin numbers 2, 3, 11, 12) are not internally connected and must all be connected to the battery supply voltage RFin,HB VBAT 4 3 VBAT VTXon 5 2 VDAC 6 16 RFout,HB VSTAB 7 15 GND Vband 8 14 RFout,LB N.C. 9 10 11 12 RFin,LB VBAT VBAT Top view Fig.1 Simplified outline 2003 Aug 20 3 1 GND 13 GND Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 INTERNAL CIRCUIT 850/900 MHz PA RFin,LB biasing output match RFout,LB output match RFout,HB power sense VDAC + - Power controller VSTAB vTXon Logic control * * vband biasing power sense RFin,HB 1800/1900 MHz PA BGY284 Fig.2 Internal circuit 2003 Aug 20 4 * = pull down resistor Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 FUNCTIONAL DESCRIPTION Operating conditions The BGY284 is designed to meet the 3GPP TS 45.005 technical specification for the European Telecommunication Standards Institute (ETSI). Power amplifier The low band (GSM850 and EGSM900) and the high band (DCS1800 and PCS1900) power amplifiers both consist of 3 cascaded gain stages. Input and output matching as well as harmonic filters are integrated in the module. The output power is controlled by means of an internal control signal (generated in the power controller block) that is used to adapt the biasing of the 3 stages of an amplifier. For every line-up the power amplifier block generates a detected output power signal, that is an input to the power control block. Control logic In the control logic block the various signals are generated to control the complete BGY284 out of VTXon and Vband, as indicated in the mode control table. The VSTAB is used as supply for the control logic. When VSTAB = 0 V the BGY284 is in idle mode and the battery current consumption is almost zero. The VTXon signal “HIGH” enables the power control block. When Vband signal is “LOW” the low band (GSM850/EGSM900) line-up is enabled, when the Vband signal is “HIGH” the high band (DCS1800/PCS1900) channel is enabled. On both VTXon and Vband inputs there are pull down resistors of approximately 1 MΩ. Power controller Main inputs to the power controller block are the VDAC and the internal generated detected output power signals from the power amplifier block. The VDAC signal is the reference voltage for the requested output power level, and usualy is generated by an external digital analog converter. The VDAC signal is buffered and compared to the detected output power signal. The error signal is then further amplified by the integrator. Dependent on the Vband signal one of the integrators are selected. The output of the selected integrator is the internal control signal that sets the biasing circuits of the selected channel. Mode control MODE VSTAB Mode description (V) VTXon Vband VDAC (V) Idle complete PA off, minimal leakage current 0 0 0 <0.15 Standby control logic functioning, PA off 2.6...3 0 logic 1 or logic 0 <0.15 LB TX low band transmit mode 2.6...3 1 0 <2.5 HB TX high band transmit mode 2.6...3 1 1 <2.5 2003 Aug 20 5 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 TIMING DIAGRAM dB PL LB,HB +4 +1 -1 -6 (**) -30 (***) (147 bits) (*) 10 µs 7056/13 (542.8) µs 8 µs 10 µs 10 µs 8 µs t 10 µs VSTAB VTXon Vband PD LB,HB VDAC Fig.3 Timing diagram TIMING CHARACTERISTICS ZS = ZL = 50 Ω; −3 ≤ PD HB,LB ≤ 3 dBm; 3.1 ≤ VBAT ≤ 4.6 V; 2.6 ≤ VSTAB ≤ 3.0 V; −20 ≤ Tmb ≤ 85 °C; 1 : 8 ≤ δ ≤ 4 : 8; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT td1 delay time; VSTAB high voltage input power before transition VTXon to logic 1 0 − − µs td2 delay time; Vband to logic 0 or logic 1 before VTXon transition to logic 1 0 − − µs td3 delay time; RF signal on RFin HB,LB before VDAC ramp 0 − − µs td4 delay time; voltage step on VDAC after transition VTXon to logic 1 10 − − µs td5 delay time; transition of VTXon to logic 0 after VDAC signal to off 0 − − µs td6 delay time; VSTAB to 0, after VTXon to logic 0 10 − − µs td7 delay time; change of Vband after VTXon to logic 0 0 − − µs td8 delay time; removal of RF signal on RFin HB,LB after VDAC signal to off 0 − − µs 2003 Aug 20 6 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 DESCRIPTION RAMP-UP Minimum td1 before VTX on becomes high (control loop becomes active) the VSTAB must be available. The Vband signal will select the correct transmit channel (LB = GSM850/EGSM900, or HB = DCS1800/PCS1900). The Vband signal must be at the correct value no later than the rising edge of the VTXon signal. The VTXon signal going high enables the power control loop. To set-up the right internal biasing conditions and charge the integration capacitors to the right starting value there is a set-up time of VTXon before the first increase of VDAC. Before VDAC signal is ramping high there has to be RF power on the input of the selected channel (PD LB,HB). VDAC has to step up to the voltage level to get the required power level. Sequence of VDAC steps can be chosen to have approximately a quarter cosine wave ramp-up of PL LB,HB in such a way that there is no violation of the GSM power mask, and that in the same time there is no violation of the spectrum due to transients. To avoid violation of the lowest power level in the GSM power mask (indicated by *), the BGY284 has to give sufficient isolation in following condition: VTXon high, VDAC minimum value, RF power on input of PA. For GSM850/EGSM900 the system specification for maximum output power level of the handset in this condition is −36 dBm. For DCS1800/PCS1900 the system specification in this condition is −48 dBm. In the handset the antenna switch can still be in Rx mode and therefore still provide isolation between the PA and the antenna. This situation is accounted in the isolation conditions in electrical characteristics transmit mode. DESCRIPTION RAMP-DOWN VDAC will step down from the voltage level for the current power level to offstate. Sequence of VDAC steps can be chosen to have approximately a quarte cosine wave ramp-down of PL LB,HB in such a way that there is no violation of the GSM power mask, and that in the same time there is no violation of the spectrum due to transients. The control loop can be switched off (VTXon signal going to logic 0) as soon as the VDAC has reached the offstate level. At the same time also the Vband signal is allowed to change polarity and the RF input power (PD LB,HB) at the selected channel can be removed. Because there is no input power anymore there is no additional isolation specification required to meet the GSM system specification. For GSM850/EGSM900 the system specification for maximum output power level of the handset in this condition is −54 dBm. For DCS1800/PCS1900 the system specification in this condition is −48 dBm. td6 after VTXon signal going to logic 0 (control loop is switched off) and all charge in the internal capacitors of the control loop has been removed the BGY284 can go into idle mode (VSTAB can go to 0 V). 2003 Aug 20 7 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT idle mode − 7 V HB TX or LB TX mode − 5.3 V DC supply voltage −0.5 3.3 V supply current − 2 mA VDAC DC output power control voltage − 3 V IDAC current into output power control input −2 +2 mA PD HB, PD LB input drive power on RFin HB,LB − 10 dBm PL LB load power from RFout LB − 37 dBm PL HB load power from RFout HB − 35 dBm Vband band switch voltage −0.5 +3.3 V Iband band switch current −2 +2 mA VTXon transmit control signal −0.5 +3.3 V ITXon current into transmit control input PBAT power from supply during pulse VBAT DC supply voltage VSTAB ISTAB IBAT −2 +2 mA HB TX mode − 4 W LB TX mode − 7 W current from supply during pulse HB TX mode − 1.4 A LB TX mode − 2.2 A −40 +100 °C Tstg storage temperature Tmb operating mounting base temperature 2003 Aug 20 δ=2:8 −30 +100 °C δ=4:8 −30 +90 °C 8 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 DC CHARACTERISTICS ZS = ZL = 50 Ω; PD HB, LB = 0 mW; VBAT = 3.5 V; VSTAB = 2.8 V; Tmb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VOLTAGE SUPPLY VBAT IBAT VSTAB ISTAB battery supply voltage leakage current supply voltage current consumption Note 1 2.9 − 3.1 V typical oprating range 3.1 3.6 4.6 V Note 2 4.6 − 5.2 V standby mode − − 25 µA idle mode − − 10 µA standby, HB TX or LB TX mode 2.6 2.8 3.0 V idle mode 0 − 0.2 V HB TX or LB TX mode − − 1 mA standby mode − − 10 µA ZS = ZL = 50 Ω; −3 ≤ PD HB,LB ≤ 3 dBm; 3.1 ≤ VBAT ≤ 4.6 V; 2.6 ≤ VSTAB ≤ 3.0 V; −20 ≤ Tmb ≤ 85 °C; 1 : 8 ≤ δ ≤ 4 : 8; unless otherwise specified DIGITAL INPUTS: V TXon, Vband Vil logic low voltage 0 − 0.5 V Vih logic high voltage 0.9 − 3 V Iil current at low voltage − − 3 µA Iih current at high voltage − − 15 µA Ci input capacitance − 4 − pF 0 − 2.5 V ANALOG INPUTS: VDAC VDAC power control voltage IDAC power control current −100 − − µA CDAC input capacitance of VDAC − 4 − pF RDAC input resistance of VDAC − 1.2 − MΩ Note 1. PA is functional from 2.9 to 3.1 V, but will not meet all electrical specification points. 2. PA is functional from 4.6 to 5.2 V under 50 Ω conditions, but will not meet all electrical specification points. 2003 Aug 20 9 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 ELECTRICAL CHARACTERISTICS GSM850 AND EGSM900 TRANSMIT MODE ZS = ZL = 50 Ω; VBAT = 3.6 V; VSTAB = 2.8 V; Tmb = 25 °C; 1 : 8 ≤ δ ≤ 4 : 8; 575 ≤ tp ≤ 2300 µs; PD LB = 0 dBm; spurious on PD LB < −50 dBm; LB TX mode selected; f = 824 to 849 MHz for GSM850; f = 880 to 915 MHz for EGSM900;unless otherwise specified. SYMBOL PARAMETER UNIT 0 +2 dBm − 2 V f = 897.5 MHz for EGSM900; f = 836.5 MHz for GSM850; PL LB = 5 dBm 0.2 − − V VDAC = 2.2 V 35.2 36 − dBm VDAC = 2.2 V; VBAT = 3.2 V; PD LB = −2 dBm; Tmb = 85 °C 34.1 − − dBm efficiency GSM850 saturated power − 55 − % PL LB = 34 dBm − 50 − % efficiency EGSM900 saturated power − 50 − % PL LB = 34 dBm − 45 − % VDAC set to have 31 ≤ PL LB ≤ 34 dBm; see note 1 and 2 −1 − 1 dB VDAC set to have 13 ≤ PL LB ≤ 31 dBm see note 1 and 2 −1.5 − 1.5 dB VDAC set to have 7 ≤ PL LB ≤ 13 dBm see note 1 and 2 −3 − 2 dB VDAC set to have 31 ≤ PL LB ≤ 34 dBm see note 1 and 3 −1.5 − 1.5 dB VDAC set to have 13 ≤ PL LB ≤ 31 dBm; see note 1 and 3 −2 − 2 dB VDAC set to have 7 ≤ PL LB ≤ 13 dBm; see note 1 and 3 −4 − 3 dB output power variation vs frequency VDAC set to have 31 ≤ PL LB ≤ 34 dBm; see note 1 and 4 −0.3 − 0.3 dB harmonics PL LB ≤ 34 dBm − − −5 dBm isolation H2 into DCS1800/PCS1900 measured at RFout HB; PL LB = 34 dBm − − −15 dBm isolation H3 into DCS1800/PCS1900 measured at RFout HB; PL LB = 34 dBm − − −25 dBm isolation PD LB = 2 dBm; VDAC = 0.15 V; standby mode − − −36 dBm PD LB = 2 dBm; VDAC = 0.15 V; LB TX mode − − −36 dBm available output power output power variation at nominal temperature output power variation at extreme temperature H2 to H13 MAX. − reference voltage to set output power ∆PL LB TYP. −2 RF input power η MIN. f = 897.5 MHz for EGSM900; f = 836.5 MHz for GSM850; PL LB = 35 dBm PD LB VDAC PL LB CONDITIONS VSWRin input VSWR PL LB < 5 dBm − − 6:1 VSWRin input VSWR 5 ≤ PL LB ≤ 34 dBm; − 2:1 3:1 2003 Aug 20 10 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 SYMBOL Pn PARAMETER noise power CONDITIONS RBW = 100 kHz; f0 = 897.5 MHz for EGSM900; f0 = 836.5 MHz for GSM850; f0 + 10 MHz; PL LB < 34 dBm; f0 + 20 MHz; PL LB < 34 dBm; f ≥ 1805 MHz; PL LB < 34 dBm; BGY284 MIN. TYP. MAX. UNIT − − − − − − −73 −82 −77 dBm dBm dBm CG conversion gain f0 = 915 MHz for EGSM900; f0 = 849 MHz for GSM850; 5 ≤ PL LB ≤ 34 dBm; fSS1 = f0 − 20 MHz; PSS1 = −40 dBm; CG = PL CON − PSS1; see fig. 4 − − 28 dB SSG small signal gain f0 = 915 MHz for EGSM900; f0 = 849 MHz for GSM850; 5 ≤ PL LB ≤ 34 dBm; fSS2 = f0 + 20 MHz; PSS2 = −40 dBm; SSG = PL SS2 − PSS2; see fig. 5 − − 31 dB AM/AM AM/AM conversion 5 ≤ PL LB ≤ 34 dBm;6.5 % AM modulation with fmod = 67 kHz at RFin LB − 8 12 % 5 ≤ PL LB ≤ 34 dBm;6.5 % AM modulation with fmod = 140 kHz at RFin LB − 12 15 % 5 ≤ PL LB ≤ 34 dBm;6.5 % AM modulation with fmod = 271 kHz at RFin LB − 18 20 % AM/PM conversion −0.5 ≤ PD LB ≤ 0.5 dBm; 5 ≤ PL LB ≤ 34 dBm − − 4 deg/dB maximum control slope 5 ≤ PL LB ≤ 34 dBm − − 250 dB/V tr , tf carrier rise and fall time PL LB 5 dBm to 34 dBm or vice versa − − 2 µs fCL control loop bandwidth − 200 − kHz − −36 dBm AM/PM stability PL LB ≤ 34 dBm; VSWR ≤ 8 : 1 through all − phases; 3.2 ≤ VBAT ≤ 4.6 V ruggedness 3.2 ≤ VBAT ≤ 4.6 V; PL LB ≤ 34 dBm; δ = 4 : 8; VSWR ≤ 8 : 1 through all phases no degradation Note 1. Condition to set VDAC: VBAT = 3.6 V; δ = 2 : 8; PD LB = 0 dBm; Tmb = 25 °C; f = 897.5 MHz for EGSM900; f = 836.5 MHz for GSM850 2. Conditions for power variation: −2 ≤ PD LB ≤ +2 dBm; f = 824 to 849 MHz for GSM850; f = 880 to 915 MHz for EGSM900; 15 ≤ Tmb ≤ 70 °C; 3.2 ≤ VBAT ≤ 4.2 V; VSTAB = 2.8 V ± 10 mV 3. Conditions for power variation: −2 ≤ PD LB ≤ +2 dBm; f = 824 to 849 MHz for GSM850; f = 880 to 915 MHz for EGSM900; −10 ≤ Tmb ≤ 90 °C; 3.2 ≤ VBAT ≤ 4.2 V; VSTAB = 2.8 V ± 10 mV 4. Conditions for power variation: PD LB = 0 dBm; f = 824 to 849 MHz for GSM850; f = 880 to 915 MHz for EGSM900; Tmb = 25 °C; VBAT = 3.6 V; VSTAB = 2.8 V ± 10 mV 2003 Aug 20 11 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 ELECTRICAL CHARACTERISTICS DCS1800/PCS1900 TRANSMIT MODE ZS = ZL = 50 Ω; VBAT = 3.6 V; VSTAB = 2.8 V; Tmb = 25 °C; 1 : 8 ≤ δ ≤ 4 : 8; 575 ≤ tp ≤ 2300 µs; PD HB = 0 dBm; spurious on PD HB < −50 dBm; HB TX mode selected; f = 1710 to 1785 MHz for DCS1800; f = 1850 to 1910 MHz for PCS1900; unless otherwise specified. SYMBOL PARAMETER PD HB RF input power VDAC reference voltage to set output power PL HB η ∆PL HB MIN. TYP. MAX. UNIT −2 0 +2 dBm f = 1747.6 MHz for DCS1800; f = 1880 MHz for PCS1900; PL HB = 32.5 dBm − − 2 V f = 1747.6 MHz for DCS1800; f = 1880 MHz for PCS1900; PL HB = 0 dBm 0.2 − − V VDAC = 2.2 V 32.7 33.5 − dBm VDAC = 2.2 V; VBAT = 3.2 V; PD HB = −3 dBm; Tmb = 85 °C 31.8 − − dBm efficiency DCS1800 saturated power − 50 − % PL HB = 31.3 dBm − 45 − % efficiency PCS1900 saturated power − 50 − % PL HB = 31.3 dBm − 45 − % VDAC set to have 30 ≤ PL HB ≤ 32 dBm; see note 1 and 2 −1 − 1 dB VDAC set to have 15 ≤ PL HB ≤ 30 dBm; see note 1 and 2 −1.5 − 1.5 dB VDAC set to have 5 ≤ PL HB ≤ 15 dBm; see note 1 and 2 −2 − 2 dB VDAC set to have 2 ≤ PL HB ≤ 5 dBm; see note 1 and 2 −3 − 3 dB VDAC set to have 30 ≤ PL HB ≤ 32 dBm; see note 1 and 3 −1.5 − 1.5 dB VDAC set to have 15 ≤ PL HB ≤ 30 dBm; see note 1 and 3 −2 − 2 dB VDAC set to have 5 ≤ PL HB ≤ 15 dBm; see note 1 and 3 −2.5 − 2.5 dB VDAC set to have 2 ≤ PL HB ≤ 5 dBm; see note 1 and 3 −3.5 − 3.5 dB output power variation vs frequency VDAC set to have 30 ≤ PL HB ≤ 32 dBm; see note 1 and 4 −0.3 − 0.3 dB harmonics PL HB ≤ 32 dBm − − −4.5 dBm isolation PD HB = 2 dBm; VDAC = 0.15 V; standby mode − − −36 dBm PD HB = 2 dBm; VDAC = 0.15 V; HB TX mode − − −36 dBm available output power output power variation at nominal temperature output power variation at extreme temperature H2 to H7 CONDITIONS VSWRin input VSWR PL HB < 2 dBm − − 6:1 VSWRin input VSWR 2 ≤ PL LB ≤ 32 dBm − 2:1 3:1 2003 Aug 20 12 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 SYMBOL Pn PARAMETER noise power CONDITIONS RBW = 100 kHz f0 = 1747.5 MHz for DCS1800; f0 = 1880 MHz for PCS1900; f0 + 20 MHz; PL HB < 32 dBm BGY284 MIN. TYP. MAX. UNIT − − −77 dBm CG conversion gain f0 = 1785 MHz for DCS1800; f0 = 1910 MHz for PCS1900; 0 ≤ PL HB ≤ 32 dBm; fSS1 = f0 − 20 MHz; PSS1 = −40 dBm; CG = PL CON − PSS1; see fig. 4 − − 25.5 dB SSG small signal gain f0 = 1785 MHz for DCS1800; f0 = 1910 MHz for PCS1900; 0 ≤ PL HB ≤ 32 dBm; fSS2 = f0 + 20 MHz; PSS2 = −40 dBm; SSG = PL SS2 − PSS2; see fig. 5 − − 31 dB AM/AM AM/AM conversion 0 ≤ PL HB ≤ 32 dBm;6.5 % AM modulation − with fmod = 67 kHz at RFin HB 8 12 % 0 ≤ PL HB ≤ 32 dBm;6.5 % AM modulation − with fmod = 140 kHz at RFin HB 12 15 % 0 ≤ PL HB ≤ 32 dBm;6.5 % AM modulation − with fmod = 271 kHz at RFin HB 18 20 % AM/PM conversion −0.5 ≤ PD HB ≤ 0.5 dBm; 0 ≤ PL HB ≤ 32 dBm − − 4 deg/dB maximum control slope 0 ≤ PL HB ≤ 32 dBm − − 250 dB/V tr , tf carrier rise and fall time PL HB from 0 dBm to 32 dBm and vice versa − − 2 µs fCL control loop bandwidth − 200 − kHz − −36 dBm AM/PM stability PL HB ≤ 32 dBm; VSWR ≤ 8 : 1 through all − phases; 3.2 ≤ VBAT ≤ 4.6 V ruggedness 3.2 ≤ VBAT ≤ 4.6 V; PL HB ≤ 32 dBm; δ = 4 : 8; VSWR ≤ 8 : 1 through all phases no degradation Note 1. Condition to set VDAC: VBAT = 3.6 V; δ = 2 : 8; PD HB = 0 dBm; Tmb = 25 °C; f = 1747.6 MHz for DCS1800; f = 1880 MHz for PCS1900 2. Conditions for power variation: −2 ≤ PD HB ≤ +2 dBm; f = 1710 to 1785 MHz for DCS1800; f = 1850 to 1910 MHz for PCS1900; 15 ≤ Tmb ≤ 70 °C; 3.2 ≤ VBAT ≤ 4.2 V; VSTAB = 2.8 V ± 10 mV 3. Conditions for power variation: −2 ≤ PD HB ≤ +2 dBm; f = 1710 to 1785 MHz for DCS1800; f = 1850 to 1910 MHz for PCS1900; −10 ≤ Tmb ≤ 90 °C; 3.2 ≤ VBAT ≤ 4.2 V; VSTAB = 2.8 V ± 10 mV 4. Conditions for power variation: PD HB = 0 dBm; f = 1710 to 1785 MHz for DCS1800; f = 1850 to 1910 MHz for PCS1900; Tmb = 25 °C; VBAT = 3.6 V; VSTAB = 2.8 V ± 10 mV 2003 Aug 20 13 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 PL PD P PL SS1 P PL CON PSS1 PA fSS1 f0 fSS1 f f0 2f0-fSS1 f CG = PLCON - PSS1 Fig.4 Input and output signals for conversion gain PL PD P PSS2 f0 fSS2 PA f f0 SSG = PLSS2 - PSS2 Fig.5 Input and output signals for small signal gain Note 1: total noise at the output of the PA is the summation of three sources: 1) the noise present at the input of the PA at fSS1 amplified by the conversion gain 2) the noise present at the input of the PA at fSS2 amplified by the small signal gain 3) the noise generated by the PA itself, when the noise at the input of the PA is 0 2003 Aug 20 PL SS2 P 14 fSS2 f Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 APPLICATION INFORMATION VBAT C10 C2 C3 C4 C5 Z0 RFin,HB R1 VTXon 5 4 VTXon RFin,HB 3 2 VBAT VBAT 1 GND Z0 R2 VDAC 6 VDAC 7 VSTAB 8 vband RFout,HB 16 GND 15 RFout,LB 14 RFout,HB C1 R3 VSTAB PAM1 Z0 R4 vband N.C. 9 RFin,LB 10 VBAT VBAT GND 11 12 13 Z0 RFin,LB VBAT 2003 Aug 20 15 C7 C8 C9 C11 Note: pin 9 must not have any driving signals attached to it Fig.6 Test circuit. C6 RFout,LB Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 List of components QUANTITY LOCATION 1 VALUE / TYPE DESCRIPTION PB005H1 PCB BGY284 Power amplifier module 1 PAM1 4 CON1, CON2, CON3, CON4 Jack assembly end launch SMA connector 1 CON5 DC conector 5 pin 1 CON6 solder ring 1 C1 2.7 nF 0603 size SMD capacitor 4 C2, C3, C8, C9 100 nF 0805 size SMD capacitor 2 C4, C5 10 pF 0603 size SMD capacitor 2 C6, C7 33 pF 0603 size SMD capacitor 2 C10, C11 47 µF / 35 V Electrol. capacitor 4 R1, R3, R4, R5 0Ω 0603 size SMD resistor 1 R2 1k Ohms / 0.1 W 0603 size SMD resistor 4 Z0 50 Ω stripline; note 1 REMARK Roland Haefele Type no. 142-0701-881 Johnson Components note 2 Matsushita width 1.4 mm Note 1. The striplines are on a double etched printed circuit board (εr = 4.6); thickness 0.8 mm 2. C10 and C11 have beed added to smoothen VBAT 2003 Aug 20 16 SUPPLIER Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 3&%'HVLJQ3%+ & & &RQ & & &RQ & 5 5 &RQ & 5 5 5 &RQ & & & & &RQ & &RQ Fig.7 PCB testcircuit. 2003 Aug 20 17 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 SOLDERING RECOMMENDATIONS Reflow profile: The BGY284 is a laminate based PA module in a LGA package. The module can be assembled using a standard SMT reflow process in a convection or IR-oven. In the graph below (see Fig.8) the minimum and maximum limits of the temperature profile are given. The actual profile has to be within these limits, and will depend on the PCB material, the number and size of the components to be assembled, and the type of solder which is being used. Temperature TP TR TE max T E min E tR tE α α β Time Fig.8 Recommended reflow temperature profile. It is recommended to use a standard no-clean solder paste like SnPb (in case of a profile for a lead containing solder) or SnAgCu (in case of a lead free assembly process). In the table the corresponding values are given for SnPb and for SnAgCu solder. PARAMETER SnPb SOLDER SnAgCu SOLDER Temperature gradient (α) (°C/s) ≤3 ≤3 Preheat (soak) temperature (TE) (°C) 100 -150 150 - 200 Preheat time (tE) (s) 60 - 120 60 -180 Reflow temperature (TR) (°C) >183 >217 Reflow time (tR) (s) 60 - 150 60 - 150 Maximum peak temperature (TP) (°C) 240 260 Temperature gradient (β) (°C/s) <5 <5 Time 25 °C to peak temperature 6 minutes max. 8 minutes max. 2003 Aug 20 18 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 PCB layout: The PCB footprint layout is a copy of the metal pattern on the backside of the LGA package. It is recommended to design a big ground plane on the PCB, and to make the solder lands of the ground plane solder mask defined. A drawing of the footprint is included in the “Footprint layout SOT775A” drawing. Stencil design: The dimensions of the solder stencil are also given in the “Footprint layout SOT775A” drawing. The recommendation is based on a stencil thickness of 125 µm. If a thinner or thicker stencil is being used, the dimensions of the stencil apertures have to be adjusted. Moisture sensitivity level: The BGY284 is tested according to the JEDEC standard JESD 22-A113C. The BGY284 is classified on MSL3 for a lead containing soldering profile with a peak temperature of 240 °C, and on MSL4 for a lead free soldering profile with a peak temperature of 260 °C. Rework: If rework is needed it is recommended to use a BGA rework station with a programmable top and bottom heater. The first step of the rework process is preheating the PCB with the bottom heater of the rework station. When the board has reached the preheat temperature then the top heater can be used to increase the temperature above the melting point of the solder. The component which has to be replaced can be picked up with a vacuum nozzle. Before placing a new component the remaining solder on the board has to be removed. Fresh solder can be dispensed, a new component can be placed, and the board can be heated in a similair way as described before. 2003 Aug 20 19 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 Fig.9 Footprint layout and solder stencil design. 2003 Aug 20 20 BGY284 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 PACKAGE OUTLINE 1 2 3 4 16 6 15 7 14 8 13 12 11 10 2003 Aug 20 5 9 21 BGY284 Philips Semiconductors Preliminary specification power amplifier with integrated control loop for GSM850, EGSM900, DCS1800 & PCS1900 BGY284 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Aug 20 22 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. © Koninklijke Philips Electronics N.V. 2003 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands budgetnum/printrun/ed/pp23 Date of release: 2003 Aug 20 Document order number: 9397 750 11968