ITF86116SQT TM Data Sheet 10A, 30V, 0.012 Ohm, N-Channel, Logic Level, Power MOSFET Packaging TSSOP8 File Number 4808.3 Features • Ultra Low On-Resistance - rDS(ON) = 0.012Ω, VGS = 10V - rDS(ON) = 0.016Ω, VGS = 4.5V • Gate to Source Protection Diode • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com 5 1 23 July 2000 4 • Peak Current vs Pulse Width Curve • Transient Thermal Impedance Curve vs Board Mounting Area Symbol • Switching Time vs RGS Curves DRAIN(1) DRAIN(8) SOURCE(2) Ordering Information PART NUMBER SOURCE(7) ITF86116SQT SOURCE(3) SOURCE(6) PACKAGE TSSOP-8 BRAND 86116 NOTE: When ordering, use the entire part number. ITF86116SQT2 is available only in tape and reel. DRAIN(5) GATE(4) Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA = 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Technical Brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: ITF86116SQT 30 30 ±20 UNITS V V V 10.0 9.0 5.0 Figure 4 2 16 -55 to 150 A A A A W mW/oC oC 300 260 oC oC 1. TJ = 25oC to 125oC. 2. 62.5oC/W measured using FR-4 board with 1.00 in2 (645.2 mm2) copper pad at 10 second. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. SABER™ is a trademark of Analogy, Inc. PSPICE® is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 ITF86116SQT TA = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 30 - - V OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) Zero Gate Voltage Drain Current IDSS VDS = 30V, VGS = 0V - - 10 µA Gate to Source Leakage Current IGSS VGS = ±20V - - ±10 µA 1.0 - 2.5 V ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) Drain to Source On Resistance rDS(ON) ID = 10.0A, VGS = 10V (Figures 8, 9) - 0.0086 0.012 Ω ID = 5.0A, VGS = 4.5V (Figure 8) - 0.011 0.016 Ω Pad Area = 1.00 in2 (645.2 mm2) (Note 2) - - 62.5 oC/W Pad Area = 0.035 in2 (22.4 mm2) (Figure 20) - - 165.4 oC/W Pad Area = 0.0045 in2 (2.88 mm2) (Figure 20) - - 206.8 oC/W VDD = 15V, ID = 5.0A VGS = 4.5V, RGS = 8.2Ω (Figures 14, 18, 19) - 21.5 - ns - 82 - ns - 29 - ns - 31 - ns - 12 - ns - 63 - ns - 47 - ns - 46 - ns - 34 - nC - 18.6 - nC - 2 - nC THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RθJA SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time VDD = 15V, ID = 10.0A VGS = 10V, RGS = 9.1Ω (Figures 15, 18, 19) tf GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge VDD = 15V, ID = 9.0A, Ig(REF) = 1.0mA (Figures 13, 16, 17) Gate to Source Gate Charge Qgs - 6.4 - nC Gate to Drain “Miller” Charge Qgd - 7.2 - nC - 1770 - pF - 390 - pF - 163 - pF MIN TYP MAX UNITS ISD = 9.0A - 0.81 - V trr ISD = 9.0A, dISD/dt = 100A/µs - 27 - ns QRR ISD = 9.0A, dISD/dt = 100A/µs - 13.5 - nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Reverse Recovery Time Reverse Recovered Charge 2 TEST CONDITIONS ITF86116SQT 1.2 12 1.0 10 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 8 6 4 VGS = 4.5V, RθJA = 206.8oC/W 2 0.2 0 VGS = 10V, RθJA = 62.5oC/W 0 0 25 50 75 100 125 25 150 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 3 ZθJA, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 RθJA = 62.5oC/W 0.1 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 1000 RθJA = 62.5oC/W TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 I = I25 150 - TA 125 VGS = 4.5V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 5 10-5 10-4 10-3 10-2 10-1 100 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 3 101 102 103 ITF86116SQT Typical Performance Curves (Continued) 40 RθJA = 62.5oC/W SINGLE PULSE TJ = MAX RATED TA = 25oC 100 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 500 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 30 TJ = 150oC 20 TJ = 25oC 10 TJ = -55oC 10ms 1 1 10 0 2.0 100 2.5 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 25 VGS = 4V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) ID, DRAIN CURRENT (A) VGS = 10V VGS = 5V 30 VGS = 4.5V 20 VGS = 3.5V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 TA = 25oC 3.5 4.0 FIGURE 6. TRANSFER CHARACTERISTICS 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 20 ID = 1A 15 ID = 10A 10 VGS = 3V 5 0 0 0.2 0.4 0.8 0.6 2 1.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.6 1.2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = VDS, ID = 250µA VGS = 10V, ID = 10A 1.4 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3.0 VGS, GATE TO SOURCE VOLTAGE (V) 1.2 1.0 1.0 0.8 0.6 0.8 0.6 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 160 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE ITF86116SQT Typical Performance Curves (Continued) 1.10 3000 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.05 1.00 0.95 CISS = CGS + CGD COSS ≅ CDS + CGD 1000 CRSS = CGD 0.90 -80 VGS = 0V, f = 1MHz -40 0 40 80 120 100 0.1 160 1.0 TJ , JUNCTION TEMPERATURE (oC) 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 250 VDD = 15V VGS = 4.5V, VDD = 15V, ID = 5.0A 8 200 SWITCHING TIME (ns) VGS , GATE TO SOURCE VOLTAGE (V) 10 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 9A ID = 1A 2 tr 150 100 tf 50 td(OFF) td(ON) 0 0 20 10 30 0 40 0 Qg, GATE CHARGE (nC) 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE (Ω) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. SWITCHING TIME vs GATE RESISTANCE FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 250 SWITCHING TIME (ns) VGS = 10V, VDD = 15V, ID = 10A 200 td(OFF) 150 tf 100 tr 50 td(ON) 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE 5 50 50 ITF86116SQT Test Circuits and Waveforms VDS RL VDD Qg(TOT) VDS VGS = 10V VGS + - Qg(5) VDD VGS = 5V VGS DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS tON RL td(ON) td(OFF) VDS VGS tOFF + VGS tf tr VDS 90% 90% 0V 10% 10% 0 DUT RGS 90% VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM – T A ) P DM = ------------------------------Z θJA (EQ. 1) In using surface mount devices such as the TSSOP-8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 6 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer’s preliminary application evaluation. Figure 20 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state ITF86116SQT Displayed on the curve are RθJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RθJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R θJA = 97.5 – 20.2 • ln ( Area ) (EQ. 2) Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 240 RθJA = 97.5 - 20.2 * 220 ln (AREA) 206.8oC/W - 0.0045in2 200 RθJA (oC/W) junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. 180 165.4oC/W - 0.035in2 160 140 120 The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. 100 80 0.001 0.1 0.01 AREA, TOP COPPER AREA (in2) 1.0 FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA 150 ZθJA, THERMAL IMPEDANCE (oC/W) COPPER BOARD AREA - DESCENDING ORDER 100 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 50 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA 7 102 103 ITF86116SQT PSPICE Electrical Model .SUBCKT ITF86116SQT 2 1 3 ; REV 29 Dec 1999 CA 12 8 1.55e-9 CB 15 14 1.65e-9 CIN 6 8 1.65e-9 LDRAIN DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7DESD2MOD DPLCAP 10 5 DPLCAPMOD DPLCAP 5 DRAIN 2 10 RLDRAIN DBREAK RSLC1 51 RSLC2 + 5 51 EBREAK 11 7 17 18 38.78 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 - RDRAIN 16 6 8 ESG EVTHRES + 19 8 + GATE 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 EVTEMP 9 RGATE + 18 22 20 EBREAK 6 + 17 18 DBODY - 21 MWEAK MMED MSTRO RLGATE DESD1 91 DESD2 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD LSOURCE CIN SOURCE 3 7 8 RSOURCE RLSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.40e-3 RGATE 9 20 1.37 RLDRAIN 2 5 10 RLGATE 1 9 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.50e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 11 50 - LGATE IT 8 17 1 ESLC S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),2))} .MODEL DBODYMOD D (IS = 2.15e-12 RS = 4.73e-3 TRS1 = 1.51e-3 TRS2 = 1.06e-6 CJO = 1.16e-9 TT = 2.19e-8 M = 0.50) .MODEL DBREAKMOD D (RS = 8.99e-2 TRS1 = -1.74e-3 TRS2 = 2.86e-5) .MODEL DESD1MOD D (BV = 9.7 Tbv1= -2.72e-3 N= 16 RS = 25) .MODEL DESD2MOD D (BV = 15.6 Tbv1= -2.17e-3 N= 13 RS = 25) .MODEL DPLCAPMOD D (CJO = 8.50e-10 IS = 1e-30 M = 0.50) .MODEL MMEDMOD NMOS (VTO = 2.30 KP = 3.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.37) .MODEL MSTROMOD NMOS (VTO = 2.89 KP =125 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.05 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 7.98e-4 TC2 = -9.15e-7) .MODEL RDRAINMOD RES (TC1 = 8.78e-3 TC2 = 8.98e-6) .MODEL RSLCMOD RES (TC1 = 9.15e-4 TC2 = 1.22e-6) .MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -3.55e-3 TC2 = -6.24e-6) .MODEL RVTEMPMOD RES (TC1 = -1.66e-3 TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -2.8) VON = -2.8 VOFF= -4.0) VON = -2.5 VOFF= 0) VON = 0 VOFF= -2.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 8 ITF86116SQT SABER Electrical Model REV 29 Dec 1999 template itf86116sqt n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 2.15e-12,rs=4.73e-3,trs1=1.51e-3,trs2=1.06e-6, cjo = 1.16e-9, tt = 2.19e-8, m = 0.50) dp..model dbreakmod = (rs=8.99e-2,trs1=-1.74e-3,trs2=2.86e-5) dp..model desd1mod = (bv=9.7,tbv1=-2.72e-3,n1=16, rs=25) dp..model desd2mod = (bv=15.6,tbv1=-2.17e-3,n1=13, rs=25) dp..model dplcapmod = (cjo = 8.50e-10, is = 1e-30, m = 0.50) m..model mmedmod = (type=_n, vto = 2.30, kp = 3.50, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.89, kp = 125, is = 1e-30, tox = 1) DPLCAP 5 m..model mweakmod = (type=_n, vto = 2.05, kp = 0.10, is = 1e-30, tox = 1) 10 sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -2.8) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.8, voff = -4.0) RSLC1 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.5, voff = 0) 51 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -2.5) RSLC2 LDRAIN DRAIN 2 RLDRAIN ISCL c.ca n12 n8 = 1.55e-9 c.cb n15 n14 = 1.65e-9 c.cin n6 n8 = 1.65e-9 dp.dbody n7 n71 = model=dbodymod dp.dbreak n72 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod dp.dplcap n10 n5 = model=dplcapmod RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10 DBREAK 50 - EVTEMP RGATE + 18 22 9 20 RLGATE DESD1 91 DESD2 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 MMED MSTRO CIN - 8 LSOURCE 7 RSOURCE RLSOURCE S1A m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 12 S2A 13 8 S1B res.rbreak n17 n18 = 1, tc1 = 7.98e-4, tc2 = -9.15e-7 res.rdrain n50 n16 = 2.40e-3, tc1 = 8.78e-3, tc2 = 8.98e-6 res.rgate n9 n20 = 1.37 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 9.15e-4, tc2 = 1.22e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.50e-3, tc1 = 1.00e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.66e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -3.55e-3, tc2 = -6.24e-6 CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 2)) } } - IT 14 + + spe.ebreak n11 n7 n17 n18 = 38.78 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 9 RBREAK 15 14 13 VBAT 5 8 EDS - + 8 22 RVTHRES SOURCE 3 ITF86116SQT SPICE Thermal Model REV 27 Dec 1999 ITF86116SQT Copper Area = 0.04 in2 CTHERM1 th 8 1.50e-3 CTHERM2 8 7 5.00e-3 CTHERM3 7 6 1.00e-2 CTHERM4 6 5 2.00e-2 CTHERM5 5 4 5.00e-2 CTHERM6 4 3 1.20e-1 CTHERM7 3 2 2.50e-1 CTHERM8 2 tl 1.30 JUNCTION th CTHERM1 RTHERM1 8 CTHERM2 RTHERM2 RTHERM1 th 8 0.15 RTHERM2 8 7 0.50 RTHERM3 7 6 1.25 RTHERM4 6 5 8.00 RTHERM5 5 4 12.00 RTHERM6 4 3 26.00 RTHERM7 3 2 39.00 RTHERM8 2 tl 49.5 7 CTHERM3 RTHERM3 6 RTHERM4 CTHERM4 SABER Thermal Model 5 Copper Area = 0.04 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 1.50e-3 ctherm.ctherm2 8 7 = 5.00e-3 ctherm.ctherm3 7 6 = 1.00e-2 ctherm.ctherm4 6 5 = 2.00e-2 ctherm.ctherm5 5 4 = 5.00e-2 ctherm.ctherm6 4 3 = 1.20e-1 ctherm.ctherm7 3 2 = 2.50e-1 ctherm.ctherm8 2 tl = 1.30 CTHERM5 RTHERM5 4 RTHERM6 CTHERM6 3 CTHERM7 RTHERM7 rtherm.rtherm1 th 8 = 0.15 rtherm.rtherm2 8 7 = 0.50 rtherm.rtherm3 7 6 = 1.25 rtherm.rtherm4 6 5 = 8.00 rtherm.rtherm5 5 4 = 12.00 rtherm.rtherm6 4 3 = 26.00 rtherm.rtherm7 3 2 = 39.00 rtherm.rtherm8 2 tl = 49.50 } 2 CTHERM8 RTHERM8 tl CASE TABLE 1. THERMAL MODELS 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.0 in2 CTHERM6 1.20e-1 2.00e-1 2.80e-1 1.90e-1 2.00e-1 CTHERM7 2.50e-1 4.80e-1 4.50e-1 3.90e-1 5.00e-1 CTHERM8 1.30 2.30 2.20 2.70 3.00 RTHERM6 26 20 15 11 12 RTHERM7 39 24 21 21 18 RTHERM8 49.5 36.8 39 29.5 25 COMPONENT 10 ITF86116SQT MO-153AA (TSSOP-8) 8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE E INCHES A E1 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.041 0.047 1.05 1.20 - A1 0.002 0.006 0.05 0.15 - b 0.010 0.012 0.25 0.30 - 8 A1 e D c 0.127 - 4 5 0.005 b c D 0.114 0.122 2.90 3.10 2 E 0.244 0.260 6.20 6.60 - E1 0.170 0.177 4.30 4.50 3 e 0.004 IN 0.10mm L 0o-8o 0.015 0.4 0.035 0.9 0.025 0.65 0.232 5.9 0.077 1.95 L 0.025 BSC 0.020 0.028 0.65 BSC 0.50 0.70 4 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC MO-153AA outline dated 10-97. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension “E1” does not include inter-lead flash or protrusions. Interlead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. “L” is the length of terminal for soldering. 5. Controlling dimension: Millimeter 6. Revision 3 dated: 5-00. MO-153AA (TSSOP-8) 12mm TAPE AND REEL 17.4mm 1.5mm DIA. HOLE 4.0mm 2.0mm 13mm 1.75mm CL 12mm 330mm 100mm 8.0mm 13.4mm USER DIRECTION OF FEED COVER TAPE GENERAL INFORMATION 1. 3000 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 11 ITF86116SQT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 12 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369