HUF76407DK8
Data Sheet
October 1999
File Number
4712.4
3.5A, 60V, 0.105 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
Packaging
Features
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
• Ultra Low On-Resistance
- rDS(ON) = 0.090Ω, VGS = 10V
- rDS(ON) = 0.105Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.semi.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Transient Thermal Impedance Curve vs Board Mounting
Area
SOURCE1 (1)
DRAIN 1 (8)
GATE1 (2)
DRAIN 1 (7)
SOURCE2 (3)
DRAIN 2 (6)
GATE2 (4)
DRAIN 2 (5)
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
HUF76407DK8
PACKAGE
MS-012AA
BRAND
76407DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76407DK8T.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.5V) (Figure 2) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
HUF76407DK8
60
60
±16
UNITS
V
V
V
3.5
3.8
1.0
1.0
Figure 4
Figures 6, 17, 18
2.5
20
-55 to 150
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF76407DK8
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
60
-
-
V
ID = 250µA, VGS = 0V , TA = -40oC (Figure 12)
55
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
VDS = 55V, VGS = 0V
-
-
1
µA
VDS = 50V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 3.8A, VGS = 10V (Figures 9, 10)
-
0.075
0.090
Ω
ID = 1.0A, VGS = 5V (Figure 9)
-
0.088
0.105
Ω
ID = 1.0A, VGS = 4.5V (Figure 9)
-
0.092
0.110
Ω
Pad Area = 0.76 in2 (490.3 mm2) (Note 2)
-
-
50
oC/W
Pad Area = 0.027 in2 (17.4 mm2) (Figure 23)
-
-
191
oC/W
Pad Area = 0.006 in2 (3.87 mm2) (Figure 23)
-
-
228
oC/W
VDD = 30V, ID = 1.0A
VGS = 4.5V, RGS = 27Ω
(Figures 15, 21, 22)
-
-
57
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
-
8
-
ns
tr
-
30
-
ns
td(OFF)
-
25
-
ns
tf
-
25
-
ns
tOFF
-
-
75
ns
-
-
24
ns
-
5
-
ns
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 3.8A
VGS = 10V,
RGS = 30Ω
(Figures 16, 21, 22)
-
11
-
ns
td(OFF)
-
46
-
ns
tf
-
31
-
ns
tOFF
-
-
116
ns
-
9.4
11.2
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
VDD = 30V,
ID = 1.0A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
5.3
6.4
nC
-
0.42
0.5
nC
Gate to Source Gate Charge
Qgs
-
1.05
-
nC
Reverse Transfer Capacitance
Qgd
-
2.4
-
nC
-
330
-
pF
-
100
-
pF
-
18
-
pF
MIN
TYP
MAX
UNITS
ISD = 3.8A
-
-
1.25
V
ISD = 1.0A
-
-
1.00
V
trr
ISD = 1.0A, dISD/dt = 100A/µs
-
-
48
ns
QRR
ISD = 1.0A, dISD/dt = 100A/µs
-
-
89
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
HUF76407DK8
Typical Performance Curves
4
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 10V, RθJA = 50oC/W
3
2
1
VGS = 4.5V, RθJA = 228oC/W
0.2
0
0
0
25
50
75
100
125
25
150
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 228oC/W
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
RθJA = 228oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
100
I = I25
VGS = 5V
150 - TA
125
10
1
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
HUF76407DK8
Typical Performance Curves
50
500
100
IAS, AVALANCHE CURRENT (A)
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
RθJA = 228oC/W
ID, DRAIN CURRENT (A)
(Continued)
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1ms
10ms
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
STARTING TJ = 150oC
1
0.1
1
10
100
0.01
200
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
15
VGS = 10V
VGS = 4.5V
VGS = 5V
TJ = 25oC
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
20
TJ = -55oC
TJ = 150oC
10
5
15
VGS = 4V
10
VGS = 3.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
5
TA = 25oC
2.0
2.5
3.0
3.5
4.5
4.0
VGS, GATE TO SOURCE VOLTAGE (V)
0
5.0
FIGURE 7. TRANSFER CHARACTERISTICS
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
4
FIGURE 8. SATURATION CHARACTERISTICS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 3.8A
120
ID = 1A
90
2.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
150
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 3V
0
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 3.8A
1.5
1.0
0.5
60
2
3
4
6
8
5
7
VGS, GATE TO SOURCE VOLTAGE (V)
9
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
160
HUF76407DK8
Typical Performance Curves
(Continued)
1.2
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
1.1
1.0
0.6
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
10
1000
C, CAPACITANCE (pF)
CISS = CGS + CGD
100
COSS ≅ CDS + CGD
CRSS = CGD
10
VDD = 30V
8
6
4
0
VGS = 0V, f = 1MHz
0
5
0.1
1.0
10
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
2
4
6
Qg, GATE CHARGE (nC)
8
10
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
50
80
VGS = 4.5V, VDD = 30V, ID = 1.0A
VGS = 10V, VDD = 30V, ID = 3.8A
tr
40
SWITCHING TIME (ns)
SWITCHING TIME (ns)
WAVEFORMS IN
DESCENDING ORDER:
ID = 3.8A
ID = 1.0A
2
tf
30
td(OFF)
20
td(ON)
td(OFF)
60
tf
40
20
tr
10
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
50
HUF76407DK8
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76407DK8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
RθJA = 103.2 - 24.3
250
Rθβ, RθJA (oC/W)
( T JM – T A )
P DM = ------------------------------R θJA
300
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
150
100
(EQ. 1)
50
Rθβ = 46.4 - 21.7 * ln(AREA)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
0
0.001
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
ln ( Area )
7
(EQ. 2)
0.1
1
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFET™s are offered with
two die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
Rθβ
4. The use of thermal vias.
0.01
AREA, TOP COPPER AREA (in2) PER DIE
3. The use of external heat sinks.
R θJA = 103.2 – 24.3 ×
* ln(AREA)
= 46.4 – 21.7 ×
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (RθJA) and thermal coupling resistance
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 159˚C/W
Rθβ1 = Rθβ2 = 97˚C/W
TJ1 and TJ2 define the junction temerature of the respective
die. Similarly, P1 and P2 define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70˚C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate TJ1 and and Equation 5 to
calulate TJ2.
.
T J1 = P 1 R θJA + P 2 R θβ + T A
(EQ. 4)
TJ1 = (0 Watts)(159˚C/W) + (0.5 Watts)(97˚C/W) + 70˚C
TJ1 = 119˚C
T J2 = P 2 R θJA + P 1 R θβ + T A
(EQ. 5)
TJ2 = (0.5 Watts)(159˚C/W) + (0 Watts)(97˚C/W) + 70˚C
TJ2 = 150˚C
HUF76407DK8
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
ZθJA, THERMAL
IMPEDANCE (oC/W)
160
120
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
80
40
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
8
102
103
HUF76407DK8
PSPICE Electrical Model
.SUBCKT HUF76407DK8 2 1 3 ;
REV 28 May 1999
CA 12 8 4.55e-10
CB 15 14 5.20e-10
CIN 6 8 3.11e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
ESG
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.00e-2
RGATE 9 20 3.37
RLDRAIN 2 5 10
RLGATE 1 9 15
RLSOURCE 3 7 4.86
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.80e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.5e-9
LSOURCE 3 7 4.86e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 67.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
14
13
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*105),2))}
.MODEL DBODYMOD D (IS = 3.17e-13 RS = 2.21e-2 TRS1 = 6.25e-4 TRS2 = -1.11e-6 CJO = 6.82e-10 TT = 7.98e-8 M = 0.65)
.MODEL DBREAKMOD D (RS = 3.36e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6)
.MODEL DPLCAPMOD D (CJO = 2.91e-10 IS = 1e-30 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37)
.MODEL MSTROMOD NMOS (VTO = 2.33 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.71 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5)
.MODEL RSLCMOD RES (TC1 = 1.0e-3 TC2 = 1.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.11e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.0 VOFF= -2.5)
VON = -2.5 VOFF= -7.0)
VON = -1.0 VOFF= 0)
VON = 0 VOFF= -1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
HUF76407DK8
SABER Electrical Model
REV 28May 1999
template huf76407dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.17e-13, cjo = 6.82e-10, tt = 7.98e-8, m = 0.65)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.91e-10, is = 1e-30, m = 0.85)
m..model mmedmod = (type=_n, vto = 2.00, kp = 1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.33, kp = 19, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.71, kp = 0.02, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7, voff = -2.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -7)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
c.ca n12 n8 = 4.55e-10
c.cb n15 n14 = 5.20e-10
c.cin n6 n8 = 3.11e-10
72
ISCL
EVTHRES
+ 19 8
+
LGATE
i.it n8 n17 = 1
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.5e-9
l.lsource n3 n7 = 4.86e-10
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
21
DBODY
EBREAK
+
17
18
MSTRO
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/105))** 2))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 67.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
10
MWEAK
MMED
CIN
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0
res.rdbody n71 n5 = 2.21e-2, tc1 = -6.25e-4, tc2 = -1.11e-6
res.rdbreak n72 n5 = 3.36e-1, tc1 = 1.25e-4, tc2 = 1.34e-6
res.rdrain n50 n16 = 3.00e-2, tc1 = 1.23e-2, tc2 = 2.58e-5
res.rgate n9 n20 = 3.37
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 15
res.rlsource n3 n7 = 4.86
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.80e-2, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.11e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76407DK8
SPICE Thermal Model
REV 1June 1999
HUF76407DK8
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
CTHERM4
5
Copper Area = 0.02 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
2
CTHERM8
RTHERM8
tl
AMBIENT
TABLE 1. Thermal Models
0.02 in2
0.14 in2
0.257 in2
0.38 in2
0.493 in2
CTHERM6
9.0e-2
1.3e-1
1.5e-1
1.5e-1
1.5e-1
CTHERM7
4.0e-1
6.0e-1
4.5e-1
6.5e-1
7.5e-1
CTHERM8
1.4
2.5
2.2
3
3
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
COMPONANT
11
HUF76407DK8
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12
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