FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET 40 V, 80 A, 2.1 mΩ Features General Description Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. Max rDS(on) = 2.1 mΩ at VGS = 10 V, ID = 27 A Max rDS(on) = 3.1 mΩ at VGS = 4.5 V, ID = 22 A High performance technology for extremely low rDS(on) Termination is Lead-free Application 100% UIL Tested DC-DC Conversion RoHS Compliant Pin 1 Pin 1 S D D D Top S S S D S D S D G D G D Bottom Power 33 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C Ratings 40 Units V ±20 V 80 (Note 1a) 27 (Note 4) 240 (Note 3) 294 54 (Note 1a) Operating and Storage Junction Temperature Range 2.3 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient (Note 1) 2.3 (Note 1a) 53 °C/W Package Marking and Ordering Information Device Marking FDMC8360L Device FDMC8360L ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. C1 Package Power33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET June 2013 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 3.0 V 40 V 22 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 27 A 1.6 2.1 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 22 A 2.3 3.1 VGS = 10 V, ID = 27 A, TJ = 125 °C 2.2 2.9 VDD = 5 V, ID = 27 A 138 VDS = 20 V, VGS = 0 V, f = 1 MHz 4140 5795 pF 1230 1725 pF gFS Forward Transconductance 1.0 1.6 -6 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance 0.1 36 60 pF 0.9 2.7 Ω ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time 5.3 11 ns Qg(TOT) Total Gate Charge VGS = 0 V to 10 V 57 80 nC Qg(TOT) Total Gate Charge 37 Gate to Source Charge VGS = 0 V to 4.5 V VDD = 20 V, ID = 27 A 26 Qgs Qgd Gate to Drain “Miller” Charge VDD = 20 V, ID = 27 A, VGS = 10 V, RGEN = 6 Ω 15 28 6.7 14 ns 38 60 ns nC 11 nC 5.7 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 27 A (Note 2) 0.8 1.3 VGS = 0 V, IS = 1.9 A (Note 2) 0.7 1.2 V 49 80 ns 29 46 nC IF = 27 A, di/dt = 100 A/μs V Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 53 °C/W when mounted on a 1 in2 pad of 2 oz copper b. 125 °C/W when mounted on a minimum pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 294 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 14 A, VDD = 40 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 44 A. 4. Pulsed Id limited by junction temperature, td<=100 μS, please refer to SOA curve for more details. ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. C1 2 www.fairchildsemi.com FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted VGS = 10 V VGS = 4.5 V 180 VGS = 4 V 120 VGS = 3.5 V 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 0 0.0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 240 VGS = 3 V 4 VGS = 3.5 V 3 VGS = 4 V 2 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 2.0 120 180 240 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 8 ID = 27 A VGS = 10 V rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics IS, REVERSE DRAIN CURRENT (A) VDS = 5 V 120 TJ = 150 oC TJ = 25 oC 60 TJ = -55 oC 2.0 2.5 3.0 3.5 4 TJ = 125 oC 2 TJ = 25 oC 2 240 100 4 6 8 10 VGS = 0 V 10 1 TJ = 150 oC TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. C1 6 Figure 4. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS, GATE TO SOURCE VOLTAGE (V) 240 180 ID = 27 A 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On- Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 0 VGS = 10 V VGS = 4.5 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 10000 ID = 27 A VDD = 15 V Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 20 V 6 VDD = 25 V 4 1000 Coss 100 0 Crss 10 2 f = 1 MHz VGS = 0 V 0 10 20 30 40 50 1 0.1 60 Figure 7. Gate Charge Characteristics 40 160 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 10 Figure 8. Capacitance vs Drain to Source Voltage 100 TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 120 80 VGS = 10 V Limited by Package VGS = 4.5 V 40 o RθJC = 2.3 C/W 1 0.001 0.01 0.1 1 10 100 0 25 1000 P(PK), PEAK TRANSIENT POWER (W) 100 100 μs 10 1 ms THIS AREA IS LIMITED BY rDS(on) 10 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 125 oC/W TA = 25 oC 0.01 0.01 100 ms CURVE BENT TO MEASURED DATA 0.1 1 10 10 s DC 100200 VDS, DRAIN to SOURCE VOLTAGE (V) 125 150 2000 1000 100 10 SINGLE PULSE RθJA = 125 oC/W o 1 TA = 25 C 0.5 -4 -3 -2 10 10 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. C1 100 Figure 10. Maximum Continuous Drain Current vs Case Temperature 300 0.1 75 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 1 50 o tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 1 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 0.0005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. C1 5 www.fairchildsemi.com FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMC8360L N-Channel Shielded Gate Power Trench® MOSFET Dimensional Outline and Pad Layout ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I64 ©2013 Fairchild Semiconductor Corporation FDMC8360L Rev. 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