RENESAS HAT2265H-EL-E

HAT2265H
Silicon N Channel Power MOS FET Power Switching
Rev.1.00
Jun.06.2005
Features
• High speed switching
• Capable of 4.5 V gate drive
• Low drive current
• High density mounting
• Low on-resistance
RDS(on) = 2.5 mΩ typ. (at VGS = 10 V)
Outline
LFPAK
5
5
D
4
G
4
1, 2, 3 Source
4
Gate
5
Drain
S S S
1 2 3
Rev.1.00, Jun.06.2005, page 1 of 10
3
1 2
HAT2265H
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
VDSS
30
V
Gate to source voltage
VGSS
±20
V
Drain current
ID
55
A
220
A
55
A
Drain peak current
ID(pulse)
Body-drain diode reverse drain current
IDR
Note1
Note 2
Avalanche current
IAP
30
A
Avalanche energy
EAR
Note 2
90
mJ
Channel dissipation
Pch
Note3
30
W
Channel to Case Thermal Resistance
θch-C
4.17
°C/W
Channel temperature
Tch
150
°C
Storage temperature
Tstg
–55 to +150
°C
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tch = 25°C, Rg ≥ 50 Ω
3. Tc = 25°C
Rev.1.00, Jun.06.2005, page 2 of 10
HAT2265H
Electrical Characteristics
(Ta = 25°C)
Item
Symbol Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
—
—
V
ID = 10 mA, VGS = 0
Gate to source breakdown
voltage
V(BR)GSS ± 20
—
—
V
IG = ±100 µA, VDS = 0
Gate to source leak current
IGSS
—
—
± 10
µA
VGS = ±16 V, VDS = 0
Zero gate voltage drain current
IDSS
—
—
1
µA
VDS = 30 V, VGS = 0
Gate to source cutoff voltage
VGS(off)
1.6
—
2.5
V
VDS = 10 V, I D = 1 mA
Static drain to source on state
RDS(on)
—
2.5
3.3
mΩ
ID = 27.5 A, VGS = 10 V
resistance
RDS(on)
—
3.4
5.3
mΩ
ID = 27.5 A, VGS = 4.5 V
Forward transfer admittance
|yfs|
60
100
—
S
ID = 27.5 A, VDS = 10 V
Input capacitance
Ciss
—
5180
—
pF
VDS = 10 V
Output capacitance
Coss
—
1200
—
pF
VGS = 0
Reverse transfer capacitance
Crss
—
380
—
pF
f = 1 MHz
Gate Resistance
Rg
—
0.5
—
Ω
Total gate charge
Qg
—
33
—
nc
VDD = 10 V
Gate to source charge
Qgs
—
15
—
nc
VGS = 4.5 V
Gate to drain charge
Qgd
—
7.1
—
nc
ID = 55 A
Turn-on delay time
td(on)
—
13
—
ns
VGS = 10 V, ID = 27.5 A
Rise time
tr
—
65
—
ns
VDD ≅ 10 V
Turn-off delay time
td(off)
—
60
—
ns
RL = 0.36 Ω
Fall time
tf
—
9.5
—
ns
Rg = 4.7 Ω
Body–drain diode forward
voltage
VDF
—
0.81
1.06
V
IF = 55 A, VGS = 0
Body–drain diode reverse
recovery time
trr
—
40
—
ns
IF = 55 A, VGS = 0
diF/ dt = 100 A/ µs
Notes: 4. Pulse test
Rev.1.00, Jun.06.2005, page 3 of 10
30
Note4
Note4
Note4
Note4
HAT2265H
Main Characteristics
Power vs. Temperature Derating
Maximum Safe Operation Area
500
I D (A)
Pch (W)
40
20
10
0
10
n
1 Operation in
this area is
limited by R DS(on)
50
100
150
200
Tc (°C)
Tc = 25°C
1 shot Pulse
0.01
0.1 0.3
1
3
10
30
100
Drain to Source Voltage V DS (V)
10 V
4.5 V
Typical Transfer Characteristics
100
Pulse Test
V DS = 10 V
Pulse Test
3.0 V
2.8 V
60
2.6 V
40
2.4 V
20
ID
(A)
80
Drain Current
I D (A)
1m
s
0m
Op
era
s
=1
tio
Typical Output Characteristics
Drain Current
DC
0.1
Case Temperature
100
10
µ
0µ s
s
10
PW
Drain Current
Channel Dissipation
30
100
80
60
40
20
25°C
Tc = 75°C
-25°C
VGS = 2.2 V
0
2
4
6
Drain to Source Voltage
Rev.1.00, Jun.06.2005, page 4 of 10
8
10
V DS (V)
0
1
2
3
Gate to Source Voltage
5
4
V GS (V)
250
200
150
I D = 50 A
100
20 A
50
10 A
0
Static Drain to Source on State Resistance
R DS(on) (m Ω)
Pulse Test
4
8
12
Gate to Source Voltage
16
20
V GS (V)
Static Drain to Source on State Resistance
vs. Temperature
8
Pulse Test
6
I D = 10 A, 20 A
50 A
4 V GS = 4.5 V
10 A, 20 A, 50 A
2
10 V
0
-25
0
25 50 75 100 125 150
Case Temperature Tc (°C)
Rev.1.00, Jun.06.2005, page 5 of 10
Drain to Source On State Resistance
R DS(on) (m Ω)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Static Drain to Source on State Resistance
vs. Drain Current
10
Pulse Test
5
VGS = 4.5 V
10 V
2
1
1
3
10
100 300
30
Drain Current I D (A)
1000
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
Drain to Source Voltage
V DS(on) (mV)
HAT2265H
1000
300
100
Tc = -25°C
30
75°C
10
25°C
3
1
V DS = 10 V
Pulse Test
0.3
0.1
0.1
0.3
1
3
10
30
Drain Current I D (A)
100
HAT2265H
Body-Drain Diode Reverse
Recovery Time
Typical Capacitance vs.
Drain to Source Voltage
10000
Ciss
Capacitance C (pF)
Reverse Recovery Time trr (ns)
100
50
20
10
0.1
3000
1000
Coss
300
Crss
100
di / dt = 100 A / µs
V GS = 0, Ta = 25°C
30
VGS = 0
f = 1 MHz
10
0.3
1
3
10
30
100
Reverse Drain Current I DR (A)
0
5
V DD = 25 V
12
8
20
V DS
10
10 V
4
5V
0
20
40
60
80
Gate Charge Qg (nc)
Rev.1.00, Jun.06.2005, page 6 of 10
20
25
30
0
100
1000
Switching Time t (ns)
30
V GS
VDD = 5 V
10 V
25 V
V GS (V)
I D = 55 A
15
Switching Characteristics
16
Gate to Source Voltage
Drain to Source Voltage
V DS (V)
Dynamic Input Characteristics
40
10
Drain to Source Voltage V DS (V)
300
t d(off)
100
tf
30
t d(on)
10
tr
3
V GS = 10 V , VDS = 10 V
Rg = 4.7 Ω, duty < 1 %
0.1 0.2 0.5 1
2 5 10 20 50 100
Drain Current I D (A)
HAT2265H
Maximum Avalanche Energy vs.
Channel Temperature Derating
(A)
100
Repetitive Avalanche Energy EAR (mJ)
Reverse Drain Current vs.
Source to Drain Voltage
Reverse Drain Current IDR
80
10 V
V GS = 0
5V
60
40
20
Pulse Test
0
0.4
0.8
1.2
Source to Drain Voltage
1.6
2.0
100
I AP = 30 A
V DD = 15 V
duty < 0.1 %
Rg > 50 Ω
80
60
40
20
0
25
V SD (V)
50
75
100
125
150
Channel Temperature Tch (˚C)
Avalanche Test Circuit
Avalanche Waveform
EAR =
L
V DS
Monitor
1
2
I AP
Monitor
L • IAP2 •
VDSS
VDSS - V DD
V (BR)DSS
I AP
Rg
D. U. T
V DS
VDD
ID
Vin
15 V
50Ω
0
Rev.1.00, Jun.06.2005, page 7 of 10
VDD
HAT2265H
Normalized Transient Thermal Impedance vs. Pulse Width
Normalized Transient Thermal Impedance
γ s (t)
3
Tc = 25°C
1
D=1
0.5
0.3
0.2
0.1
θ ch - c(t) = γs (t) · θ ch - c
θ ch - c = 4.17°C/ W, Tc = 25°C
0.1
0.05
0.03
PDM
0.02
1
0.0
D=
e
uls
PW
p
ot
T
h
0.01
10 µ
1s
PW
T
100 µ
1m
100 m
10 m
1
10
Pulse Width PW (s)
Switching Time Test Circuit
Switching Time Waveform
Vout
Monitor
Vin Monitor
Rg
90%
D.U.T.
RL
Vin
Vin
10 V
V DS
= 10 V
Vout
10%
10%
90%
td(on)
Rev.1.00, Jun.06.2005, page 8 of 10
tr
10%
90%
td(off)
tf
HAT2265H
Package Dimensions
As of January, 2003
Unit: mm
4.9
5.3 Max
4.0 ± 0.2
+0.05
4.2
6.1 –0.3
+0.1
3.95
5
4
0˚ – 8˚
+0.25
+0.05
*0.20 –0.03
0.6 –0.20
1.3 Max
1
1.1 Max
+0.03
0.07 –0.04
3.3
1.0
0.25 –0.03
0.75 Max
0.10
1.27
*0.40 ± 0.06
*Ni/Pd/Au plating
Rev.1.00, Jun.06.2005, page 9 of 10
0.25 M
Package Code
JEDEC
JEITA
Mass (reference value)
LFPAK
—
—
0.080 g
HAT2265H
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.1.00, Jun.06.2005, page 10 of 10