RLP1N08LE Data Sheet April 1999 1A, 80V, 0.750 Ohm, Current Limited, N-Channel Power MOSFET • 1A, 80V • ILIMIT at 150oC = 1.5A Maximum • Built-in Current Limiting • ESD Protected • Controlled Switching Limits EMI and RFI • Specified for 150oC Operation • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PACKAGE TO-220AB • rDS(ON) = 0.750Ω • Temperature Compensated Spice Model Provided Formerly developmental type TA09842. RLP1N08LE 2252.3 Features The RLP1N08LE is a semi-smart monolithic power circuit which incorporates a lateral bipolar transistor, two resistors, a zener diode, and a PowerMOS transistor. Good control of the current limiting levels allows use of these devices where a shorted load condition may be encountered. “Logic level” gates allow this device to be fully biased on with only 5V from gate to source. The zener diode provides ESD protection up to 2kV. These devices can be produced on the standard PowerMOS production line. PART NUMBER File Number BRAND Symbol L1N08LE D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 6-435 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RLP1N08LE Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RLP1N08LE UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 80 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 80 V Electrostatic Voltage at 100pF, 1500Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD 2 kV Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Self Limited Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . . . . . . . . . VGS 5.5 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 30 W Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24 W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, Figure 7 80 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, Figure 8 1 - 2 V - - 1 µA - - 50 µA - - 50 µA - - 0.750 Ω - - 1.5 Ω 1.8 - 3 A 1.1 - 1.5 A - - 6.5 µs - - 1.5 µs tr 1 - 5 µs td(OFF) - - 7.5 µs tf 1 - 5 µs t(OFF) - - 12.5 µs Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Limiting Current IDSS VDS = 65V, VGS = 0V IGSS VGS = 5V, TC = 150oC rDS(ON) IDS(Lim) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time ID = 1A, VGS = 5V Figure 6 VDS = 15V, VGS = 5V Figure 3 TC = 25oC TC = 150oC TC = 25oC TC = 150oC TC = 25oC TC = 150oC VDD = 30V, ID = 1A, VGS = 5V, RGS = 25Ω RL = 30Ω Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA TO-220AB Electrostatic Voltage ESD Human Model (100pF, 1.5kΩ) - - 4.17 oC/W - - 62 oC/W 2000 - - V MIN TYP MAX Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time SYMBOL TEST CONDITIONS VSD ISD = 1A - - 1.5 V trr ISD = 1A - - 1 ms NOTES: 2. Pulsed: pulse duration = ≤ 300µs maximum, duty cycle = ≤ 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. 6-436 UNITS RLP1N08LE Typical Performance Curves Unless Otherwise Specified 10 0.8 0.6 0.4 ID MAX AT 25oC 100µs 1ms ID MIN AT 150oC 10ms 1.0 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) DC 0.2 VDSS MAX = 80V 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 0.1 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 2. FORWARD BIAS SAFE OPERATING AREA 2.0 1.5 1.0 0.5 0 -50 0 50 100 TC, CASE TEMPERATURE (oC) IDS, DRAIN TO SOURCE CURRENT (A) 3.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. VDS = 10V, VGS = 5V 8V 6V 5V 2.0 PULSE TEST PULSE DURATION = 80µs 3.5 DUTY CYCLE = 0.5% MAX VDS = 15V 2.8 3V 1.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 0.5 2V 0 150 0 150oC 0.7 0 2.5 5.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 5. TRANSFER CHARACTERISTICS 6-437 5 2.5 -55oC 2.1 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. SATURATION CHARACTERISTICS 25oC 1.4 4V 1.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 4.2 VGS = 10V TC = 25oC 2.5 FIGURE 3. NORMALIZED CURRENT LIMIT vs CASE TEMPERATURE IDS(ON), DRAIN TO SOURCE CURRENT (A) NORMALIZED DRAIN TO SOURCE CURRENT TJ = MAX RATED 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 7.5 2.0 VGS = 5V, ID = 1A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 1.5 1.0 0.5 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 150 RLP1N08LE Typical Performance Curves 1.2 ID = 250µA VGS = VDS ID = 250µA 1.1 1.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.4 Unless Otherwise Specified (Continued) 1.0 0.8 0.6 1.0 0.9 0.8 0.7 0.4 -50 0 50 100 0.6 -50 150 0 TJ, JUNCTION TEMPERATURE (oC) 50 FIGURE 7. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VDD VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 400 C, CAPACITANCE (pF) 150 FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 500 RL VDS D VGS 300 + 200 G 0 COSS CRSS CISS 100 0 0 RGS 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) S 25 FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 TJ = 150oC ILIM = 1.5A RθJC = 4.17oC/W HSTR = 0oC/W 1oC/W 2oC/W FREE AIR RθJC = 80oC/W 10 5oC/W 5 10oC/W 25oC/W 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 10. SWITCHING TEST CIRCUIT 80 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 TJ, JUNCTION TEMPERATURE (oC) 60 10% DUTY CYCLE = 20% 5% 2% 1% 40 20 50% MAX PULSE WIDTH = 100ms TJ = 150oC, ILIM = 1.5A, RθJC = 4.17oC/W 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 2oC/W FIGURE 11. DC OPERATION IN CURRENT LIMITING 6-438 FIGURE 12. MAXIMUM VDS vs TA IN CURRENT LIMITING RLP1N08LE Typical Performance Curves 60 MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RθJC = 4.17oC/W 80 5% 2% VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) 80 Unless Otherwise Specified (Continued) 1% 10% 40 DUTY CYCLE = 20% 20 50% 0 25 50 75 100 125 60 MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RθJC = 4.17oC/W 5% 10% DUTY CYCLE = 20% 20 50% 50 TA, AMBIENT TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) 1% DUTY CYCLE = 2% 5% 20 10% 20% 50% 50 75 100 125 60 40 20 2% 10% 20% 50% 5% 0 25 150 MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RθJC = 4.17oC/W DUTY CYCLE = 1% 50 TA, AMBIENT TEMPERATURE (oC) 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 25oC/W NOTE: No external heatsink. FIGURE 15. MAXIMUM VDS vs TA IN CURRENT LIMITING 10 FIGURE 16. MAXIMUM VDS vs TA IN CURRENT LIMITING 10 RθJC = RθJC = 4.17oC/W 4.17oC/W 8 8 125oC 100oC 75oC 50oC STARTING TEMP = 25oC TIME TO 150oC (s) TIME TO 150oC (s) 150 80 MAX PULSE WIDTH = 100ms TJ = 150oC ILIM = 1.5A RθJC = 4.17oC/W 40 6 4 2 0 125 FIGURE 14. MAXIMUM VDS vs TA IN CURRENT LIMITING 80 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 NOTE: Heatsink thermal resistance = 10oC/W FIGURE 13. MAXIMUM VDS vs TA IN CURRENT LIMITING 0 25 75 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 5oC/W 60 1% 40 0 25 150 2% STARTING TEMP = 25oC 6 125oC 100oC 75oC 50oC 4 2 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Heatsink thermal resistance = 2oC/W Heatsink thermal capacitance = 4j/oC FIGURE 17. TIME TO 150oC IN CURRENT LIMITING 6-439 20 0 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Heatsink thermal resistance = 5oC/W Heatsink thermal capacitance = 2j/oC FIGURE 18. TIME TO 150oC IN CURRENT LIMITING 20 RLP1N08LE Typical Performance Curves Unless Otherwise Specified (Continued) 10 10 RθJC = 4.17oC/W 8 STARTING TEMP = 25oC TIME TO 150oC (s) TIME TO 150oC (s) 8 6 125oC 100oC 75oC 50oC 4 STARTING TEMP = 25oC 6 125oC 100oC 4 75oC 50oC 2 2 0 RθJC = 4.17oC/W 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 20 NOTE: Heatsink thermal resistance = 10oC/W Heatsink thermal capacitance = 1j/oC 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Heatsink thermal resistance = 25oC/W Heatsink thermal capacitance = 0.5j/oC FIGURE 19. TIME TO 150oC IN CURRENT LIMITING FIGURE 20. TIME TO 150oC IN CURRENT LIMITING 10 TIME TO 150oC (s) 8 6 STARTING TEMP = 25oC 4 125oC 100oC 2 0 75oC 0 50oC 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: No external heatsink. FIGURE 21. TIME TO 150oC IN CURRENT LIMITING 6-440 20 20 RLP1N08LE Temperature Dependence of Current Limiting and Switching Speed The RLP1N08LE is a monolithic power device which incorporates a logic level PowerMOS transistor with a resistor in series with the source. The base and emitter of a lateral bipolar transistor is connected across this resistor, and the collector of the bipolar transistor is connected to the gate of the PowerMOS transistor. When the voltage across the resistor reaches the value required to forward bias the emitter base junction of the bipolar transistor, the bipolar transistor “turns on”. A series resistor is incorporated in series with the gate of the PowerMOS transistor allowing the bipolar transistor to drive the gate of the PowerMOS transistors to a voltage which just maintains a constant current in the PowerMOS transistor. Since both the resistance of the resistor in series with the PowerMOS transistor source and voltage required to forward bias the base emitter junction of the bipolar transistor vary with the temperature, the current at which the device limits is a function of temperature. This dependence is shown in figure 3. The resistor in series with the gate of the PowerMOS transistor results in much slower switching than in most PowerMOS transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable, and a minimum as well as maximum fall time is given in the device characteristics for this type. DC Operation of the RLP1N08LE The limit of the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown as Figure 11. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most Power MOSFET devices today, is limited to 150oC. The maximum voltage allowable can, therefore be expressed as: o ( 150 C – T AMBIENT ) V DS = ---------------------------------------------------------I LIM × ( R θJC + R θCA ) 6-441 (EQ. 1) Duty Cycle Operation of the RLP1N08LE In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLP1N08LE is mounted has a very large thermal storage capability, so for pulse widths of less than 100 milliseconds, the temperature of the header can be considered a constant case temperature calculated simply as: T C = ( V DS × I D × D × R θCA ) + T AMBIENT (EQ. 2) Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 150oC and using the TC calculated above, the expression for maximum VDS under duty cycle operation is: 150 – T C V DS = -----------------------------------------I LIM × D × R θJC (EQ. 3) These values are plotted as Figures 12 thru 16 for various heat sink thermal resistances. Limited Time Operations of the RLP1N08LE Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 milliseconds and the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as figures 17 thru 21 give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 150oC junction termperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur. RLP1N08LE Spice Model (RLP1N08LE) .SUBCKT RLP1N08LE 2 1 3; rev 09/16/91 *Nominal Temperature = 25oC .MODEL MOSMOD NMOS (VTO=1.7 KP=2.1 IS=1e-30 N=10 TOS=1 L=1u W=1u) Vto 21 6 0.33 Rsource 8 7 RDSMOD 0.28 Rdrain 5 16 RDSMOD 0.2 .MODEL RDSMOD RES (TC1=7.54E-3 TC2=2.23E-5) .MODEL RVTOMOD RES (TC1=-2.23E3 TC2=-5.29E-7) .MODEL RVTOMOD2 RES (TC1=0 TC2=0) Ebreak 11 7 17 18 107.3 .MODEL RBKMOD RES (TC1=1.11E-3 TC2=-6.83E-7) .MODEL DBKMOD D (RS=2.78 TRS1=-8.88E-3 TRS2=2.55E-5) .MODEL DBDMOD D (IS=9.91E-15 RS=3.01E-1 TRS1=3.79E-3 TRS2=1.11E-6 +CJO=4.32E-10 Cin 6 8 3.75E-10 Ca 12 8 6.5E-10 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-1) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-3) .MODEL DPLCAPMOD D (CJO=2E-10 IS=1e-30 N=10) Cb 12 14 6.5E-10 .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.65 VOFF=3.35) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.35 VOFF=-1.65) Rgate 9 20 4.48E3 Lgate 1 9 9.5E-10 Ldrain 2 5 2.5E-9 Lsource 3 7 2.5E-9 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 It 8 17 1 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 Rbreak 17 18 RBKMOD 1 Rin 6 8 1e9 Rvto 18 19 RVTOMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 8 19 DC 1 *Current Limiting Control Section .MODEL RSMOD RES (TC1=3.2E-3) Q Control 20 8 7 QMOD 10 .MODEL QMOD NPN (BF=5 VJE=0.5) *ESD Protection DESD 7 9 DESMOD .MODEL DESMOD D(BV=7.185 TBV1=3.5E-4 TBV2=2.2E-6) .ENDS 6-442 TT=2E-7 RLP1N08LE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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