RFT2P03L
Data Sheet
July 1999
2.1A, 30V, 0.150 Ohm, P-Channel Logic
Level, Power MOSFET
Features
This product is a P-Channel power MOSFET manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. This transistor can be operated directly
from integrated circuits.
• rDS(ON) = 0.150Ω
• 2.1A, 30V
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49222.
Ordering Information
PART NUMBER
RFT2P03L
Symbol
PACKAGE
SOT-223
File Number 4574.2
BRAND
D
2P03L
NOTE: RFT2P03L is available only in tape and reel. Use the entire
part number and add the suffix T.
G
S
Packaging
SOT-223
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
7-7-19
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFT2P03L
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
-30
-30
±20V
2.1
Figure 5
Figures 6, 14, 15
1.1
0.009
-55 to 150
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
SYMBOL
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
-30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
-1
-
-3
V
VDS = -30V, VGS = 0V
-
-
-1
µA
VDS = -30V, VGS = 0V, TA = 150oC
-
-
-50
µA
VGS = ±20V
-
-
±100
nA
ID = 2.1A, VGS = -10V (Figure 9)
-
0.120
0.150
Ω
ID = 2.1A, VGS = -4.5V (Figure 9)
-
0.300
0.360
Ω
VDD = -15V, ID ≅ 2.1A,
RL = 7.1Ω, VGS = −10V,
RGS = 21Ω
-
-
50
ns
-
13
-
ns
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
-
18
-
ns
td(OFF)
-
43
-
ns
tf
-
24
-
ns
tOFF
Total Gate Charge
Qg(TOT)
VGS = 0V to -20V
Gate Charge at -10V
Qg(-10)
VGS = 0V to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -2V
VDD = -15V, ID ≅ 2.1A,
RL = 7.1Ω
Ig(REF) = -1.0mA
(Figure 13)
-
-
100
ns
-
27
33
nC
-
14
17
nC
-
1.3
1.6
nC
VDS = -25V, VGS = 0V,
f = 1MHz
(Figure 12)
-
620
-
pF
-
240
-
pF
-
30
-
pF
Pad Area = 0.171 in2 (See note 2)
-
-
110
oC/W
Pad Area = 0.068 in2 (See Tech Brief 377)
-
-
128
oC/W
Pad Area = 0.026 in2 (See Tech Brief 377)
-
-
147
oC/W
MIN
TYP
MAX
UNITS
ISD = -2.1A
-
-
-1.25
V
trr
ISD = -2.1A, dISD/dt = 100A/µs
-
-
49
ns
QRR
ISD = -2.1A, dISD/dt = 100A/µs
-
-
45
nC
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
VSD
TEST CONDITIONS
NOTE:
2. 110oC/W measured using FR-4 board with 0.171 in2 footprint for 1000 seconds.
7-7-20
RFT2P03L
Typical Performance Curves Unless Otherwise Specified
-2.5
RθJA = 110oC/W
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
1.0
0.8
0.6
0.4
-2.0
-1.5
-1.0
-0.5
0.2
0
0
0
25
50
75
100
25
150
125
50
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA , AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
NOTES:
DUTY FACTOR: D = t1/t2
0.01
t2
PEAK TJ = PDM x ZθJA x RθJA + TA
RθJA = 110oC/W
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
t, RECTANGULAR PULSE DURATION (s)
101
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-30
TJ = MAX RATED
TA = 25oC
RθJA = 110oC/W
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
-100
100µs
-10
1ms
10ms
-1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
RθJA = 110oC/W
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
150 - TA
125
I = I25
-10
-0.1
-1
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
7-7-21
-100
-1
10-3
10-2
10-1
100
101
102
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
103
RFT2P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
-6
VGS = -20V
-4
STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
-20
-5
-3
STARTING TJ = 150oC
-2
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
-1
1
10
tAV, TIME IN AVALANCHE (ms)
VGS = -10V
-16
VGS = -7V
-12
VGS = -6V
-8
VGS = -5V
VGS = -4.5V
-4
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
0
100
0
-1.5
-3.0
-4.5
-6.0
-7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
1.8
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-16
-55oC
25oC
150oC
-12
-8
-4
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID, DRAIN CURRENT (A)
-20
FIGURE 7. SATURATION CHARACTERISTICS
-1.5
-3.0
-4.5
-6.0
1.4
1.2
1.0
0.8
0.6
-80
0
0
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = 2.1A
-7.5
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
VGS = VDS, ID = 250µA
1.0
0.8
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
7-7-22
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
-40
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFT2P03L
Typical Performance Curves Unless Otherwise Specified
(Continued)
CISS
C, CAPACITANCE (pF)
600
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
450
COSS
300
150
CRSS
VGS , GATE TO SOURCE VOLTAGE (V)
-10
750
WAVEFORMS IN
DESCENDING ORDER:
ID = 2.1A
ID = 1A
-8
VDD = -15V
-6
-4
-2
0
0
0
-5
-10
-15
-20
-25
0
-30
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
6
9
Qg, GATE CHARGE (nC)
12
15
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
VDS
tAV
L
0
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
+
VDD
DUT
0V
VDD
tP
VGS
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDS
Qg(TH)
RL
0
VGS= -2V
VGS
-
Qg(-10)
+
DUT
VGS= -10V
-VGS
VDD
VGS= -20V
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
7-7-23
FIGURE 17. GATE CHARGE WAVEFORM
RFT2P03L
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(OFF)
td(ON)
tf
tr
VDS
0
RL
10%
10%
VGS
VDS
VDD
+
VGS
VGS
0
DUT
RGS
90%
90%
10%
50%
50%
PULSE WIDTH
90%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal impedance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------R θJA
(EQ. 1)
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the PDM
is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board
2. The number of copper layers and the thickness of the
board
3. The use of external heat sinks
4. The use of thermal vias
5. Air flow and board orientation
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
7-7-24
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
200
RθJA = 75.9 - 19.3 * in(AREA)
147oC/W - 0.026in2
RθJA (oC/W)
Thermal Resistance vs. Mounting Pad
Area
150
128oC/W - 0.068in2
110oC/W - 0.171in2
100
50
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD
AREA
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM. Thermal resistances corresponding to other
component side copper areas can be obtained from Figure
20 or by calculation using Equation 2. The area, in square
inches is the top copper area including the gate and source
pads.
R θJA = 75.9 – 19.3 × in ( Area )
(EQ. 2)
RFT2P03L
PSPICE Electrical Model
.SUBCKT RFT2P03L 2 1 3 ;
REV July 1998
CA 12 8 6.5e-10
CB 15 14 6.4e-10
CIN 6 8 5.77e-10
ESG
8
6
10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
LDRAIN
DRAIN
2
5
+
RLDRAIN
RSLC1
51
+
5
ESLC
51
RSLC2
EBREAK 5 11 17 18 -41.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
+
17
18
EBREAK
50
DPLCAP
IT 8 17 1
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 1.27e-9
LSOURCE 3 7 4.2e-10
RDRAIN
16
EVTHRES
+ 19
8
EVTEMP
LGATE
RGATE
9
20
18 +
22
DBODY
11
21
6
MWEAK
MMED
MSTRO
RLGATE
DBREAK
LSOURCE
CIN
RSOURCE
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
SOURCE
3
7
RLSOURCE
S1A
12
13
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 24e-3
RGATE 9 20 5.2
RLDRAIN 2 5 10
RLGATE 1 9 12.7
RLSOURCE 3 7 4.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 68e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S2A
15
14
13
S1B
RBREAK
18
17
S2B
13
CA
RVTEMP
CB
+
EGS
EDS
IT
14
+
6
8
19
VBAT
5
8
+
8
22
RVTHRES
S1A
S1B
S2A
S2B
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))}
.MODEL DBODYMOD D (IS = 2e-13 RS = 3.5e-2 IKF = 0.7 XTI = 8.2 TRS1 = 6e-4 TRS2 = 5e-7 CJO = 7.3e-10 TT = 3.51e-8 M = 0.4
.MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-4 TRS2 = 1e-5)
.MODEL DPLCAPMOD D (CJO = 2.65e-10 IS = 1e-30 N = 10 M = 0.63)
.MODEL MMEDMOD PMOS (VTO = -2.6 KP = 1.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.2)
.MODEL MSTROMOD PMOS (VTO = -3.27 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -2.11 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 52 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.2e-4 TC2 = -1e-7)
.MODEL RDRAINMOD RES (TC1 = 1.8e-2 TC2 = 2.1e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 1.3e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = 8.8e-4 TC2 = 6.1e-6)
.MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 5.7 VOFF= 2.7)
VON = 2.7 VOFF= 5.7)
VON = -0.1 VOFF= -2.4)
VON = -2.4 VOFF= -0.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7-7-25
RFT2P03L
SPICE Thermal Model
9
REV July 98
JUNCTION
RFT2P03L
CTHERM1 9 8 1.9e-5
CTHERM2 8 7 3.0e-4
CTHERM3 7 6 1.2e-3
CTHERM4 6 5 3.5e-3
CTHERM5 5 4 2.0e-2
CTHERM6 4 3 6.5e-2
CTHERM7 3 2 2.0e-1
CTHERM8 2 1 1
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 9 8 3.5e-2
RTHERM2 8 7 8.5e-2
RTHERM3 7 6 3.5e-1
RTHERM4 6 5 1.85
RTHERM5 5 4 2.75
RTHERM6 4 3 15
RTHERM7 3 2 30
RTHERM8 2 1 50
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
1
7-7-26
AMBIENT
RFT2P03L
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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7-7-27
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