TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
D
D
D
D
D
Low rDS(on) . . . 0.25 Ω Typ
High Output Voltage . . . 60 V
Pulsed Current . . . 10 A Per Channel
Avalanche Energy Capability . . . 105 mJ
Input Transient Protection . . . 2000 V
KTC or KTD† PACKAGE
(TOP VIEW)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
description
The TPIC2601 is a monolithic power DMOS array
that consists of six electrically isolated N-channel
enhancement-mode
DMOS
transistors
configured with a common source and open
drains. Each transistor features integrated
high-current zener diodes to prevent gate
damage in the event that an overstress condition
occurs. These zener diodes also provide up to
2000 V of ESD protection when tested using the
human-body model.
DRAIN6
GATE6
DRAIN5
GATE5
DRAIN4
DRAIN4
GATE4
SOURCE/GND
GATE3
DRAIN3
DRAIN3
GATE2
DRAIN2
GATE1
DRAIN1
† TI Japan only
The TPIC2601 is offered in a 15-pin PowerFLEX (KTC) package and is characterized for operation over the
case temperature range of – 40°C to 125°C. A 15-pin PowerFLEX (KTD) package is also available for TI Japan
only.
schematic
DRAIN1
1
Q1
GATE1
DRAIN2
3
GATE2
4
Q2
DRAIN3
5, 6
GATE3
7
Q3
DRAIN4
DRAIN5
DRAIN6
10, 11
13
15
GATE4
GATE5
Q4 9
Q5 12
Q6
14
2
GATE6
8
SOURCE/GND
NOTE A: For correct operation, no drain terminal may be taken below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerFLEX is a trademark of Texas Intruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-to-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 9 V to 18 V
Continuous drain current, each output, all outputs on, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Pulsed drain current, each output, IOmax, TC = 25°C (see Note 1 and Figure 7) . . . . . . . . . . . . . . . . . . . 10 A
Continuous gate-to-source zener diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 mA
Pulsed gate-to-source zener diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA
Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . 105 mJ
Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W
Power dissipation at (or below) TC = 75°C, all outputs on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.75 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
VGS(th)
Drain-to-source breakdown voltage
VGS(th)match
V(BR)GS
Gate-to-source threshold voltage matching
V(BR)SG
Source-to-gate breakdown voltage
Gate-to-source threshold voltage
Gate-to-source breakdown voltage
ID = 250 µA,
ID = 1 mA,,
See Figure 5
60
VDS = VGS,
1.5
IGS = 250 µA
ISG = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 2 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
IS = 2A,
VGS = 0,
See Notes 2 and 3 and Figure 12
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 48 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short circuited to
source
VGS = 10 V,
IGSSR
Reverse gate current, drain short circuited to
source
drain to source on-state
on state resistance
Static drain-to-source
rDS(
DS(on))
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common
source
Crss
Short-circuit reverse transfer capacitance,
common source
TYP
MAX
2.05
2.2
V
5
40
mV
V
18
V
9
V
VGS = 10 V,
0.5
0.6
V
0.85
1
V
1
0.5
10
VDS = 0
20
200
nA
VSG = 5 V,
VDS = 0
10
100
nA
VGS = 10 V,
ID =2 A,,
See Notes 2 and 3
and Figures 6 and 7
TC = 25°C
0.25
0.3
TC = 125°C
0.4
0.5
VDS = 25 V,
f = 1 MHz,
ID = 1 A
VGS = 0,
See Figure 11
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• DALLAS, TEXAS 75265
µA
Ω
1.3
1.95
S
180
225
110
138
80
100
NOTES: 2. Technique should limit TJ – TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
2
UNIT
0.05
VDS = 15 V,
See Notes 2 and 3
and Figure 9
gfs
MIN
VGS = 0
pF
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
source-to-drain diode characteristics, TC = 25°C
PARAMETER
trr(SD)
Reverse-recovery time
QRR
Total diode charge
TEST CONDITIONS
MIN
IS = 1 A,
VDS = 48 V,
VGS = 0,
0
di/dt = 100 A/µs
A/µs,
See Figures 1 and 14
TYP
MAX
UNIT
72
ns
180
nC
resistive-load switching characteristics, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
td(on)
td(off)
Delay time, VGS↑ to VDS↓ turn on
tr
tf
Rise time, VDS
Qg
Total gate charge
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
Internal drain inductance
5
LS
Rg
Internal source inductance
5
Delay time, VGS↓ to VDS↑ turn off
MAX
UNIT
194
VDD = 25 V,,
tdis = 10 ns,
RL = 25 Ω,,
See Figure 2
430
ten = 10 ns,,
ns
90
Fall time, VDS
180
VDD = 48 V,
V
See Figure 3
ID = 1 A,
A
VGS = 10 V,
V
Internal gate resistance
5.1
6.4
0.5
0.63
2.75
3.4
nC
nH
Ω
500
thermal resistance
PARAMETER
RθJA
RθJC
TEST CONDITIONS
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
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MIN
TYP
MAX
All outputs with equal power
72
All outputs with equal power
4
One output dissipating power
7
• DALLAS, TEXAS 75265
UNIT
°C/W
3
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
2
TJ = 25°C
I SD – Source-to-Drain Diode Current – A
1
Reversed di/dt = 100 A/µs
0
–1
25% of lRM{
–2
–3
Shaded Area = QRR
–4
lRM{
–5
trr(SD)
–6
0
25
50
75
100
125
150
175
200
225
250
t – Time – ns
†IRM = maximum recovery current
Figure 1. Reverse-Recovery Current Waveform of Source-to-Drain Diode
VDD
ten
Pulse Generator
(see Note A)
tdis
90%
RL
VDS
VGS
10 V
90%
10%
0
VGS
DUT
Rgen
50 Ω
td(off)
td(on)
50 Ω
90%
VDS
10%
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: The pulse generator has the following characteristics: ten ≤ 10 ns, tdis ≤ 10 ns, ZO = 50 Ω.
4
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VDS(on)
tr
tf
Figure 2. Resistive Switching
VDD
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
Qgs(th)
0.3 µF
VGS
VDD
DUT
IG = 1 mA
0
Qgd
Gate Voltage
t – Time – s
IG Sampling
Resistor
ID Sampling
Resistor
Qgs = Qg – Qgd
WAVEFORM
TEST CIRCUIT
Figure 3. Gate Charge Test Circuit and Waveform
25 V
tw
10 V
L
VGS
Pulse Generator
(see Note A)
50 Ω
ID
tav
0
VDS
VGS
IAS
(see Note B)
ID
DUT
0
Rgen
V(BR)DSX = 60 V MIN
VDS
50 Ω
0
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 2 A.
Energy test level is defined as E
AS
+
I
AS
V
(BR)DSX
2
t av
+ 105 mJ minimum where t + avalanche time.
av
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
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TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2.5
1
VDS = VGS
ID = 2 A
1.5
ID = 100 µA
1
0.5
0
– 40 – 20
0
20
40
60
0.8
On-State Resistance – Ω
ID = 1 mA
2
r DS(on) – Static Drain-to-Source
VGS(th) – Gate-to-Source Threshold Voltage – V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.6
VGS = 10 V
0.4
VGS = 15 V
0.2
0
– 40 – 20
80 100 120 140 160
TJ – Junction Temperature – °C
0
Figure 5
VGS = 15 V
VGS = 10 V
I D – Drain Current – A
8
On-State Resistance –Ω
rDS(on) – Static Drain-to-Source
80 100 120 140 160
10
9
VGS = 10 V
VGS = 15 V
Delta VGS = 0.4 V
Unless Otherwise
Noted
TJ = 25°C
7
VGS = 6 V
6
5
4
3
VGS = 4 V
2
1
0.1
1
10
0
0
1
ID – Drain Current – A
2
3
4
5
Figure 8
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6
7
8
VDS – Drain-to-Source Voltage – V
Figure 7
6
60
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TJ = 25°C
ÁÁ
ÁÁ
ÁÁ
40
Figure 6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
20
TJ – Junction Temperature – °C
• DALLAS, TEXAS 75265
9
10
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF FORWARD TRANSCONDUCTANCE
40
30
TJ = 25°C
20
15
10
5
TJ = 150°C
4
3
2
5
1
1.85
1.875
1.9
1.925
1.95
1.975
0
2
0
gfs – Forward Transconductance – S
1
2
I SD – Source-to-Drain Diode Current – A
Capacitance – pF
300
250
Ciss
150
Coss
100
Crss
50
0
10
6
7
8
9
10
10
f = 1 MHz
TJ = 25°C
Ciss(0) = 257 pF
Coss(0) = 488 pF
Crss(0) = 213 pF
200
5
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
500
350
4
Figure 10
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
400
3
VGS – Gate-to-Source Voltage – V
Figure 9
450
VDS = 15 V
6
25
0
TJ = – 40°C
7
I D – Drain Current – A
Percentage of Units – %
35
8
Total Number of
Units = 367
VDS = 15 V
ID = 1 A
TJ = 25°C
20
30
40
VDS – Drain-to-Source Voltage – V
VGS = 0
TJ = – 40°C
1
0.1
0.1
TJ = 25°C
TJ = 150°C
1
VSD – Source-To-Drain Voltage – V
10
Figure 12
Figure 11
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TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
TC = 25°C
See Figure 3
VDD = 30 V
8
30
6
20
4
VDD = 48 V
10
2
trr – Reverse-Recovery Time – ns
10
50
40
0
2
3
4
Qg – Gate Charge – nC
85
80
75
70
65
60
50
0
1
90
55
VDD = 20 V
0
VDS = 48 V
VGS = 0
IS = 1 A
TJ = 25°C
See Figure 1
95
VDD = 20 V
VGS – Gate-to-Source Voltage – V
VDS – Drain-to-Source Voltage – V
100
12
60
5
6
0
50
100
150
200
Reverse di/dt – A/µs
Figure 13
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
I D – Maximum Drain Current – A
I AS – Maximum Peak Avalanche Current – A
100
TC = 25°C
10 ms
1 ms
DC
DC
0.5 ms
10 µs
0.1
See Figure 4
10
TC = 25°C
TC = 125°C
1
10
VDS – Drain-To-Source Voltage
100
0.1
1
Figure 16
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10
tav – Time Duration of Avalanche – ms
Figure 15
8
300
Figure 14
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
1
250
• DALLAS, TEXAS 75265
100
TPIC2601
6-CHANNEL COMMON-SOURCE POWER DMOS ARRAY
SLIS048A – NOVEMBER 1996 – REVISED JANUARY 1998
THERMAL INFORMATION
KTC PACKAGE†
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
1
RθJA – Normalized Junction-to-Ambient Thermal Resistance – °C/W
DC Conditions
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
Single Pulse
tc
tw
ID
0
0.01
0.0001
0.001
0.1
0.01
1
10
tw – Pulse Duration – s
† Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink.
NOTE A: ZθA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated