TI TPIC5421L

SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
•
•
•
•
•
•
Low rDS(on) . . . 0.4 Ω Typ
Voltage Output . . . 60 V
Input Protection Circuitry . . . 18 V
Pulsed Current . . . 3 A Per Channel
Extended ESD Capability . . . 4000 V
Direct Logic-Level Interface
DW PACKAGE
(TOP VIEW)
GND
SOURCE4/GND
GATE4
NC
DRAIN4
SOURCE3
DRAIN3
GATE3
NC
NC
description
The TPIC5421L is a monolithic gate-protected
logic-level power DMOS array that consists of four
electrically isolated N-channel enhancementmode DMOS transistors, two of which are
configured with common source. Each transistor
features integrated high-current zener diodes
(ZCXa and ZCXb) to prevent gate damage in the
event that an overstress condition occurs. These
zener diodes also provide up to 4000 V of ESD
protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ
resistor.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SOURCE2/GND
GATE2
NC
NC
DRAIN2
SOURCE1
DRAIN1
GATE1
NC
NC
NE PACKAGE
(TOP VIEW)
DRAIN2
SOURCE2/GND
GATE2
GND
GND
GATE4
SOURCE4/GND
DRAIN4
The TPIC5421L is offered in a 20-pin wide-body
surface-mount (DW) package and a 16-pin
thermally-enhanced dual-in-line (NE) package
and is characterized for operation over the case
temperature of −40°C to 125°C.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SOURCE1
DRAIN1
GATE1
GND
GND
GATE3
DRAIN3
SOURCE3
NC − No internal connection
schematic
DRAIN1
7
14
Q1
Q3
Z1
13
GATE1
ZC1b
D1
D2
Z3
8
GATE3
ZC3b
ZC3a
6
SOURCE3
5
DRAIN4
ZC1a
15
SOURCE1
16
DRAIN2
Q2
GATE2
DRAIN3
Q4
19
3
Z2
Z4
ZC2b
ZC4b
ZC2a
ZC4a
GATE4
1, 2, 20
GND, SOURCE2, SOURCE4
NOTE A: For correct operation, no terminal may be taken below GND.
Pin numbers shown are for the DW package.
Copyright  1995, Texas Instruments Incorporated
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1
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Source-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q2, Q4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −9 V to 18 V
Continuous drain current, each output, TC = 25°C: NE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A
Continuous gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . 180 mJ
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
DISSIPATION RATING TABLE
2
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
DW
1125 mW
9.0 mW/°C
225 mW
NE
2075 mW
16.6 mW/°C
415 mW
•
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•
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
V(BR)GS
V(BR)SG
Gate-to-source breakdown voltage
ID = 250 µA,
ID = 1 mA,
See Figure 5
VGS = 0
VDS = VGS,
Source-to-gate breakdown voltage
IGS = 250 µA
ISG = 250 µA
V(BR)
Reverse drain-to-GND breakdown voltage (across
D1, D2)
Drain-to-GND current = 250 µA
VDS(on)
Drain-to-source on-state voltage
ID = 1 A,
See Notes 2 and 3
VF(SD)
Forward on-state voltage, source-to-drain
VF
MIN
TYP
MAX
60
1.5
UNIT
V
1.85
2.2
V
18
V
9
V
100
V
VGS = 5 V,
0.4
0.475
V
IS = 1 A,
VGS = 0 (Z1, Z2, Z3, Z4),
See Notes 2 and 3 and Figure 12
0.9
1.1
V
Forward on-state voltage, GND-to-drain
ID = 1 A (D1, D2),
See Notes 2 and 3
4.6
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
IGSSR
Forward-gate current, drain short circuited to source
Reverse-gate current, drain short circuited to source
VGS = 15 V,
VSG = 5 V,
VDS = 0
VDS = 0
1
Leakage current, drain-to-GND
VDGND = 48 V
TC = 25°C
TC = 125°C
0.05
Ilkg
0.5
10
TC = 25°C
0.4
0.475
Static drain-to-source on-state resistance
VGS = 5 V,
ID = 1 A,
See Notes 2 and 3
and Figures 6 and 7
TC = 125°C
0.65
0.68
rDS(on)
Forward transconductance
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common source
Crss
Short-circuit reverse-transfer capacitance,
common source
VDS = 25 V,
f = 1 MHz,
0.05
1
0.5
10
20
200
nA
10
100
nA
µA
A
A
µA
Ω
VDS = 15 V,
ID = 0.5 A,
See Notes 2 and 3 and Figure 9
gfs
V
1.25
VGS = 0,
See Figure 11
1.4
S
220
275
120
150
100
125
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER
trr
TEST CONDITIONS
Reverse-recovery time
IS = 0.5 A,
VGS = 0,
See Figures 1 and 14
QRR
VDS = 48 V,
di/dt = 100 A/µs,
Total diode charge
•
MIN
55
Z2 and Z4
150
D1 and D2
200
Z1 and Z3
0.06
Z2 and Z4
0.3
D1 and D2
0.7
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•
TYP
Z1 and Z3
MAX
UNIT
ns
µC
3
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
resistive-load switching characteristics, TC = 25°C
PARAMETER
td(on)
td(off)
Turn-on delay time
tr2
tf2
Rise time
Qg
Total gate charge
TEST CONDITIONS
Turn-off delay time
RL = 25 Ω,
See Figure 2
VDD = 25 V,
tf1 = 10 ns,
MIN
tr1 = 10 ns,
Fall time
VDS = 48 V,
See Figure 3
ID = 0.5 A,
VGS = 5 V,
TYP
MAX
25
50
20
40
21
42
9
18
3.9
5
0.55
0.8
2.5
3.6
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
Internal drain inductance
5
LS
Internal source inductance
5
Rg
Internal gate resistance
UNIT
ns
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
DW package
RθJA
JA
Junction-to-ambient thermal resistance
RθJB
Junction-to-board thermal resistance
RθJP
Junction-to-pin thermal resistance
TYP
MAX
UNIT
90
See Notes 4 and 6
NE package
DW package
See Notes 4 and 6
DW package
See Notes 5 and 6
NE package
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.
5. Package mounted in intimate contact with infinite heatsink.
6. All outputs with equal power
4
MIN
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•
60
53
30
25
°C/W
C/W
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
1.5
VDS = 48 V
VGS = 0
Z1 and Z3‡
I S − Source-to-Drain Diode Current − A
1
Reverse di/dt = 100 A/µs
0.5
0
− 0.5
25% of IRM†
−1
Shaded Area = QRR
− 1.5
−2
IRM(REC)†
trr(SD)
− 2.5
0
25
50
75
100
125
150
175
200
225
250
Time − ns
† IRM(REC) = maximum recovery current
‡ The above waveform is representative of Z2, Z4, D1, and D2 in shape only.
Figure 1. Reverse-Recovery-Current Waveforms of Source-to-Drain Diode
VDD = 25 V
tr1
RL
Pulse Generator
5V
VDS
VGS
0V
VGS
50 Ω
tr2
tf2
CL = 30 pF
(see Note A)
50 Ω
td(off)
td(on)
DUT
Rgen
tf1
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
•
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•
5
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
5V
0.3 µF
Qgs(th)
VDD
VDS
0V
VGS
DUT
IG = 100 µA
Qgd
Gate Voltage
Time
ID CurrentSampling Resistor
IG CurrentSampling Resistor
WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
VDD = 25 V
tw
tav (see Note B)
23 mH
Pulse Generator
(see Note A)
5V
VGS
VDS
ID
0V
IAS
(see Note B)
VGS
50 Ω
ID
DUT
0V
Rgen
50 Ω
V(BR)DSX = 60 V Min
VDS
0V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω .
B. Input pulse duration (tw) is increased until peak current IAS = 3 A.
I
Energy test level is defined as E
where tav = avalanche time
AS
+
AS
V
(BR)DSX
2
t av
+ 180 mJ,
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
6
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•
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
CASE TEMPERATURE
2.5
0.8
VDS = VGS
ID = 1 A
2
ID = 1 mA
1.5
ID = 100 µA
1
0.5
0.7
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
VGS(th) − Gate-to-Source Threshold Voltage − V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS = 4.5 V
0.6
0.5
VGS = 5 V
0.4
0.3
0.2
0.1
0
− 40 − 20
0
20
40
60
0
− 40 − 20
80 100 120 140 160
0
20
Figure 5
80 100 120 140 160
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
3
nVGS = 0.2 V
TJ = 25°C
TJ = 25°C
0.6
I D − Drain Current − A
On-State Resistance − Ω
r DS(on) − Static Drain-to-Source
60
Figure 6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
0.9
0.8
0.7
40
TC − Case Temperature − °C
TJ − Junction Temperature − °C
VGS = 4.5 V
0.5
0.4
0.3
VGS = 5 V
0.2
0.1
0.1
2
1
VGS = 3 V
1
ID − Drain Current − A
0
10
0
2
4
6
8
10 12 14 16 18
VDS − Drain-to-Source Voltage − V
Figure 7
20
Figure 8
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•
7
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
30
I D − Drain Current − A
Percentage of Units − %
25
3
Total Number of
Units = 2888
VDS = 25 V
ID = 0.5 A
TJ = 25°C
20
15
10
2
TJ = − 40°C
1
TJ = 150°C
TJ = 125°C
5
TJ = 25°C
0
1.455
1.443
1.430
1.418
1.405
1.393
1.380
1.368
1.355
1.343
1.330
TJ = 75°C
0
0
1
2
3
4
5
VGS − Gate-to-Source Voltage − V
gfs − Forward Transconductance − S
Figure 9
Figure 10
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
500
C − Capacitance − pF
400
I SD − Source-to-Drain Diode Current − A
450
f = 1 MHz
VGS = 0
TJ = 25°C
350
300
Ciss
250
200
Coss
150
100
Crss
50
5
4
3
VGS = 0
2
1
0.6
0.4
TJ = 125°C
0.2
TJ = 150°C
TJ = 25°C
TJ = 75°C
0.1
0
10
20
30
40
0.1
VDS − Drain-to-Source Voltage − V
1
VSD − Source-to-Drain Voltage − V
Figure 11
8
TJ = − 40°C
Figure 12
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10
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
7
ID = 0.5 A
TJ = 25°C
See Figure 3
60
6
VDD = 20 V
50
5
VDD = 30 V
40
4
30
3
20
2
VDD = 48 V
10
1
VDD = 10 V
VGS − Gate-to-Source Voltage − V
VDS − Drain-to-Source Voltage − V
70
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Qg − Gate Charge − nC
Figure 13
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
200
VDS = 48 V
VGS = 0
IS = 0.5 A
TJ = 25°C
See Figure 1
trr − Reverse-Recovery Time − ns
175
150
125
100
Z2 and Z4
75
50
Z1 and Z3
25
0
100
200
300
400
500
600
700
Reverse di/dt − A/µs
Figure 14
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SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
I D − Maximum Drain Current − A
TC = 25°C
1 µs†
10 ms†
1 ms†
500 µs†
1
ÁÁ
ÁÁ
DW Pkg
NE Pkg
DC Conditions
0.1
0.1
1
10
VDS − Drain-to-Source Voltage − V
† Less than 2% duty cycle
100
Figure 15
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
I AS − Maximum Peak Avalanche Current − A
10
See Figure 4
TC = 25°C
TC = 125°C
1
0.01
0.1
1
10
tav − Time Duration of Avalanche − ms
Figure 16
10
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•
100
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
NE PACKAGE†
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
tc
tw
ID
0
0.0001
0.0001
0.001
0.1
0.01
1
10
tw − Pulse Duration − s
† Device mounted on FR4 printed-circuit board with no heatsink.
NOTES A: ZθJA(t) = r(t) RθJA
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 17
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11
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
THERMAL INFORMATION
DW PACKAGE†
JUNCTION - TO -BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
RθJB − Junction-to-Board Thermal Resistance − °C/W
DC Conditions
d = 0.5
d = 0.2
10
d = 0.1
d = 0.05
d = 0.02
1
d = 0.01
Single Pulse
tc
tw
ID
0
0.1
0.0001
0.001
0.01
0.1
tw − Pulse Duration − s
† Device mounted on a 24 in2, 4-layer FR4 printed-circuit board with no heatsink.
NOTES A: ZθJB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 18
12
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•
1
10
100
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPIC5421LDW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
TPIC5421LNE
OBSOLETE
PDIP
NE
16
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MPDI003 – OCTOBER 1994
NE (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
20 PIN SHOWN
0.070 (1,78) MAX
11
20
PINS **
DIM
A
C
1
20
0.914 (23,22)
MIN
MAX
B
16
0.780 (19,80)
0.975 (24,77)
MIN
0.930 (23,62)
MAX
1.000 (25,40)
10
C
MIN
0.240 (6,10)
0.260 (6,61)
MAX
0.260 (6,60)
0.280 (7,11)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25) M
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
B
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25) M
0°– 15°
0.010 (0,25) NOM
4040054 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (16 pin only)
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