NEC UPD75516

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75516
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75516 is a product in the 75X series(of 4-bit single-chip microcomputers). The 75X series has an
architecture which is comparable to that of 8-bit microcomputers.
The µPD75516 possesses high class processing capacities as a 4-bit single-chip microcomputer with built-in
A/D converter and serial interface, including the capability to process data in lengths of 1, 4 and 8 bits in addition
to its high speed operation.
Details of functions are described in the User's Manual shown below. Be sure to read in design.
µPD75516 User's Manual: IEM–5049
FEATURES
●
●
●
●
●
●
●
●
●
A large
Built-in
Built-in
Built-in
number of I/O Lines: 64 lines (Internal pull-up/pull- down resistor specifiable: 47)
8-bit serial interface: 2 channels
NEC standard serial bus interface (SBI)
8-bit AD converter: 8 channels
High speed operation and a instruction execution time variation function which is effective for saving power.
• 0.95 µs/1.91 µs/15.3 µs (at 4.19 MHz operation), 122 µs (at 32.768 kHz operation)
Program memory (ROM) capacity: 16256 × 8 bits
Data memory (RAM) capacity: 512 × 4 bits
Powerful timer function: 4 channels
• 8-bit timer/event counter
• Watch timer
• 8-bit basic interval timer
• Timer/pulse generator: 14-bit PWM with variable output
Ultra low power consumption clock operation is possible (5 µA TYP.: During operation at 3 V)
Devices with built-in PROM are available (µ PD75P516)
USES
VCRs and CD players, telephones, cameras, etc.
The information in this document is subject to change without notice.
Document No. IC-2471D
(O. D. No. IC-7580D)
Date Published November 1993 P
Printed in Japan
The mark ★ shows major revised points.
© NEC Corporation 1989
µPD75516
ORDERING INFORMATION
Ordering Code
Package
µ PD75516GF-×××-3B9
Remarks
Quality Grade
80-pin plastic QFP (14 × 20 mm)
Standard
"×××" means the specified ROM code.
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
LIST OF µPD75516 FUNCTIONS
Item
On-chip memory
Function
ROM
16256 × 8 bits
RAM
512 × 4bits
General registers
(4 bits × 8 or 8 bits × 4) × 4 banks
Instruction cycle
• 0.95 µs/1.91 µs/15.3 µs (Main system clock: 4.19 MHz operation)
• 122 µs (Subsystem clock: 32.768 kHz operation)
Total
64
CMOS input
16 (dual function and analog input as INT, SIO, PPO, software pull-up capability: 7)
CMOS input/output
28 (LED drive: 4)
• Software pull-up capability : 16
• Mask option pull-down capability: 4
Input/
output
ports
N-ch open-drain
input/output
2
20 (LED drive: 8; 10 V withstand voltage, mask option pull-up capability: 20)
A/D converter
8-bit resolution × 8 channels (successive approximation type)
• Operating voltage: VDD = 3.5 to 6.0 V
Timer/counters
4 channels
Serial Interface
2 channels
Vectored interrupt
External: 3, internal: 4
Test input
External: 1, internal: 1
Instruction set
• Bit data set/reset/test/Boolean operations
• 4-bit data transfer, operation, increment/ decrement, compare
• 8-bit data transfer, operation, increment/ decrement, compare
System clock oscillator
• Ceramic/crystal oscillator for main system clock oscillation: 4.19 MHz
• Crystal oscillator for subsystem clock oscillation: 32.768 kHz
Operating voltage
VDD = 2.7 to 6.0 V
Package
80-pin plastic QFP (14 × 20 mm)
•Timer/event counter
• Basic interval timer
• Timer/pulse generator (14-bit PWM output capability)
• Watch timer
• NEC standard serial bus interface (SBI)/3-wire SIO: 1 channel
• Normal clocked serial interface (3-wire SIO): 1 channel
µPD75516
CONTENTS
1.
PIN CONFIGURATION ................................................................................................................................ 4
2.
EXAMPLE OF SYSTEM CONFIGURATION ..............................................................................................5
3.
INTERNAL BLOCK DIAGRAM .................................................................................................................... 6
4.
PIN FUNCTIONS ......................................................................................................................................... 7
4.1
4.2
4.3
4.4
4.5
PORT PINS ........................................................................................................................................................... 7
NON-PORT PINS .................................................................................................................................................. 9
PIN INPUT/OUTPUT CIRCUIT LIST ................................................................................................................. 10
RECOMMENDED CONNECTIONS OF UNUSED PINS .................................................................................. 13
MASK OPTION SELECTION ............................................................................................................................. 14
5.
MEMORY CONFIGURATION ................................................................................................................... 15
6.
PERIPHERAL HARDWARE FUNCTIONS ................................................................................................. 18
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
PORTS ................................................................................................................................................................. 18
CLOCK GENERATOR ......................................................................................................................................... 19
CLOCK OUTPUT CIRCUIT ................................................................................................................................. 20
BASIC INTERVAL TIMER .................................................................................................................................. 21
WATCH TIMER ................................................................................................................................................... 22
TIMER/EVENT COUNTER ................................................................................................................................. 22
TIMER/PULSE GENERATOR ............................................................................................................................ 24
SERIAL INTERFACE ........................................................................................................................................... 25
A/D CONVERTER .............................................................................................................................................. 29
BIT SEQUENTIAL BUFFER ............................................................................................................................... 30
7.
INTERRUPT FUNCTIONS ......................................................................................................................... 31
8.
STANDBY FUNCTIONS ............................................................................................................................ 33
9.
RESET FUNCTIONS .................................................................................................................................. 34
10. INSTRUCTION SET ................................................................................................................................... 36
11. ELECTRICAL SPECIFICATIONS ............................................................................................................... 45
12. CHARACTERISTIC CURVES ..................................................................................................................... 59
13. PACKAGE INFORMATION ....................................................................................................................... 65
14. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 66
APPENDIX A. DEVELOPMENT TOOLS ........................................................................................................ 67
APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 68
3
µPD75516
AN1
AN2
AN3
AN4/P150
AN5/P151
AN6/P152
AN7/P153
AVSS
P120
P121
P122
P123
P130
P131
P132
P133
1. PIN CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
KR3/P63
KR2/P62
KR1/P61
KR0/P60
P53
P52
P51
P50
VSS
P43
P42
P41
P40
P33
P32
P31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
µPD75516GF-×××-3B9
AV0
AVREF
VDD
* VDD
P113
P112
P111
P110
P103
P102
P101
P100
P93
P92
P91
P90
SI1/P83
SO1/P82
SCK1/P81
PPO/P80
KR7/P73
KR6/P72
KR5/P71
KR4/P70
IC: Internally Connected (Connect to VSS directly.)
*
4
Be sure to supply power to both VDD pins.
P140
P141
P142
P143
RESET
X2
X1
IC
XT2
XT1
VSS
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30
µPD75516
2. EXAMPLE OF SYSTEM CONFIGURATION
VTR (Voltage Synthesizer Tuner)
µ PD75516
Remote
Control IC
SIO
INT0
Input Port
Mechanism
Mechanism
Control
Servo IC
Mechanism
Computer/
Timer
Output Port
Port4, 5
Key Matrix
OSD
Analog
Input
Tuner
PPO
LPF
SIO
FIP Driver
FIP
KR0–KR7
System Clock
Watch Clock
5
INTBT
TIMER/EVENT
COUNTER
#0
TI0/P13
PTO0/P20
PROGRAM
COUNTER (14)
CY
ALU
SP (8)
INTT0
BANK
WATCH
TIMER
BUZ/P23
INTW
GENERAL REG.
TIMER PULSE
GENERATOR
PPO/P80
INTTPG
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
SERIAL
INTERFACE0
ROM
PROGRAM
MEMORY
16256×8 BITS
DECODE
AND
CONTROL
RAM
DATA MEMORY
512× 4 BITS
INTCSI
SI1/P83
SO1/P82
SCK1/P81
SERIAL
INTERFACE1
fx/2N
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60KR7/P73
INTERRUPT
CONTROL
CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
CPU CLOCK
Φ
P00-P03
PORT1
4
P10-P13
PORT2
4
P20-P23
PORT3
4
P30-P33
PORT4
4
P40-P43*
PORT5
4
P50-P53*
PORT6
4
P60-P63
PORT7
4
P70-P73
PORT8
4
P80-P83
PORT9
4
P90-P93
PORT10
4
P100-P103
PORT11
4
P110-P113
PORT12
4
P120-P123 *
PORT13
4
P130-P133 *
PORT14
4
P140-P143 *
PORT15
4
P150-P153
PCL/P22
XT1XT2 X1 X2
RESET
VDD
VSS
A/D
CONVERTER
*
PORTs 4 , 5 and 12 to 14 are 10 V middle-high voltage N-ch open-drain input/output ports.
µPD75516
AVREF
AV SS
CLOCK
DIVIDER
4
8
BIT SEQ.
BUFFER(16)
AN0-AN3
AN4/P150-AN7/P15
CLOCK
OUTPUT
CONTROL
PORT0
3. INTERNAL BLOCK DIAGRAM
6
BASIC
INTERVAL
TIMER
µPD75516
4. PIN FUNCTIONS
4.1
PORT PINS (1/2)
Pin Name
I/O
P00
DualFunction Pin
Input / Output
8-Bit
After Reset Circuit Type *1
I/O
Function
INT4
P01
Input
SCK0
P02
SO0/SB0
P03
SI0/SB1
P10
B
4-bit input port (PORT0).
Internal pull-up resistor can be specified in 3-bit
units by software for P01 to P03.
Input
INT1
P12
INT2
P13
TI0
P20
PTO0
P21
Input/
output
P22
P23
—
PCL
F –B
M–C
4-bit input port (PORT1).
Internal pull-up resistor can be specified in 4-bit
units by software.
4-bit input/ output port (PORT2).
Internal pull-up resistor can be specified in 4-bit
units by software.
×
Input
B –C
×
Input
E–B
×
Input
E–C
High level
(when a pullup resistor is
incorporated)
or high impedance
M
BUZ
P30 *2
P31 *2
P32 *2
—
Input/
output
—
—
—
P33 *2
P40 to P43
Input/
output
Programmable 4-bit input/ output port (PORT3).
Input/ output specifiable in 1-bit units.
Internal pull-up resistor can be specified in 4-bit
units by software.
—
N-ch open-drain 4-bit input/output port (PORT4).
Pull-up resistor can be incorporated in 1-bit units
(mask option).
10 V withstand voltage with open-drain.
—
N-ch open-drain 4-bit input/ output port (PORT5).
Pull-up resistor can be incorporated in 1-bit units
(mask option).
10 V withstand voltage with open-drain.
High level
(when a pullup resistor is
incorporated)
or high impedance
M
Programmable 4-bit input/output port (PORT6).
Input/output specifiable in 1-bit units.
Internal pull-up resistor can be specified in 4-bit
units by software.
Input
F–C
Input
F –A
*2
●
*2
P50 to P53
Input/
output
KR0
P60
P61
P62
KR1
KR2
KR3
P70
KR4
P72
P73
* 1.
2.
Input/
output
P63
P71
F –A
Input
Noise removing
function available
INT0
P11
×
Input/
output
KR5
KR6
●
4-bit input/output port (PORT7).
Internal pull-up resistor can be specified in 4-bit
units by software.
KR7
Schmitt trigger inputs are circled.
Can drive LED directly.
7
µPD75516
4.1
PORT PINS (2/2)
Pin Name
I/O
DualFunction Pin
8-Bit
After Reset
I/O
PPO
P80
P81
SCK1
Input
P82
SO1
P83
SI1
Input / Output
Circuit Type *
E
4-bit input port (PORT8).
×
Input
F
E
B
P90 to P93
Input/
output
4-bit input/output port (PORT9)
Pull-up resistor can be incorporated in 1-bit units
(mask option).
P100 to P103
Input/
output
4-bit input/output port (PORT10).
P110 to P113
Input/
output
4-bit input/output port (PORT11).
P120 to P123
Input/
output
N-ch open-drain 4-bit input/ output port (PORT12).
Pull-up resistor can be incorporated in 1-bit units
(mask option).
10 V withstand voltage with open-drain.
P130 to P133
Input/
output
N-ch open-drain 4-bit input/ output port (PORT13).
Pull-up resistor can be incorporated in 1-bit units
(mask option).
10 V withstand voltage with open-drain.
×
P140 to P143
Input/
output
N-ch open-drain 4-bit input/ output port (PORT14).
Pull-up resistor can be incorporated in 1-bit units
(mask option).
10 V withstand voltage with open-drain.
×
P150 to P153
Input
4-bit input/output port (PORT15).
×
*
8
Function
×
Low level
(when a pull
down resistor
is incorporated) or high
impedance
V
Input
E
Input
E
High level
(when a pullup resistor is
incorporated)
or high impedance
M
×
AN4 to AN7
Schmitt trigger inputs are circled.
×
High level
(when a pullup resistor is
incorporated)
or high impedance
High level
(when a pullup resistor is
incorporated)
or high impedance
Input
M
M
Y-A
µPD75516
4.2
NON-PORT PINS
Function
After Reset
Input / Output
Circuit Type *
P13
External event pulse input pin to the timer/event counter.
—
B –C
Output
P20
Timer/event counter output pin.
Input
E–B
PCL
Output
P22
Clock output pin.
Input
E–B
BUZ
Output
P23
Fixed frequency output pin (for buzzer or system clock
trimming).
Input
E–B
SCK0
Input/
output
P01
Serial clock input/output pin.
Input
F –A
SO0/SB0
Input/
output
P02
Serial data output pin.
Serial bus input/output pin.
Input
F –B
SI0/SB1
Input/
output
P03
Serial data input pin.
Serial bus input/output pin.
Input
M–C
INT4
Input
P00
Edge-detected vectored interrupt input pin (valid for
detection of rising and falling edges).
—
B
—
B–C
—
B –C
Pin Name
I/O
TI0
Input
PTO0
INT0
DualFunction Pin
P10
Input
P11
INT1
Edge-detected testable input pin (rising
edge detection).
Clocked
Asynchronous
INT2
Input
P12
KR0 to KR3
Input
P60 to P63
Serial falling edge detection testable input pin.
Input
F –C
KR4 to KR7
Input
P70 to P73
Serial falling edge detection testable input pin.
Input
F –A
SCK1
Input/
output
P81
Serial clock input/output pin.
Input
F
SO1
Output
P82
Serial data output pin.
Input
E
P83
Serial data input pin.
Input
B
SI1
Input
AN0 to AN3
AN4 to AN7
Asynchronous
Y
—
Input
A/D converter analog input pin.
—
P150 to P153
Y-A
AVREF
Input
—
A/D converter reference voltage input pin.
—
Z
AVSS
—
—
A/D converter reference GND potential pin.
—
—
X1, X2
Input
—
Main system clock oscillation crystal/ceramic connection
pin. An external clock is input to X1 and an antiphase
clock is input to X2.
—
—
XT1
Input
—
Subsystem clock oscillation crystal connection pin. An
external clock is input to XT1 and XT2 is leave open.
—
—
System reset input pin.
—
B
Input
E
XT2
—
RESET
Input
—
PPO
Output
P80
IC
—
—
Internally Connected. Connect to VSS directly.
—
—
VDD
—
—
Positive power supply pin.
—
—
GND potential pin.
—
—
VSS
*
Edge-detected vectored interrupt input
pin (detected edge selection possible).
—
—
Timer/pulse generator pulse output pin.
Schmitt trigger inputs are circled.
9
µPD75516
4.3 PIN INPUT/OUTPUT CIRCUIT LIST
Use of simplified forms of the input/output circuit for each pin of the µPD75516 are shown as follows.
Fig. 4–1 Pin Input/Output Circuit List (1/3)
TYPE A
TYPE D
VDD
VDD
data
P-ch
IN
N-ch
P-ch
OUT
output
disable
N-ch
Push-Pull Output which can be Set to Output High
Impedance (with Both P-ch and N-ch Set to OFF)
CMOS Specified Input Buffer
TYPE B
TYPE E
data
IN/OUT
Type D
output
disable
IN
Type A
Schmitt Trigger Input Having Hysteresis
Characteristics
TYPE B-C
Input/Output Circuit Consisting of Type D Push-Pull
Output and Type A Input Buffer
TYPE B
VDD
VDD
P.U.R.
P.U.R.
P-ch
P.U.R.
enable
P.U.R.
enable
P-ch
data
output
disable
P.U.R. : Pull-Up Resistor
Schmitt Trigger Input Having Hysteresis
Characteristics
10
IN/OUT
Type D
IN
Type A
P.U.R. : Pull-Up Resistor
µPD75516
Fig. 4–1 Pin Input/Output Circuit List (2/3)
TYPE E-C
TYPE F-B
VDD
VDD
P.U.R.
P.U.R.
P.U.R.
enable
P-ch
data
P-ch
VDD
output
disable
(P-ch)
P-ch
IN/OUT
IN/OUT
Type D
data
output
disable
output
disable
output
disable
(N-ch)
Type A
N-ch
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
TYPE F
TYPE F-C
VDD
P.U.R.
data
IN/OUT
Type D
output
disable
P.U.R.
enable
P-ch
data
IN/OUT
Type D
output
disable
Type B
Type B
Input/Output Circuit Consisting of Type D Push-Pull
Output and Type B Schmitt Trigger input
TYPE F-A
P.U.R. : Pull-Up Resistor
P.U.R.
(Mask
Option)
P.U.R.
P.U.R.
enable
VDD
TYPE M
VDD
P-ch
N-ch
(+10 V
Withstand
Voltage)
data
data
IN/OUT
Type D
IN/OUT
output
disable
output
disable
Type B
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
11
µPD75516
Fig. 4–1 Pin Input/Output Circuit List (3/3)
TYPE M-C
TYPE Y-A
VDD
In Instruction
P.U.R.
P.U.R.
enable
P-ch
VDD
IN/OUT
data
IN
VDD
N-ch
P-ch
N-ch
+
-
Sampling C
output
disable
AVss
AVss
input
enable
P.U.R. : Pull-Up Resistor
TYPE V
Reference Voltage
(from the Series Resistance
String Voltage Tap)
TYPE Z
data
IN/OUT
AVREF
Type D
output
disable
Type A
Reference
Voltage
P.D.R.
(Mask
Option)
P.D.R.: Pull-Down Resistor
TYPE Y
VDD
IN
VDD
P-ch
N-ch
+
Sampling C
AVss
AVss
input
enable
12
Reference Voltage
(from the Series Resistance
String Voltage Tap)
AVSS
µPD75516
4.4
RECOMMENDED CONNECTIONS OF UNUSED PINS
Table 4-1 Recommended Connection of Unused Pins
Pin
P00/INT4
Recommended Connection
Connect to V SS
P01/SCK0
P02/SO0/SB0
Connect to VSS or VDD
P03/SI1/SB1
P10/INT0 to P12/INT2
Connect to V SS
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
Input state : Connect to VSS or VDD
P30 to P33
P40 to P43
Ouput state : Leave open
P50 to P53
P60/KR0 to P63/KR3
P70/KR4 to P73/KR7
P80/PPO
P81/SCK1
Connect to V SS or VDD
P82/SO1
P83/SI1
P90 to P93
P100 to P103
Input state : Connect to VSS or VDD
P110 to P113
P120 to P123
Ouput state : Leave open
P130 to P133
P140 to P143
P150/AN4 to P153/AN7
Connect to V SS
AN0 to AN3
XT1
Connect to V SS or VDD
XT2
Leave open
AVREF
AVSS
Connect to V SS
IC
13
µPD75516
4.5 MASK OPTION SELECTION
The following mask options are available for the pins.
(1) Specification of internal pull-up/pull-down resistor
Table 4-2 Pull-Up/Pull-Down Resistor Selection
Pins
Mask Option
P40 to P43,
P50 to P53,
P120 to P123,
➀ With pull-up resistor
➁ Without pull-up resistor
(specifiable bit-wise)
P130 to P133,
(specifiable bit-wise)
P140 to P143
➀ With pull-down resistor
P90 to P93
➁ Without pull-down resistor
(specifiable bit-wise)
(specifiable bit-wise)
(2) Specification of internal feedback resistor for subsystem clock oscillation
Table 4-3 Feedback Resistor Selection
Pins
Mask Option
➀
XT1, XT2
Note
14
With feedback resistor
(subsystem clock used)
➁ Without feedback resistor
(subsystem clock not used)
When the subsystem clock is not used, operation is not affected if a feedback resistor is incorporated, but
the supply current IDD is increased.
µPD75516
5. MEMORY CONFIGURATION
• Program memory (ROM) ...... 12160 × 8 bits (0000H to 2F7FH)
• 0000H, 0001H
: Vector table in which the program start addresses by reset are written.
• 0002H to 000DH : Vector table in which the program start addresses by interrupt are written.
• 0020H to 007FH : Table area referred by the GETI instruction.
• Data memory
• Data area ... 512 × 4 bits (000H to 1FFH)
• Peripheral hardware area ... 128 × 4 bits (F80H to FFFH)
15
µPD75516
Fig. 5–1 Program Memory Map
Address
7
0000H
6
MBE
RBE
0
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
MBE
0002H
RBE
INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
0004H
MBE
RBE
INT0 Start Address (High-Order 6 Bits)
CALLF
! faddr
Instruction
Entry
Address
INT0 Start Address (Low-Order 8 Bits)
0006H
MBE
RBE
INT1 Start Address (High-Order 6 Bits)
CALL !addr
Instruction
Subroutine
Entry Address
INT1 Start Address (Low-Order 8 Bits)
0008H
MBE
RBE
INTCSI0 Start Address (High-Order 6 Bits)
INTCSI0 Start Address (Low-Order 8 Bits)
000AH
MBE
RBE
BRCB
! caddr
Instruction
Branch
Address
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
MBE
000CH
RBE
BR !addr
Instruction
Branch Address
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
INTTPG Start Address (High-Order 6 Bits)
INTTPG Start Address (Low-Order 8 Bits)
≈
≈
0020H
GETI Instruction Reference Table
007FH
0080H
07FFH
0800H
≈
≈
≈
≈
≈
≈
BRCB !caddr
Instruction
Branch Address
≈
≈
BRCB !caddr
Instruction
Branch Address
≈
≈
Branch Destination
Address and Subroutine
Entry Address by
GETI Instruction
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
BRCB !caddr
Instruction
Branch Address
3F7FH
Remarks
16
In cases other than above, the program can branch to an address for which only the lower 8–bit of the
PC have been changed, by a BR PCDE or BR PCXA instruction.
µPD75516
Fig. 5–2 Data Memory Map
Data Memory
General
Register Area
Memory Bank
000H
(32 × 4)
01FH
008H
Stack Area
Data Area
Static RAM
(512 × 4)
256 × 4
0
256 × 4
1
0FFH
100H
1FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
15
FFFH
17
µPD75516
6. PERIPHERAL HARDWARE FUNCTIONS
6.1
PORTS
There are the following 3 types of I/O ports.
•
•
CMOS input (PORT0, 1, 8, 15)
CMOS input/output (PORT2, 3, 6, 7, 9, 10, 11)
•
N-ch open-drain input/output (PORT4, 5, 12, 13, 14) : 20
Total
: 16
: 28
64
Table 6–1 Port Functions
Port (Pin name)
Function
PORT 0
4-bit input
Operation/Features
Can always be read or tested regardless of the
operating mode of the dual function pin.
PORT 1
Can be set in the input or output mode as a
4-bit unit.
PORT 2
4-bit input/output
PORT 3 *
PORT 4 *
PORT 5 *
4-bit input/output
PORT 7
18
Shares the use of the pin with
KR0 to KR3.
Shares the use of the pin with
KR4 to KR7.
With a mask option, the internal
pull-up resistance can be specified in 1-bit units.
4-bit input/output
Can be set in input or output mode in 4-bit
units.
PORT 11
*
Can be set in input or
output mode in 1/4-bit With ports 6 and 7 as a
units
pair, data can be input
and output in 8-bit units.
Can be set in input or
output mode in 4-bit
units
Can be set in input or output mode in 4-bit
units.
PORT 10
PORT 15
With ports 4 and 5 as a
With a mask option, the internal
pair, data can be input
pull-up resistance can be speciand output in 8-bit units. fied in 1-bit units.
4-bit input/output
PORT 9
PORT 14
Shares the use of the pin with
PTO0, PCL, BUZ
Shares the use of the pin with
PPO, SCK1, SO1 and SI1.
4-bit input
PORT 13
Shares the use of the pin with
INT0 to INT2 and TI0.
Can always be read or tested regardless of the
operating mode of the dual function pin.
PORT 8
PORT 12
Shares the use of the pin with
INT4, SCK0, SO0/SB0, SI0/SB1.
Can be set in the input or the output mode in
1/4-bit units
4-bit input/output
Can be set in input or
(N-ch open-drain 10 V output mode in 4-bit
withstand voltage)
units
PORT 6
Remarks
4-bit input/output
Can be set in input or output mode in 4-bit
(N-ch open-drain 10 V
units.
withstand voltage)
4-bit input
Can drive a LED directly.
Can always be read or tested regardless of the
operating mode of the dual function pin.
With a mask option, the internal
pull-up resistance can be specified in 1-bit units.
Shares the use of the pin with
AN4 to AN7.
µPD75516
6.2
CLOCK GENERATOR
The clock generator operation is determined by the processor clock control register (PCC) and the system clock
control register (SCC).
2 kinds of clocks such as a main system clock and a subsystem clock are available.
In addition, the instruction execution time can be changed.
• 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: 4.19 MHz operation)
• 122 µs (Subsystem clock: 32.768 kHz operation)
Fig. 6–1 Clock Generator Block Diagram
• Basic Interval Timer (BT)
• Timer/Event Counter
• Serial Interface
• Watch Timer
• Clock Output Circuit
• A/D Converter
• INT0 Noise Eliminator
XT1
Timer/Pulse
Generator
X1
X2
Watch Timer
Main System
fX
Clock Oscillation
Circuit
1/8~1/4096
1/
2
Oscillation
Stop
Frequency Divider
Selector
SCC
1/
16
Frequency Divider
Selector
XT2
Subsystem
f XT
Clock Oscillation
Circuit
SCC3
SCC0
1/4
PCC
Internal Bus
Φ
• CPU
• Clock Output
Circuit
• INT0 Noise
Eliminator
PCC0
PCC1
4
HALT F/F
HALT*
STOP*
PCC2
S
PCC3
R
PCC2 and PCC3
Clear
STOP F/F
Q
Q
Wait Release
Signal from BT
S
RESET Signal
R
*
Instruction execution
Remarks
Standby Release Signal from
Interrupt Control Circuit
1.
fX = Main system clock frequency
2.
3.
4.
5.
fXT = Subsystem clock frequency
Φ = CPU clock
PCC: Processor clock control register
SCC: System clock control register
6.
One clock cycle (tCY) of Φ is 1 machine cycle of the instruction. With tCY, refer to "AC CHARACTERISTICS" in 11. "Electrical Specifications".
19
★
µPD75516
6.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock pulses
to remote control outputs or peripheral LSI's.
• Clock output (PCL) : Φ , 524, 262, 65.5 kHz (4.19 MHz operation)
• Buzzer output (BUZ) : 2 kHz (4.19 MHz, or 32.768 kHz operation)
Fig. 6–2 Clock Output Circuit Configuration
Form Clock
Generator
Φ
f x /23
Output Buffer
Selector
f x /24
PCL/P22
6
f x /2
PORT2.2
CLOM CLOM CLOM CLOM CLOM
2
3
1
0
P22 Output
Latch
Bit 2 of PMGB
Port 2 Input/
Output Mode
Specification Bit
4
Internal Bus
Remarks
20
Consideration is given so that a low amplitude pulse is not output when switching between clock output
enable and disable.
µPD75516
6.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions.
• It operates as an interval timer which generates reference time interrupts.
• It can be applied as a watchdog timer which detects when a program is out of control.
• Selects and counts wait times when the standby mode is released.
• It reads count contents.
Fig. 6–3 Basic Interval Timer Configuration
From Clock
Generator
fX/2
fX/2
Clear
5
7
fX/2
Set
Basic Interval Timer
(8-Bit Frequency Divider)
MPX
fX/2
Clear
9
BT
12
BT Interrupt
Request Flag
IRQBT
Vectored
Interrupt
Request
Signal
3
BTM3
SET1*
BTM2
BTM1
Wait Release
Signal during
Standby Release
BTM0 BTM
8
4
Internal Bus
*
Instruction execution.
21
µPD75516
6.5
WATCH TIMER
The µPD75516 incorporates one channel of watch timer which has the following functions.
• Sets test flags (IRQW) at 0.5-second intervals.
The standby mode can be released with IRQW.
• 0.5-second time intervals can be created in either the main system clock or the subsystem clock.
• In the rapid feed mode, time intervals which are 128 times normal (3.91 ms) can be set, making this function
convenient for program debugging and testing.
• A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and
trimming system clock oscillator frequencies.
• The frequency divider can be cleared, so this watch can be started at 0 second.
Fig. 6–4 Watch Timer Block Diagram
fW
(256 Hz : 3.91 ms)
7
2
From
Clock
Generator
fW
128
(32.768 kHz)
Selector
fW
14
2
fW
Frequency Divider
(32.768 kHz)
fXT
(32.768 kHz)
INTW
IRQW
Set Signal
Selector
2Hz
0.5 sec
fW
16
(2.048 kHz) Clear
Output Buffer
P23/BUZ
WM
WM7
PORT2.3
0
0
0
0 WM2 WM1 WM0
8
P23
Output
Latch
Bit 2 of PMGB
Port 2
Input/Output
Mode
Bit Test Instruction
Internal Bus
Remarks
6.6
Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz.
TIMER/EVNET COUNTER
The µPD75516 incorporates one channel of timer/event counter which has the following functions.
• Operates as a programmable interval timer.
• Outputs square waves in the desired frequency to the PTO0 pin.
• Operates as an event counter.
• Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation).
• Supplies a serial shift clock to the serial interface circuit.
• Count status read function.
22
Fig. 6–5 Timer/Event Counter Block Diagram
Internal Bus
8
SET1 *
8
8
TM0
TM07 TM06 TM05 TM04 TM03 TM02
TMOD0
TM01 TM00
8
PORT1.3
Match
Input Buffer
8
Reset
P13/TI0
T0
Count Register (8)
From Clock
Generator
CP
PORT2.0 Bit 2 of PGMB
Port 2
P20
Input/
Output
Output
Latch
Mode
To Serial
Interface
TOUT
F/F
Comparator (8)
MPX
TOE0
TO
Enable
Flag
Modulo Register (8)
P20/PTO0
Output
Buffer
INTT0
IRQT0
Set Signal
Clear
Timer Operation Start
RESET
IRQT0
Clear Signal
*
Instruction execution
µPD75516
23
µPD75516
6.7
TIMER/PULSE GENERATOR
The µPD75516 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse
generator. The timer/pulse generator has the following functions.
(a)
Functions available in the timer mode
• 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels
• Square wave output to PPO pin
(b)
Functions available in the PWM pulse generate mode
• 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to analog converter and
applicable to tuning)
• Interrupt generation of fixed time interval
If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.
Note
If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result.
To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode
register.
Fig. 6–6 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal Bus
8
8
MODL
Modulo Register L (8)
MODH
Modulo Register H (8)
TPGM3
(Set to "1")
INTTPG
IRQTPG
Set Signal
Modulo Lach H (8)
8
Output
Buffer
Match
Comparator (8)
Selector
T F/F
PPO
Frequency
Divider
fX
1/2
TPGM1
CP
Prescalar Select Latch (5)
Clear
24
Set
8
Count Register (8)
Clear
TPGM4TPGM5 TPGM7
µPD75516
Fig. 6–7 Timer/Pulse Generator Block Diagram (PWM Pulse Generator Mode)
Internal Bus
8
8
MODH
Modulo Register H (8)
MODL
Modulo Register L (8)
TPGM3
MODL7-2 (6)
MODH (8)
Modulo Latch (14)
Output Buffer
TPGM1
fx
PWM Pulse Generator
Selector
1/2
PPO
Frequency Divider
INTTPG
TPGM5
(IRQTPG Set Signal)
TPGM7
15
( 2 = 7.81 ms : fX = 4.19 MHz operation)
fX
6.8
SERIAL INTERFACE
The µPD75516 has two serial interface channels on chip. The differences between channel 0 and channel 1 are
shown in Table 6–2.
Table 6–2 Differences between Channels 0 and 1
Serial Transfer Mode and
Function
Clock selection
Channel 0
fX/24 , fX/23 , TOUT F/F, external clock
3-wire serial I/O Transfer mode MSB first/LSB first switchable
Transfer end
flag
2-wire serial I/O
Serial transfer end interrupt request
flag (IRQCSI0)
Use enabled
Channel 1
fX/24, fX/23, external clock
MSB first
Serial transfer end flag (EOT)
None
Serial bus interface (SBI)
(1)
Serial interface (channel 0) functions
The following 4 modes are available to the µPD75516 serial interface (channel 0).
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode (serial bus interface mode)
25
26
Fig. 6–8 Serial Interface (Channel 0) Block Diagram
Internal Bus
8/4 Bit
Test
CSIM0
8
8
Bit Manipulation
Slave Address Register (SVA)
Addres Comparator
(8)
(8)
RELT
CMDT
SO0
SET CLR Latch
D
Q
ACKT
ACKE
BSYE
Shift Register (SIO0)
SBIC
Match
Signal
(8)
P03/SI/SB1
Selector
Bit Test
8
Selector
P02/SO/SB0
Busy/
Acknowledge
Output Circuit
Bus Release/
Command/
Acknowledge
Detection Circuit
P01/SCK0
Serial Clock
Counter
P01
Output
Latch
RELD
CMDD
ACKD
INTCSI0
INTCSI0 Control
 IRQCSI0 


 Set Signal 
Circuit
3
Serial Clock
Control Circuit
MPX
fX/24
fX/2
6
fX/2
TOUT F/F
(From Timer/
Event Counter)
External
SCK0
µPD75516
µPD75516
(2)
Serial interface (channel 1) functions
The following 2 modes are available to the µPD75516 serial interface (channel 1).
• Operation stop mode
• 3-wire serial I/O mode
27
28
Fig. 6–9 Serial Interface (Channel 1) Block Diagram
Internal Bus
8
SIO1 Write Signal (Serial Start Signal)
bit0
P83/SI1
Bit Manipulation
7
bit7
Bit Manipulation
8
0
CSIM1
SIO1
Shift Register 1 (8)
Serial Operating Mode Register 1 (8)
P82/SO1
Clear
Serial Transfer
End Flag (EOT)
Overflow
Serial Clock
Counter (3)
Set
Clear
P81/SCK1
R
Q
S
fx/23
MPX
fx/24
µPD75516
µPD75516
6.9
A/D CONVERTER
The µPD75516 incorporates an 8–bit resolution A/D converter with 8–channel analog inputs (AN0 to AN7).
The A/D converter employs successive approximation.
Fig. 6–10 A/D Converter Block Diagram
Internal Bus
8
0
ADM6 ADM5 ADM4 SOC
EOC
ADM1
0
ADM
8
AN0
Control Circuit
Simple & Hold
Circuit
AN1
AN2
+
AN3
Multiplexer
SA Register (8)
–
AN4
Comparator
AN5
AN6
8
AN7
Tap Decoder
AV REF
R/2
R
R
R
R/2
AV SS
29
µPD75516
6.10 BIT SEQUENTIAL BUFFER: 16 BITS
The bit sequential buffer is a special data memory for bit manipulation. In particular it facilitates bit manipulation
switch the address and bit specifications sequentially modified, and is thus useful for bit–wise processing of data
comprising many bits.
Fig. 6–11 Bit Sequential Buffer Format
Address
Bit
3
Symbol
L Register
FC2H
FC3H
2
1
0
3
BSB3
L=F
2
1
FC1H
0
3
BSB2
L=C L=B
2
1
0
FC0H
3
2
BSB1
L=8 L=7
1
0
BSB0
L=4 L=3
DECS L
INCS L
Remarks
30
In pmem.@L addressing, the specified bit shifts in accordance with the L register.
L=0
µPD75516
7. INTERRUPT FUNCTIONS
The µPD75516 has nine types of interrupt sources and can generate multiple interrupts with priority order.
2 kind of test sources are also available. INT2 of these test sources is an edge detection testable input.
The µPD75516 interrupt control circuit has the following functions:
• Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt
enable flag (IE×××) and the interrupt master enable flag (IME).
• Function of setting any interrupt start address.
• Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).
• Interrupt request flag (IRQ×××) test function (Interrupt generation can be checked by software).
• Standby mode release function (Interrupt to be released by interrupt enable flag can be selected).
31
32
Fig. 7-1 Interrupt Control Circuit Block Diagram
Internal Bus
4
2
2
2
IM2
IM1
IM0
Noise
Eliminator
INT4
/P00
INT0
/P10
INT1
/P11
(IME)
Decoder
IRQBT
Both Edges
Detection
Circuit
Edge
Detection
Circuit
IRQCSI0
INTTPG
Vector
Table
Address
Generator
Circuit
IRQTPG
IRQW
Selector
INTW
KR7/P73
Priority Control
Circuit
IRQT0
INTT0
Falling Edge
Detection
Circuit
VRQn
IRQ1
INTCSI0
KR0/P60
IRQ4
IRQ0
Edge
Detection
Circuit
Rising Edge
Detection
Circuit
IST
Interrupt Enable Flag (IE XXX )
INT
BT
INT2
/P12
IPS
2
IRQ2
Standby Release
Signal
IM2
µPD75516
µPD75516
8. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the µPD75516 to decrease power
consumption in the program standby mode.
Table 8-1 Operation Status in Standby Mode
STOP Mode
HALT Mode
STOP instruction
HALT instruction
System clock when set
Setting enabled only with main system
clock.
Setting enabled with either main system
clock or subsystem clock.
Clock generator
Oscillator stops only with main system
clock.
Stops only with CPU clock Φ (Oscillation
continued).
Basic interval timer
Operation stopped.
Operation (IRQBT set at reference time
intervals).
Serial interface (channel 0)
Operation enabled only when external
SCK0 input is selected for serial clock.
Operation enabled when the main system
clock oscillates or with external SCK0.
Serial interface (channel 1)
Operation enabled only when external
SCK1 input is selected for serial clock.
Operation enabled only when the main
system clock oscillates.
Timer/event counter
Operation enabled only when TI0 pin
input is specified for count clock.
Operation enabled only when the main
system clock oscillates.
Watch timer
Operation enabled only fXT is selected for
Operation enabled.
count clock.
A/D converter
Operation stopped.
Operation enabled only when the main
system clock oscillates.
Timer/pulse generator
Operation stopped.
Operation enabled only when the main
system clock oscillates.
Operating state
Set instruction
External interrupt
CPU
Release signal
INT1, 2, and 4 operation enabled.
INT0 operation disabled.
Operation stopped.
Interrupt request signal or RESET input from operational hardware enabled by
interrupt enable flag.
33
µPD75516
9. RESET FUNCTION
The µPD75516 is reset and the hardware is initialized as shown in Table 9-1 by RESET input. The reset
operation timing is shown in Fig. 9-1.
Fig. 9-1 Reset Operation by RESET Input
Wait
(31.3 ms/4.19 MHz)
RESET Input
Operating Mode or
Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
Table 9-1 Status of Each Hardware after Resetting (1/2)
Hardware
Program counter (PC)
Carry flag (CY)
PSW
RESET Input in Standby
Mode
RESET Input during
Operation
Low-order 6 bits of program
memory address 0000H are
set in PC13 to 8 and the
contents of address 0001H
are set in PC7 to 0.
Same as the left
Held
Undefined
Skip flag (SK0 to 2)
0
0
Interrupt status flag (IST0, 1)
0
0
Bank enable flag (MBE, RBE)
Bit 6 of program memory
address 0000H is set in RBE,
and bit 7 is set in MBE.
Same as the left
Stack pointer (SP)
Undefined
Undefined
Data memory (RAM)
Held*
Undefined
General register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank selection register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
Mode register (BTM)
0
0
Counter (T0)
0
0
FFH
FFH
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer/pulse
generator
Modulo register
Held
Held
Mode register
0
0
Watch timer
Mode register (WM)
0
0
Basic interval
timer
Timer/event
counter
Counter (BT)
Modulo register (TMOD0)
Mode register (TM0)
* Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
34
µPD75516
Table 9-1 Hardware Statuses after Reset (2/2)
RESET Input in Standby
Mode
RESET Input during
Operation
Held
Undefined
Operating mode register 0 (CSIM0)
0
0
SBI control register (SBIC)
0
0
Held
Undefined
1
1
04H (EOC = 1)
04H (EOC = 1)
7FH
7FH
Processor clock control register (PCC)
0
0
System clock control register (SCC)
0
0
Clock output mode register (CLOM)
0
0
Held
Undefined
Operating mode register 1 (CSIM1)
0
0
Serial transfer end flag (EOT)
0
0
Interrupt request flag (IRQ×××)
Reset (0)
Reset (0)
Interrupt enable flag (IE×××)
0
0
Interrupt master enable flag (IME)
0
0
0, 0, 0
0, 0, 0
Output buffer
Off
Off
Output latch
Clear (0)
Clear (0)
Input/output mode register (PMGA, B, C)
0
0
Pull-up resistor specify register (POGA)
0
0
Held
Undefined
Hardware
Shift register (SIO0)
Serial interface
(channel 0)
Slave address register (SVA)
P01/SCK0 output latch
Mode register (ADM), EOC
A/D converter
SA register
Clock generator
and clock
output circuit
Shift register (SIO1)
Serial interface
(channel 1)
Interrupt function
INT0, 1, and 2 mode registers (IM0, 1, 2)
Digital port
Bit sequential buffer (BSB0 to BSB3)
35
µPD75516
10. INSTRUCTION SET
(1)
Operand identifier and description
Enter an operand in the operand column of each instruction using the description method relating to the
operand identifier of the instruction (For details, refer to "RA75X Assembler Package User's Manual – Language
Volume" (EEU–730)). If more than one description method is available, select one. Capital alphabetic letters,
plus and minus signs are keywords. Describe them as they are.
In the case of immediate data, describe appropriate numerical values or labels.
Identifier
*
36
Description Method
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp’
rp’1
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA’, BC’, DE’, HL’
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
rpa1
HL, HL+, HL-, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
bit
8-bit immediate data or label*
2-bit immediate data or label
fmem
pmem
FB0H to FBFH and FF0H to FFFH immediate data or labels
FC0H to FFFH immediate data or labels
addr
caddr
faddr
0000H to 3F7FH immediate data or labels
12-bit immediate data or label
11-bit immediate data or label
taddr
20H to 7FH immediate data (bit0 = 0) or label
PORTn
IE×××
RBn
MBn
PORT0 to PORT15
IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG
RB0 to RB3
MB0, MB1, MB2, MB15
For 8-bit data processing, only even addresses can be specified.
µPD75516
(2)
Legend for operation description
A
: A register; 4-bit accumulator
B
: B register
C
D
E
H
:
:
:
:
C register
D register
E register
H register
L
X
XA
BC
:
:
:
:
L register
X register
Register pair (XA); 8-bit accumulator
Register pair (BC)
DE
HL
XA’
BC’
:
:
:
:
Register pair (DE)
Register pair (HL)
Expanded register pair (XA’)
Expanded register pair (BC’)
DE’
HL’
PC
SP
:
:
:
:
Expanded register pair (DE’)
Expanded register pair (HL’)
Program counter
Stack pointer
CY
PSW
MBE
RBE
:
:
:
:
Carry flag; Bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
PORTn
IME
IPS
IE×××
:
:
:
:
Port n (n
Interrupt
Interrupt
Interrupt
RBS
MBS
PCC
.
:
:
:
:
Register bank select register
Memory bank select register
Processor clock control register
Address and bit delimiter
(××)
××H
: Contents addressed by ××
: Hexadecimal data
= 0 to 15)
master enable flag
priority select register
enable flag
37
µPD75516
(3)
Description of symbols in the addressing area column
*1
MB = MBE • MBS
(MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3F7FH
*7
addr = (Current PC) – 15 to (Current PC) – 1,
(Current PC) + 2 to (Current PC) + 16
*8
caddr = 0000H
1000H
2000H
3000H
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
Remarks 1.
2.
3.
4.
(4)
to
to
to
to
0FFFH
1FFFH
2FFFH
3F7FH
(PC13, 12
(PC13, 12
(PC13, 12
(PC13, 12
=
=
=
=
00B) or
01B) or
10B) or
11B)
Data Memory
Addressing
Program Memory
Addressing
MB indicates accessible memory bank.
In *2, MB = 0 irrespective of MBE and MBS.
In *4 and *5, MB = 15 irrespective of MBE and MBS.
*6 to *10 indicate addressable areas.
Description of the machine cycle column
S indicates the number of machine cycles required for skip operation by an instruction having skip function.
The S value varies as follows:
• When not skipped ...................................................................................................... S = 0
• When 1-byte or 2-byte instructions are skipped .................................................... S = 1
• When 3-byte instructions are skipped (BR !adder, CALL !adder instruction) ... S = 2
Note
GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle (= tCY) of CPU clock Φ and three time periods are available according
to PCC setting.
38
µPD75516
Note 1 Mnemonic
Operands
No. of Machine
Bytes
Cycle
Operation
Addressing
Area
Skip
Condition
A, #n4
1
1
A←n4
Stack A
reg1, #n4
2
2
reg1←n4
XA, #n8
2
2
XA←n8
Stack A
HL, #n8
2
2
HL←n8
Stack B
rp2, #n8
2
2
rp2←n8
A, @HL
1
1
A←(HL)
*1
A, @HL+
1
2+S
A←(HL), then L←L+1
*1
L=0
A, @HL–
1
2+S
A←(HL), then L←L–1
*1
L = FH
A, @rpa1
1
1
A←(rpa1)
*2
XA, @HL
2
2
XA←(HL)
*1
@HL, A
1
1
(HL)←A
*1
@HL, XA
2
2
(HL)←XA
*1
A, mem
2
2
A←(mem)
*3
XA, mem
2
2
XA←(mem)
*3
mem, A
2
2
(mem)←A
*3
mem, XA
2
2
(mem)←XA
*3
A, reg
2
2
A←reg
XA, rp'
2
2
XA←rp'
reg1, A
2
2
reg1←A
rp'1, XA
2
2
rp'1←XA
A, @HL
1
1
A↔(HL)
*1
A, @HL+
1
2+S
A↔(HL), then L←L+1
*1
L=0
A, @HL–
1
2+S
A↔(HL), then L←L–1
*1
L = FH
A, @rpa1
1
1
A↔(rpa1)
*2
XA, @HL
2
2
XA↔(HL)
*1
A, mem
2
2
A↔(mem)
*3
XA, mem
2
2
XA↔(mem)
*3
A, reg1
1
1
A↔reg1
XA, rp'
2
2
XA↔rp'
XA, @PCDE
1
3
XA←(PC13–8+DE)ROM
XA, @PCXA
1
3
XA←(PC13–8+XA)ROM
Transfer
MOV
XCH
Note 2 MOVT
Note
1. Instruction Group
2. Table reference
39
µPD75516
Bit transfer
Note
Mnemonic
No. of Machine
Bytes
Cycle
Operation
Addressing
Area
ADDC
SUBS
CY, fmem.bit
2
2
CY←(fmem.bit)
*4
CY, pmem.@L
2
2
CY←(pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY←(H+mem3–0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)←CY
*4
pmem.@L, CY
2
2
(pmem 7–2+L3–2.bit(L 1–0))←CY
*5
@H+mem.bit, CY
2
2
(H+mem3–0.bit)←CY
*1
A, #n4
1
1+S
A←A+n4
carry
XA, #n8
2
2+S
XA←XA+n8
carry
A, @HL
1
1+S
A←A+(HL)
XA, rp'
2
2+S
XA←XA+rp'
carry
rp'1, XA
2
2+S
rp'1←rp'1+XA
carry
A, @HL
1
1
A, CY←A+(HL)+CY
XA, rp'
2
2
XA, CY←XA+rp'+CY
rp'1, XA
2
2
rp'1, CY←rp'1+XA+CY
A, @HL
1
1+S
A←A–(HL)
XA, rp'
2
2+S
XA←XA–rp'
borrow
rp'1, XA
2
2+S
rp'1←rp'1–XA
borrow
A, @HL
1
1
A, CY←A–(HL)–CY
SUBC
XA, rp'
2
2
XA, CY←XA–rp'–CY
rp'1, XA
2
2
rp'1, CY←rp'1–XA–CY
A, #n4
2
2
A←A n4
A, @HL
1
1
A←A (HL)
XA, rp'
2
2
XA←XA rp'
rp'1, XA
2
2
rp'1←rp'1 XA
A, #n4
2
2
A←A
n4
A, @HL
1
1
A←A
(HL)
XA, rp'
2
2
XA←XA
rp'1, XA
2
2
rp'1←rp'1
A, #n4
2
2
A←A
n4
A, @HL
1
1
A←A
(HL)
XA, rp'
2
2
XA←XA
rp'1, XA
2
2
rp'1←rp'1
*1
*1
*1
*1
*1
OR
rp'
XA
*1
XOR
40
Instruction Group
rp'
XA
carry
*1
AND
Note
Skip
Condition
MOV1
ADDS
Operation
Operand
borrow
µPD75516
Carry flag
manipulation
Compare
Increment/decrement
Note 2
Note 1 Mnemonic
Note
Operands
No. of Machine
Bytes
Cycle
Operation
Addressing
Area
Skip
Condition
RORC
A
1
1
CY←A0, A 3←CY, An–1←An
NOT
A
2
2
A←A
reg
1
1+S
reg←reg+1
reg = 0
rp1
1
1+S
rp1←rp1+1
rp1 = 00H
@HL
2
2+S
(HL)←(HL)+1
*1
(HL) = 0
mem
2
2+S
(mem)←(mem)+1
*3
(mem) = 0
reg
1
1+S
reg←reg–1
reg = FH
rp'
2
2+S
rp'←rp'–1
rp' = FFH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA.rp'
2
2+S
Skip if XA = rp'
XA = rp'
SET1
CY
1
1
CY←1
CLR1
CY
1
1
CY←0
SKT
CY
1
1+S
NOT1
CY
1
1
INCS
DECS
SKE
Skip if CY = 1
CY = 1
CY←CY
1. Instruction Group
2. Accumulator manipulation
41
µPD75516
Note
Mnemonic
SET1
CLR1
Memory bit manipulation
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Operands
No. of Machine
Bytes
Cycle
Operation
Addressing
Area
mem.bit
2
2
(mem.bit)←1
*3
fmem.bit
2
2
(fmem.bit)←1
*4
pmem.@L
2
2
(pmem7–2+L3–2.bit(L1–0))←1
*5
@H + mem.bit
2
2
(H+mem3–0.bit)←1
*1
mem.bit
2
2
(mem.bit)←0
*3
fmem.bit
2
2
(fmem.bit)←0
*4
pmem.@L
2
2
(pmem7–2+L3–2.bit(L1–0))←0
*5
@H+mem.bit
2
2
(H+mem3–0.bit)←0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY←CY (fmem.bit)
*4
CY, pmem.@L
2
2
CY←CY (pmem7–2+L3–2.bit(L 1–0))
*5
CY, @H+mem.bit
2
2
CY←CY (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY←CY (fmem.bit)
*4
CY, pmem.@L
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY←CY (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY←CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY←CY
(pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY←CY
(H+mem3–0.bit)
*1
PC13–0←addr
Branch
BR
Note
42
(Optimum instruction is
selected from among BR !addr,
BRCB !caddr and BR $addr by an
assembler.)
addr
—
—
!addr
3
3
PC13–0←addr
*6
$addr
1
2
PC13–0←addr
*7
!caddr
2
2
PC13–0←PC13,12+caddr11–0
*8
PCDE
2
3
PC13–0←PC13–8+DE
PCXA
2
3
PC13–0←PC13–8+XA
BR
BRCB
Skip
Condition
Instruction Group
*6
µPD75516
Note
Mnemonic
Operands
No. of Machine
Bytes
Cycle
Addressing
Area
Operation
CALL
!addr
3
3
(SP–4) (SP–1) (SP–2)←PC11–0
(SP–3)← MBE, RBE, PC13, 12
PC13–0←addr, SP←SP–4
*6
CALLF
!faddr
2
2
(SP–4) (SP–1) (SP–2)←PC11–0
(SP–3)← MBE, RBE, PC13, 12
PC13–0←00, faddr, SP←SP–4
*9
1
3
Skip
Condition
MBE, RBE, PC13, 12←(SP+1)
PC11–0←(SP) (SP+3) (SP+2)
SP←SP+4
RETS
1
3+S
RETI
1
3
PC13, 12←(SP+1)
PC11–0←(SP) (SP+3) (SP+2)
PSW←(SP+4) (SP+5), SP←SP+6
rp
1
1
(SP–1) (SP–2)←rp, SP←SP–2
BS
2
2
(SP–1)←MBS, (SP–2)←RBS, SP←SP–2
rp
1
1
rp←(SP+1) (SP), SP←SP+2
BS
2
2
MBS←(SP+1), RBS←(SP), SP←SP+2
2
2
IME(IPS.3)←1
2
2
IE×××←1
2
2
IME(IPS.3)←0
IE×××
2
2
IE×××←0
Input/output
MBE, RBE, PC13, 12←(SP+1)
PC11–0←(SP) (SP+3) (SP+2)
SP←SP+4
then skip unconditionally
A, PORTn
2
2
A←PORTn
IN
XA, PORTn
2
2
XA←PORTn+1, PORTn
PORTn, A
2
2
PORTn←A
PORTn, XA
2
2
PORTn+1, PORTn←XA
Special CPU control
Subroutine stack control
RET
HALT
2
2
Set HALT Mode (PCC.2←1)
STOP
2
2
Set STOP Mode (PCC.3←1)
NOP
1
1
No Operation
RBn
2
2
RBS←n
MBn
2
2
MBS←n (n = 0, 1, 15)
Unconditional
PUSH
Interrupt
control
POP
*
EI
IE×××
DI
OUT
*
*
(n = 0 to 15)
(n = 4, 6)
(n = 2 to 7, 9 to 14)
(n = 4, 6)
(n = 0 to 3)
SEL
MBE = 0 or MBE = 1 and MBE = 15 must be set for execution of IN/OUT instruction
Note
Instruction Group
43
µPD75516
Special
Note
*
GETI *
Operands
taddr
No. of Machine
Bytes
Cycle
1
3
Operation
• TBR instruction
PC13–0←(taddr)4–0+(taddr+1)
---------------------------------------------------• TCALL instruction
(SP–4)(SP–1)(SP–2)←PC11–0
(SP–3)← MBE, RBE, PC13, 12
PC13–0←(taddr)5–0+(taddr+1)
SP←SP–4
---------------------------------------------------• (taddr) (taddr+1) instruction
executed in the case of
instruction except TBR and
TCALL instructions
Addressing
Area
Skip
Condition
------------------------
*10
-----------------------Depends on
instructions
referred to.
TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table.
Note
44
Mnemonic
Instruction Group
µPD75516
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
SYMBOL
Power supply voltage
VDD
–0.3 to +7.0
V
VI1
Except ports 4, 5 and 12 to 14
–0.3 to VDD +0.3
V
Ports 4, 5 and 12 to
Internal pull-up resistor
–0.3 to VDD +0.3
V
14
Open-drain
–0.3 to +11
V
–0.3 to VDD +0.3
V
Input voltage
VI2
Output voltage
VO
Output current high
IOH
TEST CONDITIONS
–15
mA
All pins
–30
mA
Peak value
30
mA
Effective value
15
mA
Peak value
100
mA
Effective value
60
mA
Peak value
100
mA
Effective value
60
mA
Peak value
40
mA
Effective value
25
mA
Total of ports 0, 2, 3 and 4
VOL*
Total of ports 5 to 11
Total of ports 12 to 14
*
UNIT
1 pin
1 pin
Output current low
RATING
Operating temperature
Topt
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Calculate the effective value with the formula [Effective value] = [Peak value] × √duty.
OPERATING VOLTAGE
SYMBOL
PARAMETER
A/D converter
Timer/pulse generator
Other circuits
TEST CONDITIONS
MIN.
MAX.
UNIT
Power supply voltage
VDD
3.5
6.0
V
Ambient temperature
Ta
–10
+70
°C
Power supply voltage
VDD
4.5
6.0
V
Ambient temperature
Ta
–40
+85
°C
Power supply voltage
VDD
2.7
6.0
V
Ambient temperature
Ta
–40
+85
°C
TYP.
MAX.
UNIT
15
pF
15
pF
15
pF
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
SYMBOL
Input capacitance
CI
Output capacitance
CO
Input /output
capacitance
CIO
TEST CONDITIONS
f = 1 MHz
Unmeasured pin returned to 0 V
MIN.
45
µPD75516
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
X1
X2
Ceramic
resonator
C1
C2
X1
Crystal
resonator
PARAMETER
TEST CONDITIONS
Oscillator frequency
(fX) *1
VDD = Oscillation
voltage range
Oscillation stabilization
time *2
After VDD reaches the
minimum value in the
oscillation voltage
range
Oscillator frequency
(fX) *1
X2
MIN.
TYP.
1.0
1.0
4.19
VDD = 4.5 to 6.0 V
C1
C2
X1
X2
External
clock
µPD74HCU04
Oscillation stabilization
time *2
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
X1 input frequency
(fX) *1
1.0
5.0*3
MHz
X1 high and low level
widths (tXH, tXL)
100
500
ns
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
XT1
R
C3
C4
XT1
External
clock
TEST CONDITIONS
Oscillator frequency
(f XT) *1
XT2
Crystal
resonator
PARAMETER
XT2
MIN.
TYP.
MAX.
UNIT
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 6.0 V
Oscillation stabilization
time *2
XT1 input frequency
(f XT) *1
32
100
kHz
XT1 high and low level
widths (tXTH, tXTL)
5
15
µs
Leave Open
* 1.
Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction
execution time.
2. Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or
after STOP mode release.
3.
46
When the oscillator frequency is 4.19 MHz < fX ≤ 5.0 MHz, PPC = 0011 should not be selected as the instruction
execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 µs, and the specification MIN.
value of 0.95 µs will not be achieved.
µPD75516
Note
★
When the system clock oscillator is used, the following points should be noted concerning wiring in
the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc.
• Keep the wiring as short as possible.
• Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows.
• Ensure that oscillator capacitor connection points are always at the same potential as VDD. Do not
connect in a power supply pattern in which a high current flows.
• Do not take a signal from the oscillator.
The subsystem clock oscillator is designed to be a circuit with the low amplification factor to achieve
low consumption current, with the result that it is more prone to misoperation due to noise than the
main system clock oscillator. Therefore, when using the subsystem clock, special care is required for
the wiring method.
RECOMMENDED OSCILLATOR CONSTANTS
MAIN SYSTEM CLOCK : CERAMIC RESONATOR (Ta = –40 to +85 °C)
MANUFACTURER
Kyocera Corp.
PRODUCT NAME
EXTERNAL
CAPACITANCE (pF)
OSCILLATION
VOLTAGE RANGE (V)
C1
C2
MIN.
MAX.
KBR–1000H
100
100
KBR–2.0MS
47
47
2.7
6.0
KBR–4.0MS
33
33
30
30
2.7
30
30
3.0
REMARKS
CSA 2.00MG
CSA 4.00MGU
CSA 4.19MG093
CSA 4.91MGU
Murata Mfg. Co., Ltd.
CSA 4.91MG
6.0
CST 2.00MG
CST 4.00MGU
CST 4.19MG093
On-chip
On-chip
2.7
On-chip
On-chip
3.0
27
27
3.0
CST 4.91MGU
CST 4.91MG
CRHF 3.00
Toko, Inc.
CRHF 4.19
6.0
MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = –20 to +70 °C)
MANUFACTURER
Kinseki
PRODUCT NAME
HC–49/U
EXTERNAL
CAPACITANCE (pF)
OSCILLATION
VOLTAGE RANGE (V)
C1
C2
MIN.
MAX.
27
27
2.7
6.0
REMARKS
47
µPD75516
DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
Output voltage high
MAX.
UNIT
Ports 2, 3, 9 to 11, P80, P82
0.7 V DD
VDD
V
VIH2
Ports 0, 1, 6, 7, 15, P81, P83, RESET
0.8 V DD
VDD
V
Internal pull-up resistor
0.7 V DD
VDD
V
VIH3
Port 4, 5, 12 to 14
Open-drain
0.7 V DD
10
V
VDD–0.5
VDD
V
VIH4
X1, X2, XT1
VIL1
Ports 2 to 5, 9 to 14, P80, P82
0
0.3 VDD
V
VIL2
Ports 0, 1, 6, 7, 15, P81, P83, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH
VDD = 4.5 to 6.0 V, IOH = –1 mA
VDD–1.0
V
IOH = 100 µA
VDD–0.5
V
Ports 3, 4, 5
Output voltage low
TYP.
VIH1
Input voltage high
Input Voltage low
MIN.
VOL
VDD = 4.5 to 6.0V, IOL = 15 mA
2.0
V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
0.2 V DD
V
3
µA
X1, X2, XT1
20
µA
Ports 4, 5, 12 to 14
(when open-drain)
20
µA
Except below
–3
µA
X1, X2, XT1
–20
µA
3
µA
20
µA
–3
µA
80
kΩ
300
kΩ
70
kΩ
60
kΩ
140
kΩ
SB0, 1
0.4
Open-drain pull-up
resistance ≥ 1k Ω
Except below
ILIH1
VI = VDD
Input leakage current
high
ILIH2
ILIH3
Input leakage current
low
Output leakage current
high
Output leakage current
low
VI = 9 V
ILIL1
VI = 0 V
ILIL2
ILOH1
VO = VDD
Except below
ILOH2
VO = 9 V
Ports 4, 5, 12 to 14
(when open-drain)
ILOL
VO = 0 V
RU1
Ports 0, 1, 2, 3,
6, 7 (except P00)
VI = 0 V
VDD = 5.0 V ±10%
15
VDD = 3.0 V ± 10%
30
Ports 4, 5, 12
to 14
VO = VDD –2.0 V
VDD = 5.0 V ± 10%
15
VDD = 3.0 V ± 10%
10
VO = 2 V
Port 9
20
Internal pull-up resistor
RU2
Internal pull-down
resistor
48
RD
40
40
70
µPD75516
DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
IDD1
IDD2
Supply current *1
TEST CONDITIONS
TYP.
MAX.
UNIT
3
9
mA
0.55
1.5
mA
600
1800
µA
200
600
µA
VDD = 3 V ± 10%
40
120
µA
HALT mode VDD = 3 V ± 10%
5
15
µA
0.5
20
µA
0.3
10
µA
5
µA
VDD = 5 V ± 10% *3
Operating
4.19 MHz crystal mode
VDD = 3 V ± 10% *4
oscillation
C1 = C2 = 22 pF
VDD = 5 V ± 10%
*2
HALT mode
VDD = 3 V ± 10%
IDD3
32.768 kHz
crystal
IDD4
oscillation *5
IDD5
XT1 = 0 V
STOP mode
Operating
mode
VDD = 5 V ± 10%
* 1.
2.
3.
4.
5.
VDD = 3 V
± 10%
Ta = 25 °C
MIN.
Current flowing to the internal pull-up resistor excluded.
Subsystem clock oscillation also included.
When operated in the high speed mode with the processor clock control register (PCC) set to 0011.
When operated in the low speed mode with PCC = 0000.
When operated on the subsystem clock after the main system clock oscillation stop with the system clock
control register (SCC) set to 1001.
49
µPD75516
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)
(1)
Basic Operation
PARAMETER
SYMBOL
CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle )*1
tCY
TI0 input frequency
fTI
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
Operation with main
system clock
Operation with subsystem clock
MAX.
UNIT
0.95
64
µs
3.8
64
µs
125
µs
0
1
MHZ
0
275
kHz
114
VDD = 4.5 to 6.0 V
TI0 input high and lowlevel widths
tTIH,
Interrupt input high and
low-level widths
tINTH,
RESET low-level width
* 1.
122
0.48
µs
1.8
µs
INT0
*2
µs
INT1, 2, 4
10
µs
KR0–7
10
µs
10
µs
VDD = 4.5 to 6.0 V
tTIL
tINTL
tRSL
The CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator,
the system clock control register (SCC) and the
tCY
64
60
6
5
Operation Guaranteed
Range
4
Cycle Time tCY [µs]
2tCY or 128/fX is set by interrupt mode register (IM0)
setting.
VS VDD
(Main System Clock in Operation)
70
processor clock control register (PCC). The cycle
time tCY characteristics for power supply voltage
VDD when the main system clock is in operation is
shown below.
2.
TYP.
3
2
1
0.5
0
1
2
3
4
5
Power Supply Voltage VDD [V]
50
6
µPD75516
(2)
Serial Transfer Operation
(a)
2-wire and 3-wire serial I/O mode (SCK...Internal clock output)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
(tKCY1/2)–50
ns
tKCY1
tKL1
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH1
(tKCY1/2)–150
ns
SI setup time (to SCK↑)
tSIK1
150
ns
SI hold time (from SCK↑)
tKSI1
400
ns
SO output delay time
from SCK↓
tKSO1
*
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
ns
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
(b)
2-wire and 3-wire serial I/O mode (SCK...External clock input)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
*
250
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY2
tKL2
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH2
1600
ns
SI setup time (to SCK↑)
tSIK2
100
ns
SI hold time (from SCK↑)
tKSI2
400
ns
SO output delay time
from SCK↓
tKSO2
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
300
ns
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
51
µPD75516
(c)
SBI mode (SCK...Internal clock output (master))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY3/2–50
ns
tKCY3
tKL3
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH3
t KCY3/2–150
ns
SB0 and SB1 setup time (to SCK↑)
tSIK3
150
ns
SB0 and SB1 hold time (from SCK↑)
tKSI3
tKCY3/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO3
SB0, SB1↓ from SCK↑
tKSB
tKCY3
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0 and SB1 low-level widths
tSBL
tKCY3
ns
SB0 and SB1 high-level widths
tSBH
tKCY3
ns
*
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
0
250
ns
0
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
(d)
SBI mode (SCK...External clock input (slave))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY4
tKL4
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH4
1600
ns
SB0 and SB1 setup time (to SCK↑)
tSIK4
100
ns
SB0 and SB1 hold time (from SCK↑)
tKSI4
tKCY4/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO4
SB0, SB1↓ from SCK↑
tKSB
tKCY4
ns
SCK↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0 and SB1 low-level widths
tSBL
tKCY4
ns
SB0 and SB1 high-level widths
tSBH
tKCY4
ns
*
52
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
RL and CL are SO output line load resistance and load capacitance, respectively.
0
300
ns
0
1000
ns
µPD75516
(3)
A/D Converter (Ta = –10 to +70 °C, V DD = 3.5 to 6.0 V, AVSS = VSS = 0V)
PARAMETER
SYMBOL
TEST CONDITIONS
Resolution
MIN.
TYP.
MAX.
UNIT
8
8
8
bit
±1.5
LSB
2.5 V ≤ AVREF ≤ VDD*2
Absolute accuracy*1
Conversion time*3
tCONV
168/fX
µs
Sampling time*4
tSAMP
44/fX
µs
Analog input voltage
VIAN
AVREF
V
Analog input impedance
RAN
1000
AVREF current
IREF
1.0
* 1.
2.
AVSS
MΩ
2.0
mA
Absolute accuracy with the quantization error (±1/2 LSB) excluded.
ADM1 is set as shown below with regard to the A/D converter reference voltage (AVREF).
2.5 V
0.6 V DD
0.65 VDD
VDD (3.5 to 6.0V)
AVREF
ADM1 = 0
ADM1 = 1
3.
When 0.6 VDD ≤ AVREF ≤ 0.65 VDD, the ADM1 can be set either to 0 or 1.
This is the time form the execution of the conversion start instruction to the conversion end (EOC = 1)
(operating at 40.1 µs : fX = 4.19 MHz).
4. This is the time from the execution of the conversion start instruction to the sampling end (operating at 10.5
µs : fX = 4.19 MHz).
53
µPD75516
AC Timing Test Points (Except X1 and XT1 Inputs)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
X1 Input
V DD - 0.5 V
0.4 V
1/fXT
tXTL
tXTH
XT1 Input
VDD - 0.5 V
0.4 V
TI0 Timing
1/fTI
tTIL
TI0
54
tTIH
µPD75516
Serial Transfer Timing
3-wire serial I/O mode:
tKCY1
tKH1
tKL1
SCK
tSIK1
SI
tKSI1
Input Data
tKSO1
SO
Output Data
2-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
tKSO2
tKSI2
SB0,1
55
µPD75516
Serial Transfer Timing
Bus release signal transfer:
tKCY3,4
tKL3,4
tKH3,4
SCK
tSBL
tKSB
tSBH
tSIK3,4
tSBK
SB0,1
tKSO3,4
Command signal transfer:
tKCY3,4
tKL3,4
tKH3,4
SCK
tKSB
tSIK3,4
tSBK
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
INT0,1,2,4
KR0-7
RESET Input Timing
tRSL
RESET
56
tINTH
tKSI3,4
tKSI3,4
µPD75516
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40
to +85 °C)
PARAMETER
SYMBOL
Data retention power supply voltage
VDDDR
Data retention power supply current *1
IDDDR
Release signal set time
tSREL
3.
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.1
MAX.
UNIT
6.0
V
10
µA
µs
0
Release by RESET
Oscillation stabilization wait
time *2
* 1.
2.
TEST CONDITIONS
17
2 /fX
ms
*3
ms
tWAIT
Release by interrupt request
Current to the internal pull-up resistor is not included.
Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
According to the setting of the basic interval timer mode register (BTM) (see below).
Wait Time
BTM3
BTM2
BTM1
BTM0
(Values at fX = 4.19 MHz in parentheses)
—
0
0
0
220/fX (approx. 250 ms)
—
0
1
1
217/fX (approx. 31.3 ms)
—
1
0
1
215/fX (approx. 7.82 ms)
—
1
1
1
213/fX (approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
57
µPD75516
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
58
µPD75516
12. CHARACTERISTIC CURVES
IDD vs VDD (Main System Clock : Crystal Oscillation)
(Ta=25 °C)
5000
High-Speed Mode
PCC=0011
Medium-Speed Mode
PCC=0010
Low-Speed Mode
PCC=0000
1000
Main System Clock
HALT Mode
Power Supply Current IDD [µA]
500
Subsystem Clock
Operating Mode
100
Main System Clock
STOP Mode + 32 kHz
Oscillation and
Subsystem Clock
HALT Mode
50
10
X1
X2 XT1
Crystal
Resonator
4.19 MHz
5
C1
C2
XT2
Crystal
Resonator
32.768 kHz
R
C3
C4
1
0
1
2
3
4
5
6
7
Power Supply Voltage VDD [V]
59
µPD75516
IDD vs VDD (Main System Clock : Crystal Oscillation)
(Ta=25 °C)
5000
High-Speed Mode
PCC=0011
Medium-Speed Mode
PCC=0010
Low-Speed Mode
PCC=0000
1000
Main System Clock
HALT Mode*
Power Supply Current IDD [µA]
500
Subsystem Clock
Operating Mode
100
Main System Clock
STOP Mode + 32 kHz
Oscillation and
Subsystem Clock
HALT Mode
50
10
X1
X2 XT1
Ceramic
Oscillator
4.19 MHz
5
C1
C2
XT2
Crystal
Resonator
32.768 kHz
R
C3
C4
1
0
1
2
3
4
Power Supply Voltage VDD [V]
*
60
This is larger than the crystal oscillation by about 10%.
5
6
7
µPD75516
I
IDD vs VDD (Main System Clock : Crystal Oscillation)
(Ta=25 °C)
5000
High-Speed Mode
PCC=0011
Medium-Speed Mode
PCC=0010
Low-Speed Mode
PCC=0000
1000
Main System Clock
HALT Mode
Power Supply Current IDD [µA]
500
Subsystem Clock
Operating Mode
100
Main System Clock
STOP Mode + 32 kHz
Oscillation and
Subsystem Clock
HALT Mode
50
10
X1
X2 XT1
Ceramic
Oscillator
2.0 MHz
5
C1
C2
XT2
Crystal
Resonator
32.768 kHz
R
C3
C4
1
0
1
2
3
4
5
6
7
Power Supply Voltage VDD [V]
61
µPD75516
IDD vs VDD (Main System Clock : Crystal Oscillation)
(Ta=25 °C)
5000
High-Speed Mode
PCC=0011
Medium-Speed Mode
PCC=0010
Low-Speed Mode
PCC=0000
1000
Main System Clock
HALT Mode
Power Supply Current IDD [µA]
500
Subsystem Clock
Operating Mode
100
Main System Clock
STOP Mode + 32 kHz
Oscillation and
Subsystem Clock
HALT Mode
50
10
X1
X2 XT1
Ceramic
Oscillator
1.0 MHz
5
C1
C2
XT2
Crystal
Resonator
32.768 kHz
R
C3
C4
1
0
1
2
3
4
Power Supply Voltage VDD [V]
62
5
6
7
µPD75516
IDD VS fX (VDD = 5V, Ta = 25°C)
3
X1
X2
IDD VS fX (VDD = 3V, Ta = 25°C)
0.5
2
High-Speed Mode
PCC = 0011
Medium-Speed
Mode
PCC = 0010
IDD
[mA]
0.4
High-Speed
Mode
PCC =
0011
MediumSpeed Mode
PCC =
0010
X1
X2
0.3
Low-Speed Mode
PCC = 0000
IDD
[mA]
1
Low-Speed Mode
PCC = 0000
0.2
Main System Clock
HALT Mode
0.1
Main System Clock
HALT Mode
0
0
1
2
3
4
1
5
2
3
VOL VS IOL (Port 0, 2, 6, 7)
5
VOL VS IOL (Port 3, 4 ,5)
(Ta = 25°C)
(Ta = 25°C)
40
30
4
fX [MHz]
fX [MHz]
40
VDD = 6 V
30
VDD = 4 V
VDD = 5 V
VDD = 5 V
VDD =
6V
VDD = 4 V
IOL
[mA]
IOL
[mA]
20
20
VDD = 3 V
VDD = 3 V
VDD = 2.7 V
VDD = 2.7 V
10
10
0
0
1
2
3
VOL [V]
4
5
1
2
3
4
5
VOL [V]
63
µPD75516
VOH VS IOH
(Ta = 25°C)
20
15
VDD = 6 V
VDD = 5 V
IOH
[mA]
VDD = 4 V
10
VDD = 3 V
5
VDD = 2.7 V
0
1
2
3
VDD – VOH [V]
64
4
5
µPD75516
13. PACKAGE INFORMATION
80 PIN PLASTIC QFP (14×20)
A
B
41
40
64
65
F
Q
5°±5°
S
D
C
detail of lead end
25
24
80
1
G
H
I M
J
M
P
K
N
L
P80GF-80-3B9-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
0.8
0.031
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 –0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.15
0.006
P
2.7
Q
0.1 ± 0.1
S
3.0 MAX.
+0.008
0.106
0.004 ± 0.004
0.119 MAX.
65
µPD75516
★
14. RECOMMEDED SOLDERING CONDITIONS
The µPD75516 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions for the surface mounting type, refer to the document
“Semiconductor Device Mount Technology” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 4–1 Surface Mount Type Soldering Conditions
µPD75516GF–×××–3B9: 80–pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230 °C
Duration: 30 sec. max. (at 210 °C or above)
Number of times: Once
IR30-00-1
VPS
Package peak temperature: 215 °C
Duration: 40 sec. max. (at 200 °C or above)
Number of times: Once
VP15-00-1
Wave Soldering
Solder bath temperature: 260 °C or less
Duration: 10 sec. max.
Number of times: Once
Preheating temperature: 120 °C max. (package surface temperature)
WS60-00-1
Pin part heating
Pin part temperature: 300 °C or less
Duration: 3 sec. max. (Per device side)
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
For Your Information
Products to improve the recommended soldering conditions are available.
(Improvements: Extension of the infrared reflow peak temperature to 235oC,
doubled frequency, increased life, etc.)
For further details, consult our sales personnel.
-
66
µPD75516
APPENDIX A. DEVELOPMENT TOOLS
Hardware
The following development tools are available for the development of systems using the µPD75516.
IE–75000–R *1
IE–75001–R
In–circuit emulator for use with the 75X series
IE–75000–R–EM *2
Emulation board for use with the IE–75000–R and the IE–75001–R
EP–75516GF–R
Emulation probe for use with the µPD75516.
80–pin conversion socket EV–9200G–80 included
EV–9200G–80
PG–1500
PROM programmer
PA–75P516GF
Connect to PG–1500 with PROM programmer adapter for use with the µPD75P516GF
Software
IE control program
PG–1500 controller
Host machine
PC–9800 series (MS–DOS™ Ver. 3.30 to Ver. 5.00A *3)
IBM PC/AT™ (PC DOS™ Ver. 3.1)
RA75X relocatable assembler
*
1. Maintenance product
2. Not a built–in component in the IE–75001–R
3. Ver. 5.00/5.00A has a task swapping function, which cannot be used with this software.
Remarks
Refer to the "75X Series Selection Guide" (IF–151) for third–party development tools.
67
µPD75516
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User's Manual
IEM–5049
Instruction Application Table
IEM–5036
Basic Volume
IEM–5104
Application Note
A/D Converter Volume
IEA–630
75X Series Selection Guide
IF–151
Development Tools Documents
Hardware
Document Name
Software
★
Document Number
IE–75000–R/IE–75000–R User's Manual
EEU–846
IE–75000–R–EM User's Manual
EEU–673
EP–75516GF–R User's Manual
EEU–703
PG–1500 User's Manual
EEU–651
Operation Volume
EEU–731
Language Volume
EEU–730
RA75X Assembler Package User's Manual
PG–1500 Controller User's Manual
EEU–704
Other Documents
Document Name
Package Manual
IEI–635
Surface Mount Technology Manual
IEI–1207
Quality Grade on NEC Semiconductor Devices
IEI–1209
NEC Semiconductor Device Reliability & Quality Control
IEM–5068
Electrostatic Discharge (ESD) Test
MEM–539
Semiconductor Device Quality Guide Guarantee Guide
MEI–603
Microcomputer Related Products Guide
– Other Manufacturers Volume
MEI–604
Note
68
Document Number
The information in these related documents is subject to change without notice. For design purpose, etc.,
be sure to use the latest ones.
µPD75516
69
µPD75516
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Special
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.