NSC 54ABT574W/883

54ABT574
Octal D-Type Flip-Flop with TRI-STATE ® Outputs
General Description
The ’ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE). The
information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ’ABT374 except for
the pinouts.
Features
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’ABT374
n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF
loads
n Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9322001
Ordering Code
Military
Package Number
Package Description
54ABT574J/883
J20A
20-Lead Ceramic Dual-In-Line
54ABT574W/883
W20A
20-Lead Cerpack
54ABT574E/883
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment for DIP and Flatpak
Pin Assignment
for LCC
DS100208-1
DS100208-2
Pin Descriptions
Pin
Description
Names
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
TRI-STATE Output Enable
O0–O7
TRI-STATE Outputs
(Active Rising Edge)
Input (Active LOW)
FAST ® and TRI-STATE ® are registered trademarks of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100208
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54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
July 1998
Functional Description
Inputs
The ’ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Inputs
Internal Outputs
CP
D
Q
O
H
H or L
L
NC
Z
Function
CP
D
Q
O
H
H or L
H
NC
Z
Hold
H
N
L
L
Z
Load
H
N
H
H
Z
Load
L
N
L
L
L
Data Available
L
N
H
H
H
Data Available
L
H or L
L
NC
NC
No Change in Data
L
H or L
H
NC
NC
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
Function Table
OE
Internal Outputs
OE
Function
Hold
Logic Diagram
DS100208-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
Over Voltage Latchup (I/O)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output in
the Disabled or Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
10V
Recommended Operating
Conditions
−65˚C to +150˚C
−55˚C to +125˚C
Free Air Ambient Temperature
Military
Supply Voltage
Military
Minimum Input Edge Rate
Data Input
Enable Input
Clock Input
−55˚C to +175˚C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to 5.5V
−0.5V to VCC
−55˚C to +125˚C
+4.5V to +5.5V
(∆V/∆t)
50 mV/ns
20 mV/ns
100 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
−500 mA
DC Electrical Characteristics
Symbol
Parameter
ABT574
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
Units
VCC
2.0
V
0.8
V
−1.2
V
Recognized HIGH Signal
Min
54ABT
2.5
V
Min
54ABT
2.0
V
Min
54ABT
0.55
V
Min
5
µA
Max
5
IBVI
Input HIGH Current Breakdown Test
7
µA
Max
IIL
Input LOW Current
−5
µA
Max
V
0.0
−5
VID
Input Leakage Test
Conditions
Typ Max
4.75
Recognized LOW Signal
IIN = −18 mA
IOH = −3 mA
IOH = −24 mA
IOL = 48 mA
VIN = 2.7V (Note 4)
VIN = VCC
VIN = 7.0V
VIN = 0.5V (Note 4)
VIN = 0.0V
IID = 1.9 µA
All Other Pins Grounded
VOUT = 2.7V; OE = 2.0V
IOZH
Output Leakage Current
50
µA
0 − 5.5V
IOZL
Output Leakage Current
−50
µA
0 − 5.5V
IOS
Output Short-Circuit Current
−275
mA
Max
ICEX
Output High Leakage Current
50
µA
Max
IZZ
Bus Drainage Test
100
µA
0.0
VOUT = 0.5V; OE = 2.0V
VOUT = 0.0V
VOUT = VCC
VOUT = 5.5V; All Other GND
ICCH
Power Supply Current
50
µA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
ICCZ
Power Supply Current
50
µA
Max
All Outputs LOW
OE = VCC
ICCT
Additional ICC/Input
Outputs Enabled
2.5
mA
Outputs TRI-STATE
2.5
mA
Outputs TRI-STATE
2.5
mA
ICCD
Dynamic ICC
−100
No Load
mA/
(Note 4)
0.30 MHz
All Others at VCC or GND
VI = VCC − 2.1V
Max
Max
Enable Input VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open, OE = GND,
One Bit Toggling (Note 3),
50% Duty Cycle
Note 3: For 8-bit toggling, ICCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3
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AC Electrical Characteristics
Symbol
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Parameter
Units
CL = 50 pF
Min
Max
fmax
Max Clock Frequency
150
tPLH
Propagation Delay
1.5
7.0
tPHL
CP to On
1.5
7.4
tPZH
Output Enable Time
tPZL
tPHZ
Output Disable Time
tPLZ
MHz
1.0
6.5
1.0
7.2
1.0
7.2
1.0
6.7
ns
ns
ns
AC Operating Requirements
Symbol
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Parameter
Units
CL = 50 pF
Min
ts(H)
Setup Time, HIGH
1.5
ts(L)
or LOW Dn to CP
2.0
th(H)
Hold Time, HIGH
2.0
th(L)
or LOW Dn to CP
2.0
tw(H)
Pulse Width, CP,
3.3
tw(L)
HIGH or LOW
3.3
Max
ns
ns
ns
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
5.0
pF
COUT (Note 5)
Output Capacitance
9.0
pF
Conditions
TA = 25˚C
VCC = 0V
VCC = 5.0V
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
TPHL vs Temperature (TA) CL = 50 pF,
1 Output Switching, Clock to Output
TPLH vs Temperature (TA) CL = 50 pF,
1 Output Switching, Clock to Output
DS100208-12
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DS100208-13
4
Capacitance
(Continued)
TPZH vs Temperature (TA) CL = 50 pF,
1 Output Switching, OE to Output
TPZL vs Temperature (TA) CL = 50 pF,
1 Output Switching, OE to Output
DS100208-14
DS100208-15
TPHZ vs Temperature (TA) CL = 50 pF,
1 Output Switching, OE to Output
TPLZ vs Temperature (TA) CL = 50 pF,
1 Output Switching, OE to Output
DS100208-16
DS100208-17
TSET LOW vs Temperature (TA) CL = 50 pF,
1 Output Switching, Data to Clock
TSET vs Temperature (TA) CL = 50 pF,
1 Output Switching, Data to Clock
DS100208-18
DS100208-19
THOLD HIGH vs Temperature (TA) CL = 50 pF,
1 Output Switching, Data to Clock
THOLD LOW vs Temperature (TA) CL = 50 pF,
1 Output Switching, Data to Clock
DS100208-20
DS100208-21
5
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Capacitance
(Continued)
TPLH vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, Clock to Output
TPHL vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, Clock to Output
DS100208-22
DS100208-23
TPZH vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, OE to Output
TPZL vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, OE to Output
DS100208-24
DS100208-25
TPHZ vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, OE to Output
TPLZ vs Temperature (TA) CL = 50 pF,
8 Outputs Switching, OE to Output
DS100208-26
DS100208-27
TPLH vs Load Capacitance TA = 25˚C,
1 Output Switching, Clock to Output
TPHL vs Load Capacitance TA = 25˚C,
1 Output Switching, Clock to Output
DS100208-28
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DS100208-29
6
Capacitance
(Continued)
TPLH vs Load Capacitance TA = 25˚C,
8 Outputs Switching, Clock to Output
TPHL vs Load Capacitance TA = 25˚C,
8 Outputs Switching, Clock to Output
DS100208-30
DS100208-31
TPZH vs Load Capacitance TA = 25˚C,
8 Outputs Switching, OE to Output
TPZL vs Load Capacitance TA = 25˚C,
8 Outputs Switching, OE to Output
DS100208-32
DS100208-33
TPLH and TPHL vs Number Outputs Switching
CL = 50 pF, TA = 25˚C, VCC = 5.0V,
Outputs In Phase, Clock to Output
Typical ICC vs Output Switching Frequency
CL = 0 pF, VCC = VIH = 5.5V,
1 Output Switching at 50% Duty Cycle
DS100208-34
DS100208-35
7
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AC Loading
DS100208-4
DS100208-6
*Includes jig and probe capacitance
FIGURE 2. VM = 1.5V
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100208-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100208-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100208-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100208-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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8
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
9
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54ABT574 Octal D-Type Flip-Flop with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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