SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
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54ACT11821 . . . JT PACKAGE
74ACT11821 . . . DW PACKAGE
Inputs Are TTL-Voltage Compatible
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
(TOP VIEW)
1Q
2Q
3Q
4Q
5Q
GND
GND
GND
GND
6Q
7Q
8Q
9Q
10Q
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
OE
1D
2D
3D
4D
5D
VCC
VCC
6D
7D
8D
9D
10D
CLK
54ACT11821 . . . FK PACKAGE
3D
4D
5D
VCC
VCC
6D
7D
(TOP VIEW)
On the positive transition of the clock the Q outputs
will follow the D inputs.
2D
1D
OE
1Q
2Q
3Q
4Q
A buffered output enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low level) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly.
5
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
5Q
GND
GND
GND
GND
6Q
7Q
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
8D
9D
10
CLK
10Q
9Q
8Q
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The 54ACT11821 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT11821 is characterized for operation form − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!" #$%&'() %$)*!)" !)+$,'*!$) %&,,() *" $+ -&./!%*!$) #*(0 ,$#&%" %$)+$,' $
"-(%!+!%*!$)" -(, ( (,'" $+ (1*" )",&'()" "*)#*,# 2*,,*)30
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2−1
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
L
H
X
Q0
L
↓
X
H
X
X
X0
Z
logic symbol†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
28
15
27
26
logic diagram (positive logic)
EN
OE
C1
1D
1
2
25
3
24
4
23
5
20
10
19
11
18
12
17
13
16
14
CLK
28
15
1Q
2Q
1D
27
C1
1D
1
26
C1
1D
2
25
C1
1D
3
24
C1
1D
4
23
C1
1D
5
20
C1
1D
10
19
C1
1D
11
18
C1
1D
12
17
C1
1D
13
16
C1
1D
14
3Q
4Q
5Q
2D
2Q
6Q
7Q
8Q
3D
3Q
9Q
10Q
4D
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
6D
7D
8D
9D
10D
Pin numbers shown are for the DW, JT, and NT packages.
2−2
1Q
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4Q
5Q
6Q
7Q
8Q
9Q
10Q
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
54ACT11821
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t /∆v
Low-level output current
High-level input voltage
74ACT11821
MIN
2
2
0.8
High-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
VCC
VCC
0
0
V
24
24
mA
0
10
10
ns / V
−55
125
85
°C
−40
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2−3
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 µA
A
VOH
IOH = − 24 mA
IOH = − 50 mA†
IOH = − 75 mA†
54ACT11821
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MIN
MAX
MIN
MAX
UNIT
V
3.85
5.5 V
IOL = 24 mA
74ACT11821
MIN
5.5 V
IOL = 50 µA
A
VOL
TA = 25°C
TYP
MAX
VCC
3.85
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA†
IOL = 75 mA†
5.5 V
II
IOZ
VI = VCC or GND
VO = VCC or GND
5.5 V
±0.1
±1
±1
µA
5.5 V
±0.5
±10
±5
µA
ICC
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
8
160
80
µA
5.5 V
0.9
1
1
mA
∆ICC‡
Ci
1.65
5.5 V
VI = VCC or GND
VO = VCC or GND
1.65
5V
4.5
pF
Co
5V
12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
0
74ACT11821
MIN
MAX
MIN
MAX
0
125
0
125
UNIT
fclock
tw
Clock frequency
4
4
4
ns
tsu
th
Setup time, data before CLK↑
2.5
2.5
2.5
ns
Hold time, data after CLK↑
1.5
1.5
1.5
ns
Pulse duration, CLK high or low
125
54ACT11821
MHz
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
125
CLK
Any Q
OE
Any Q
OE
Any Q
•
MAX
125
74ACT11821
MIN
MAX
125
UNIT
MHz
7.6
10.4
4.7
12.6
4.7
11.7
5
8.1
11
5
12.9
5
12.1
3.1
6.1
9.1
3.1
10.8
3.1
10
4.1
7.6
11
4.1
13.2
4.1
12.3
4.8
7.2
9.2
4.8
10.6
4.8
10.1
4.8
6.8
8.6
4.8
9.8
4.8
9.4
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MIN
4.7
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%*)4( $, #!"%$)!)&( ("( -,$#&%" 2!$& )$!%(0
2−4
54ACT11821
ns
ns
ns
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
Outputs enabled
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
UNIT
45
CL = 50 pF,
f = 1 MHz
pF
31
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
3V
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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2−5
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
2−6
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