CYStech Electronics Corp. High Voltage NPN Power Transistor BVCEO IC RCESAT TIP50J3 Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 1/7 400V 1.5A 500mΩ(max.) Features • High breakdown voltage, VCEO=400V (min.) • High collector current, IC(max)=1.5A (DC) • Pb-free lead plating and halogen-free package Symbol Outline TIP50J3 TO-252(DPAK) B：Base C：Collector E：Emitter B C E Ordering Information Device TIP50J3-0-T3-G Package TO-252 (Pb-free lead plating and halogen-free package) Shipping 2500 pcs / Tape & Reel Environment friendly grade : S for RoHS compliant products, G for RoHS compliant and green compound products Packing spec, T3:2500 pcs/tape & reel, 13” reel Product rank, zero for no rank products Product name TIP50J3 CYStek Product Specification Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 2/7 CYStech Electronics Corp. Absolute Maximum Ratings (Ta=25°C) Parameter Collector-Base Voltage Collector-Emitter Voltage Emitter-Base Voltage Collector Current (DC) Collector Current (Pulse) Base Current (DC) Base Current (Pulse) Power Dissipation @ TA=25°C Power Dissipation @ TC=25°C Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case Operating Junction Temperature Range Storage Temperature Range Symbol VCBO VCEO VEBO IC ICM IB IBM PD RθJA RθJC Tj Tstg Limits 700 400 9 1.5 3 (Note 1) 0.5 1.5 (Note 1) 1.56 (Note 2) 15 80 (Note 2) 8.33 -55~+150 -65~+150 Unit V A W °C/W °C °C Note : 1. Pulse test, PW ≤ 5ms. 2. When the device is mounted on a FR-4 PCB with minimum pad size recommended. Characteristics (Ta=25°C) Symbol BVCBO BVCEO BVEBO ICBO IEBO *VCE(SAT) *VCE(SAT) *VCE(SAT) *RCE(SAT) *VBE(SAT) *VBE(ON) *hFE 1 *hFE 2 fT Cob ton tstg tf Min. 700 400 9 50 10 10 - Typ. 21 1.1 - Max. 10 10 0.3 0.5 0.8 0.5 1.2 1.2 100 4 0.7 Unit V V V μA μA V V V Ω V V MHz pF μs Test Conditions IC=100μA IC=10mA IE=100μA VCB=700V, IE=0 VEB=9V, IC=0 IC=500mA, IB=100mA IC=1 A, IB=200mA IC=1.5 A, IB=500mA IC=1 A, IB=200mA IC=1 A, IB=200mA VCE=10V, IC=1A VCE=10V, IC=300mA VCE=10V, IC=1A VCE=10V, IC=100mA, f=100MHz VCB=10V, IE=0A, f=1MHz VCC=125V, RL=125Ω,IC=1A, IB1=-IB2=0.2A *Pulse Test: Pulse Width ≤380μs, Duty Cycle≤2% TIP50J3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 3/7 Typical Characteristics Current Gain vs Collector Current Saturation Voltage vs Collector Current 100 1000 VCESAT Saturation Voltage-(mV) Current Gain---HFE VCE=5V VCE=2V 10 IC=4IB 100 VCE=1V HFE IC=3IB 1 10 1 10 100 1000 Collector Current ---IC(mA) 10000 1 10 100 1000 Collector Current ---IC(mA) Saturation Voltage vs Collector Current On Voltage vs Collector Current VBEON@VCE=2V On Voltage-(mV) Saturation Voltage-(mV) VBESAT@IC=4IB 1000 100 1000 100 1 10 100 1000 Collector Current--- IC(mA) 10000 1 10 100 1000 Collector Current--- IC(mA) 10000 Power Derating Curve Power Derating Curve 16 1.2 14 1 Power Dissipation---PD(W) Power Dissipation---PD(W) 10000 10000 10000 0.8 0.6 0.4 0.2 12 10 8 6 4 2 0 0 0 TIP50J3 IC=5IB 25 50 75 100 125 150 Ambient Temperature---TA(℃) 175 200 0 25 50 75 100 125 150 Case Temperature---TC(℃) 175 200 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 4/7 Recommended soldering footprint TIP50J3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 5/7 Reel Dimension Carrier Tape Dimension TIP50J3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 6/7 Recommended wave soldering condition Product Pb-free devices Peak Temperature 260 +0/-5 °C Soldering Time 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Average ramp-up rate (Tsmax to Tp) Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) Time maintained above: −Temperature (TL) − Time (tL) Peak Temperature(TP) Time within 5°C of actual peak temperature(tp) Ramp down rate Time 25 °C to peak temperature TIP50J3 Sn-Pb eutectic Assembly Pb-free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 240 +0/-5 °C 217°C 60-150 seconds 260 +0/-5 °C 10-30 seconds 20-40 seconds 6°C/second max. 6 minutes max. 6°C/second max. 8 minutes max. CYStek Product Specification Spec. No. : C827J3 Issued Date : 2010.03.16 Revised Date : 2013.12.19 Page No. : 7/7 CYStech Electronics Corp. TO-252 Dimension Marking: 4 Device Name TIP50 Date Code □□□□ 1 3-Lead TO-252 Plastic Surface Mount Package CYStek Package Code: J3 Inches Min. Max. 0.087 0.094 0.000 0.005 0.039 0.048 0.026 0.034 0.026 0.034 0.018 0.023 0.018 0.023 0.256 0.264 0.201 0.215 0.236 0.244 DIM A A1 B b b1 C C1 D D1 E Millimeters Min. Max. 2.200 2.400 0.000 0.127 0.990 1.210 0.660 0.860 0.660 0.860 0.460 0.580 0.460 0.580 6.500 6.700 5.100 5.460 6.000 6.200 2 3 Style: Pin 1.Base 2.Collector 3.Emitter 4.Collector DIM e e1 H K L L1 L2 L3 P V Inches Min. Max. 0.086 0.094 0.172 0.188 0.163 REF 0.190 REF 0.386 0.409 0.114 REF 0.055 0.067 0.024 0.039 0.026 REF 0.211 REF Millimeters Min. Max. 2.186 2.386 4.372 4.772 4.140 REF 4.830 REF 9.800 10.400 2.900 REF 1.400 1.700 0.600 1.000 0.650 REF 5.350 REF Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead : Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. TIP50J3 CYStek Product Specification