ITF86172SK8T
Data Sheet
10A, 30V, 0.016 Ohm, P-Channel, Logic
Level, Power MOSFET
January 2000
File Number
4809.1
Features
• Ultra Low On-Resistance
[ /Title
- rDS(ON) = 0.016Ω, VGS = −10V
Packaging
(HUF7
- rDS(ON) = 0.023Ω, VGS = −4.5V
SO8 (JEDEC MS-012AA)
- rDS(ON) = 0.026Ω, VGS = −4V
6400S
BRANDING DASH
• Gate to Source Protection Diode
K8)
• Simulation Models
/Sub- Temperature Compensated PSPICE™ and SABER
ject
5
Electrical Models
(60V,
Spice and SABER Thermal Impedance Models
1
0.072
2
- www.intersil.com
3
Ohm,
4
• Peak Current vs Pulse Width Curve
4A, N• Transient Thermal Impedance Curve vs Board Mounting
ChanSymbol
Area
nel,
• Switching Time vs RGS Curves
Logic
SOURCE(1)
DRAIN(8)
Level
Ordering Information
SOURCE(2)
DRAIN(7)
UltraFE
T
PART NUMBER
PACKAGE
BRAND
Power
ITF86172SK8T
SO8
86172
SOURCE(3)
DRAIN(6)
MOSNOTE: When ordering, use the entire part number. ITF86172SK8T
DRAIN(5)
is available only in tape and reel.
GATE(4)
FET)
/Author
()
/Keywords
Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified
ITF86172SK8T
UNITS
(InterDrain
to
Source
Voltage
(Note
1)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
V
-30
V
DSS
sil
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
-30
V
SemiGate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
conduc- Drain Current
tor, NContinuous (TA= 25oC, VGS = 10V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
10.0
A
Continuous (TA= 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
8.0
A
ChanContinuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
5.0
A
nel,
Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
5.0
A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Figure 4
Logic
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
2.5
W
Level
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
mW/oC
UltraFE Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
oC
-55 to 150
J STG
T
Maximum Temperature for Soldering
oC
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
300
Power
o
Package Body for 10s, See Tech brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
260
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 10 second.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc.http://www.intersil.com or 321-727-9207 | Copyright © Intersil Corporation 1999
ITF86172SK8T
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
-30
-
-
V
Zero Gate Voltage Drain Current
IDSS
VDS = -30V, VGS = 0V
-
-
-1
µA
Gate to Source Leakage Current
IGSS
VGS = ±20V
-
-
±10
uA
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V Figure 11
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA Figure 10
-1.0
-
-2.5
V
Drain to Source On Resistance
rDS(ON)
ID = 10.0A, VGS = -10V Figures 8,9
-
0.0125
0.016
Ω
ID = 5.0A, VGS = -4.5V Figure 8
-
0.017
0.023
Ω
ID = 5.0A, VGS = -4.0V Figure 8
-
0.019
0.026
Ω
Pad Area = 0.76 in2 (490.3 mm2) (Note 2)
-
-
50
oC/W
Pad Area = 0.054 in2 (34.8 mm2) Figure 20
-
-
152
oC/W
Pad Area = 0.0115 in2 (7.42 mm2) Figure 20
-
-
189
oC/W
VDD = -15V, ID = 5.0A
VGS = -4.5V,
RGS = 7.5Ω
Figures 14, 18, 19
-
20
-
ns
-
87
-
ns
-
48
-
ns
-
62
-
ns
-
12
-
ns
-
81
-
ns
-
76
-
ns
-
80
-
ns
-
38
-
nC
-
22
-
nC
-
2
-
nC
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = -4.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
SWITCHING SPECIFICATIONS (VGS = -10V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -15V, ID = 10.0A
VGS = -10V,
RGS = 7.5Ω
Figures 15, 18, 19
tf
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to -10V
Gate Charge at -5V
Qg(-5)
VGS = 0V to -5V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -1V
VDD = -15V,
ID = 8.0A,
Ig(REF) = -1.0mA
Figures 13, 16, 17
Gate to Source Gate Charge
Qgs
-
6.8
-
nC
Gate to Drain “Miller” Charge
Qgd
-
9.2
-
nC
-
1930
-
pF
-
470
-
pF
-
215
-
pF
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -25V, VGS = 0V,
f = 1MHz
Figure 12
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ISD = -8.0A
-
-0.8
-
V
trr
ISD = -8.0A, dISD/dt = 100A/µs
-
26
-
ns
QRR
ISD = -8.0A, dISD/dt = 100A/µs
-
13
-
nC
ITF86172SK8T
1.2
-12
1.0
-10
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
VGS = -10V, RθJA = 50oC/W
-8
-6
-4
VGS = -4.0V, RθJA = 189oC/W
-2
0.2
0
0
0
25
50
75
100
125
25
150
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
3
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 50oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
-800
RθJA = 50oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
-100
125
VGS = -4.5V
-10
150 - TA
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF86172SK8T
Typical Performance Curves
-40
RθJA = 50oC/W
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
-500
(Continued)
-100
100µs
-10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-30
-20
TJ = 150oC
-10
TJ = 25oC
10ms
-1
-1
-10
TJ = -55oC
0
-60
-1.5
-2.0
-2.5
-3.0
VGS, GATE TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
30
-30
VGS = -3.5V
VGS = -3V
-20
-10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
-40
VGS = -10V
VGS = -5V
VGS = -4.5V
VGS = -4V
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = -10A
25
20
ID = -2A
15
10
0
-0.5
-1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-2
-1.5
FIGURE 7. SATURATION CHARACTERISTICS
-3
-5
-7
-4
-6
-8
VGS, GATE TO SOURCE VOLTAGE (V)
-9
-10
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.2
VGS = -10V, ID = -10A
1.4
VGS = VDS, ID = -250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-3.5
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF86172SK8T
Typical Performance Curves
(Continued)
3000
ID = -250µA
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.10
1.05
1.00
0.95
1000
CRSS = CGD
VGS = 0V, f = 1MHz
0.90
-80
-40
0
40
80
120
100
-0.1
160
-1.0
TJ , JUNCTION TEMPERATURE (oC)
-10
-30
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-10
250
VDD = -15V
VGS = -4.5V, VDD = -15V, ID = -5A
-8
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
COSS ≅ CDS + CGD
-6
-4
WAVEFORMS IN
DESCENDING ORDER:
ID = -10A
ID = -2A
-2
200
tr
tf
150
td(OFF)
100
td(ON)
50
0
0
0
10
20
30
Qg, GATE CHARGE (nC)
40
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
300
VGS = -10V, VDD = -15V, ID = -10A
SWITCHING TIME (ns)
250
td(OFF)
200
tf
150
tr
100
50
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
50
ITF86172SK8T
Test Circuits and Waveforms
Qgs
VDS
RL
Qgd
VDS
Qg(TH)
0
VGS= -1V
VGS
VGS= -5V
-VGS
VDD
Qg(-5)
+
VGS= -10V
VDD
DUT
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
RL
VDS
-
10%
10%
+
VGS
VDS
0V
DUT
RGS
tf
tr
0
0
90%
90%
10%
-VGS
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
90%
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be reviewed
to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as the
basis for establishing the rating of the part.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
6
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
ITF86172SK8T
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a coefficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 83.2 – 23.6 ×
ln ( Area )
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
240
RθJA = 83.2 - 23.6*ln(AREA)
200
RθJA (oC/W)
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
152oC/W - 0.054in2
160
120
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
189oC/W - 0.0115in2
80
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
150
ZθJA, THERMAL
IMPEDANCE (oC/W)
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
102
103
ITF86172SK8T
PSPICE Electrical Model
.SUBCKT ITF86172SK8 2 1 3 ;
REV 24 November 1999
CA 12 8 1.70e-9
CB 15 14 1.70e-9
CIN 6 8 1.80e-9
-
10
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
RSLC2
EBREAK 5 11 17 18 -35.25
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
5
51
EBREAK
+
17
18
-
ESLC
-
50
DPLCAP
LGATE
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
9
-
20
21
16
MWEAK
6
18 +
22
DBREAK
MSTRO
DESD1
91
DESD2
11
MMED
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
DBODY
RDRAIN
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
LDRAIN
ESG
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.90E-3
RGATE 9 20 5.20
RLDRAIN 2 5 10
RLGATE 1 9 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 7.75e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
CA
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
S1A
S1B
S2A
S2B
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),9))}
.MODEL DBODYMOD D (IS = 3.00e-12 RS = 7.15e-3 TRS1 = 1.54e-3 TRS2 = -2.48e-6 CJO = 1.25e-9 TT = 6.5e-10 VJ=0.65 M = 0.44)
.MODEL DBREAKMOD D (RS = 1.50e-1 TRS1 = 1.00e-3 TRS2 = 1.00e-6)
.MODEL DESD1MOD D (BV=18.3 TBV1=-1.43E-3 TBV2=0 RS=100 N=13)
.MODEL DESD2MOD D (BV=18.15 TBV1=-1.43E-3 TBV2=0 RS=100 N=13)
.MODEL DPLCAPMOD D (CJO = 9.20e-10 IS = 1e-30 N=10 VJ=0.4 M = 0.36)
.MODEL MMEDMOD PMOS (VTO = -1.61 KP = 2.6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.20)
.MODEL MSTROMOD PMOS (VTO = -1.94 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u LAMBDA=0.014)
.MODEL MWEAKMOD PMOS (VTO = -1.35 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 52.0)
.MODEL RBREAKMOD RES (TC1 = 6.70e-4 TC2 = -1.02E-6)
.MODEL RDRAINMOD RES (TC1 = 1.24e-2 TC2 = 7.00e-6)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = -3.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = 1.50e-3 TC2 = 6.20e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.00e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 6.2 VOFF= 3.1)
VON = 3.1 VOFF= 6.2)
VON = 1.0 VOFF= -0.5)
VON = -0.5 VOFF= 1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
ITF86172SK8T
SABER Electrical Model
REV 24 November1999
template ITF86172SK8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.00e-12, cjo = 1.25e-9, tt = 6.5e-10, vj=0.65, m = 0.44, rs = 7.15e-3, trs1 = 1.54e-3, trs2 = -2.48e-6)
dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1.00e-3, trs2 = 1.00e-6)
dp..desd1mod = (bv=18.3, tbv1=-1.43e-3, tbv2=0, rs=100, nl=13)
dp..desd2mod = (bv=18.15, tbv1=-1.43e-3, tbv2=0, rs=100, nl=13)
dp..model dplcapmod = (cjo = 9.20e-10, isl = 1e-30, nl = 10, vj=0.4, m = 0.36)
m..model mmedmod = (type=_p, vto = -1.61, kp = 2.6, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_p, vto = -1.94, kp = 55, is = 1e-30, tox = 1, lambda=0.014)
ESG
m..model mweakmod = (type=_p, vto = -1.35, kp = 0.08, is = 1e-30, tox = 1)
5
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 6.2, voff = 3.1)
- 8 +
6
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 3.1, voff = 6.2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 1.0, voff = -0.5)
+
10
RSLC1
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 1.0)
EBREAK 17
51
DRAIN
2
RLDRAIN
18
RSLC2
c.ca n12 n8 = 1.70e-9
c.cb n15 n14 = 1.70e-9
c.cin n6 n8 = 1.80e-9
LDRAIN
-
ISCL
11
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.dplcap n10 n6 = model=dplcapmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
i.it n8 n17 = 1
50
DPLCAP
RDRAIN
LGATE
RGATE
GATE
1
RLGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.04e-9
l.lsource n3 n7 = 1.29e-10
EVTHRES
+ 19 8
EVTEMP
-
20
9
16
21
MSTRO
DBREAK
CIN
91
8
DESD2
LSOURCE
7
RSOURCE
RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A
12
CA
S2A
RBREAK
13
8
15
14
13
S1B
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 9))
}
}
19
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = -35.25
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
9
DBODY
MMED
DESD1
res.rbreak n17 n18 = 1, tc1 = 6.70e-4, tc2 = -1.02e-6
res.rdrain n50 n16 = 2.90e-3, tc1 = 1.24e-2, tc2 = 7.00e-6
res.rgate n9 n20 = 5.20
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10.4
res.rlsource n3 n7 = 1.29
res.rslc1 n5 n51 = 1e-6, tc1 = 2.00e-3, tc2 = -3.00e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 7.75e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.00e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = 1.50e-3, tc2 = 6.20e-6
MWEAK
6
18 +
22
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
ITF86172SK8T
SPICE Thermal Model
REV 28 July 1999
ITF86172SK8
Copper Area = 0.76 in2
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2.0e-1
CTHERM7 3 2 1
CTHERM8 2 tl 3
JUNCTION
th
CTHERM1
RTHERM1
8
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 13
RTHERM7 3 2 19
RTHERM8 2 tl 29.7
CTHERM2
RTHERM2
7
CTHERM3
RTHERM3
6
RTHERM4
SABER Thermal Model
Copper Area = 0.76 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 2.0e-1
ctherm.ctherm7 3 2 = 1
ctherm.ctherm8 2 tl = 3
CTHERM4
5
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 13
rtherm.rtherm7 3 2 = 19
rtherm.rtherm8 2 tl = 29.7
}
2
CTHERM8
RTHERM8
tl
CASE
TABLE 1. Thermal Models
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONENT
10
ITF86172SK8T
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
INCHES
A
A1
1
e
2
6
D
5
b
SYMBOL
c
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
0.050
1.27
0.024
0.6
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
h x 45o
MIN
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
1.75mm
CL
MS-012AA
12mm
12mm TAPE AND REEL
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
11
50mm
12.4mm
ITF86172SK8T
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil Corporation
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TEL: (321) 724-7000
FAX: (321) 724-7240
12
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