HUF76113DK8
TM
Data Sheet
June 2000
6A, 30V, 0.032 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
File Number
4387.5
Features
• Logic Level Gate Drive
This N-Channel power MOSFET is
® manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and batteryoperated products.
• 6A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.032Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA76113.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
HUF76113DK8
PACKAGE
MS-012AA
BRAND
D1(8)
D1(7)
76113DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76113DK8T.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
1
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER™ is a trademark of Analogy, Inc. | 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000.
HUF76113DK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
HUF76113DK8
30
30
±16
UNITS
V
V
V
6
1.8
1.7
Figure 4
Figure 6
2.5
0.02
-55 to 150
A
A
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in2 footprint at 1000 seconds.
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
-
-
V
VDS = 25V, VGS = 0V
-
-
1
µA
VDS = 25V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 12)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 6A, VGS = 10V (Figures 9, 10)
-
0.026
0.032
Ω
ID = 1.8A, VGS = 5V (Figure 9)
-
0.033
0.041
Ω
ID = 1.7A, VGS = 4.5V (Figure 9)
-
0.035
0.043
Ω
Pad Area = 0.76 in2 (Note 2)
-
-
50
oC/W
Pad Area = 0.027 in2 (See TB377)
-
-
191
oC/W
Pad Area = 0.006 in2 (See TB377)
-
-
228
oC/W
VDD = 15V, ID ≅ 1.7A, RL = 8.8Ω,
VGS = 4.5V, RGS = 18Ω,
(Figure 15)
-
-
110
ns
-
17
-
ns
tr
-
57
-
ns
td(OFF)
-
32
-
ns
tf
-
38
-
ns
tOFF
-
-
105
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
2
HUF76113DK8
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 15V, ID ≅ 6A, RL = 2.5Ω, VGS = 10V,
RGS = 18Ω
(Figure 16)
-
-
60
ns
-
6.5
-
ns
tr
-
33
-
ns
td(OFF)
-
50
-
ns
tf
-
40
-
ns
tOFF
-
-
135
ns
-
16.0
19.2
nC
-
8.4
10.2
nC
-
0.55
0.66
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 15V, ID ≅ 1.8A,
RL = 8.3Ω
Ig(REF) = 1.0mA
(Figure 14)
Gate to Source Gate Charge
Qgs
-
1.50
-
nC
Gate to Drain “Miller” Charge
Qgd
-
3.90
-
nC
-
605
-
pF
-
275
-
pF
-
40
-
pF
MIN
TYP
MAX
UNITS
-
-
1.25
V
1.00
V
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
TEST CONDITIONS
ISD = 6A
ISD = 1.8A
Reverse Recovery Time
Reverse Recovered Charge
trr
ISD = 1.8A, dISD/dt = 100A/µs
-
-
40
ns
QRR
ISD = 1.8A, dISD/dt = 100A/µs
-
-
42
nC
1.2
7
1.0
6
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
VGS = 10V, RθJA = 50oC/W
5
4
3
2
VGS = 4.5V, RθJA = 228oC/W
1
0
0
0
25
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
3
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
HUF76113DK8
Typical Performance Curves
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
(Continued)
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 228oC/W
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
100
RθJA = 228oC/W
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
VGS = 10V
CURRENT AS FOLLOWS:
I
= I25
150 - TA
125
VGS = 5V
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
102
103
FIGURE 4. PEAK CURRENT CAPABILITY
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TA = 25oC
100
100µs
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
VDSS(MAX) = 30V
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
4
IAS, AVALANCHE CURRENT (A)
50
500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.1
100
1
10
tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
HUF76113DK8
Typical Performance Curves
30
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
15
10
25oC
0
VGS = 3.5V
15
10
-55oC
0
5
FIGURE 7. TRANSFER CHARACTERISTICS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID = 6A
150
ID = 1.8A
100
50
0
2
0
4
6
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 6A
1.4
1.2
1.0
0.8
0.6
-80
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
0
40
80
120
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.1
1.0
0.9
0.8
0.7
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
5
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
-40
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
0.6
-80
5
FIGURE 8. SATURATION CHARACTERISTICS
200
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 3V
5
1
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
0
VGS = 10V
VGS = 5V
VGS = 4.5V
20
150oC
5
VGS = 4V
25
ID, DRAIN CURRENT (A)
25
ID, DRAIN CURRENT (A)
(Continued)
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF76113DK8
Typical Performance Curves
(Continued)
C, CAPACITANCE (pF)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
800
CISS
600
400
COSS
200
CRSS
0
VGS , GATE TO SOURCE VOLTAGE (V)
10
1000
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 6A
ID = 1.8A
2
0
0
5
10
15
20
25
30
0
5
10
15
20
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
150
120
VGS = 10V, VDD = 15V, ID = 6A, RL= 2.5Ω
tr
90
SWITCHING TIME (ns)
SWITCHING TIME (ns)
VGS = 4.5V, VDD = 15V, ID = 1.7A, RL= 8.8Ω
tf
60
td(OFF)
30
td(ON)
120
td(OFF)
90
tf
60
tr
30
td(ON)
0
0
10
20
30
40
0
50
0
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
6
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76113DK8
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
3. The use of external heat sinks.
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
4. The use of thermal vias.
( T JM – T A )
P DM = ------------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and
influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
7
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the Electrical
Specifications table. The points were chosen to depict the
compromise between the copper board area, the thermal
resistance and ultimately the power dissipation, PDM.
HUF76113DK8
Thermal resistances corresponding to other copper areas can
be obtained from Figure 23 or by calculation using Equation 2.
RθJA is defined as the natural log of the area times a cofficient
added to a constant. The area, in square inches is the top
copper area including the gate and source pads.
R θJA = 103.2 – 24.3 ×
ln ( Area )
300
RθJA = 103.2 - 24.3
Rθβ, RθJA (oC/W)
250
(EQ. 2)
* ln(AREA)
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
Rθβ1 = Rθβ2 = 97oC/W
TJ1 and TJ2 define the junction temerature of the respective
die. Similarly, P1 and P2 define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70˚C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate TJ1 and and Equation 5 to
calulate TJ2..
T J1 = P 1 R θJA + P 2 R θβ + T A
150
(EQ. 4)
TJ1 = (0 Watts)(159˚C/W) + (0.5 Watts)(97˚C/W) + 70˚C
100
TJ1 = 119˚C
50
T J2 = P 2 R θJA + P 1 R θβ + T A
Rθβ = 46.4 - 21.7 * ln(AREA)
0
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2) PER DIE
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFETs are offered with two
die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
Rθβ
= 46.4 – 21.7 ×
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (RθJA) and thermal coupling resistance
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 159oC/W
IMPEDANCE (oC/W)
ZθJA, THERMAL
160
120
(EQ. 5)
TJ2 = (0.5 Watts)(159oC/W) + (0 Watts)(97oC/W) + 70oC
TJ2 = 150oC
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
80
40
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
8
102
103
HUF76113DK8
PSPICE Electrical Model
.SUBCKT HUF76113 2 1 3 ;
REV July 1998
CA 12 8 8.50e-10
CB 15 14 8.05e-10
CIN 6 8 5.71e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DBREAK
+
RSLC2
5
51
ESLC
11
-
EBREAK 11 7 17 18 38.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 9.67e-10
LSOURCE 3 7 3.27e-10
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.04e-3
RGATE 9 20 2.65
RLDRAIN 2 5 10
RLGATE 1 9 9.67
RLSOURCE 3 7 3.27
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 25.0e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
RLDRAIN
RSLC1
51
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
-
-
IT
14
+
+
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*256),2))}
.MODEL DBODYMOD D (IS = 8.35e-13 RS = 1.39e-2 TRS1 = 1.03e-3 TRS2 = 6.85e-6 CJO = 9.11e-10 TT = 2.14e-8 M = 0.42)
.MODEL DBREAKMOD D (RS = 8.21e-2 TRS1 = 2.25e-3 TRS2 = 4.14e-5)
.MODEL DPLCAPMOD D (CJO = 3.76e-10 IS = 1e-30 N = 10 M = 0.68)
.MODEL MMEDMOD NMOS (VTO = 2.03 KP = 3.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.65)
.MODEL MSTROMOD NMOS (VTO = 2.36 KP = 50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.77 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 1e-7)
.MODEL RDRAINMOD RES (TC1 = 3.67e-2 TC2 = 4.11e-5)
.MODEL RSLCMOD RES (TC1 = 2.26e-3 TC2 = 1.23e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -2.97e-3 TC2 = -5.91e-6)
.MODEL RVTEMPMOD RES (TC1 = -7.41e-4 TC2 = 9.41e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -6.05 VOFF= -2.00)
VON = -2.00 VOFF= -6.05)
VON = 0.00 VOFF= 0.60)
VON = 0.60 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
HUF76113DK8
SABER Electrical Model
REV July 1998
template huf76113 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 8.35e-13, cjo = 9.11e-10, tt = 2.14e-8, m = 0.42)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.76e-10, is = 1e-30, n = 10, m = 0.68)
m..model mmedmod = (type=_n, vto = 2.03, kp = 3.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.36, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.77, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.05, voff = -2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.05)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.6)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.6, voff = 0)
LDRAIN
DPLCAP
DRAIN
2
5
10
RSLC1
51
c.ca n12 n8 = 8.5e-10
c.cb n15 n14 = 8.05e-10
c.cin n6 n8 = 5.71e-10
RLDRAIN
RDBREAK
RSLC2
72
ISCL
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 9.67e-10
l.lsource n3 n7 = 3.27e-10
EVTEMP
RGATE + 18 22
9
20
16
MWEAK
DBODY
EBREAK
+
17
18
MSTRO
CIN
71
11
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
-
8
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/256))** 2))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 38.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
10
21
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = 1e-7
res.rdbody n71 n5 = 1.39e-2, tc1 = 1.03e-3, tc2 = 6.85e-6
res.rdbreak n72 n5 = 8.21e-2, tc1 = 2.25e-3, tc2 = 4.14e-5
res.rdrain n50 n16 = 3.04e-3, tc1 = 3.67e-2, tc2 = 4.11e-5
res.rgate n9 n20 = 2.65
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 9.67
res.rlsource n3 n7 = 3.27
res.rslc1 n5 n51 = 1e-6, tc1 = 2.26e-3, tc2 = 1.23e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 25e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -7.41e-4, tc2 = 9.41e-7
res.rvthres n22 n8 = 1, tc1 = -2.97e-3, tc2 = -5.91e-6
DBREAK
50
-
RDBODY
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF76113DK8
SPICE Thermal Model
th
REV June 1998
HUF76113DK8
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
7
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
CTHERM3
RTHERM3
6
RTHERM4
CTHERM4
5
SABER Thermal Model
CTHERM5
RTHERM5
Copper Area = 0.02 in2
4
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
2
CTHERM8
RTHERM8
rtherm.rtherm1 th 8 = 3.0e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 3.8
rtherm.rtherm4 6 5 = 9.5
rtherm.rtherm5 5 4 = 25
rtherm.rtherm6 4 3 = 38
rtherm.rtherm7 3 2 = 25
rtherm.rtherm8 2 tl = 38
}
tl
CASE
TABLE 1. Thermal Models
COMPONANT
0.02 in2
0.14 in2
0.25 in2
0.38 in2
0.50 in2
CTHERM6
9.0e-2
1.3e-1
1.5e-1
1.5e-1
1.5e-1
CTHERM7
4.0e-1
6.0e-1
4.5e-1
6.5e-1
7.5e-1
CTHERM8
1.4
2.5
2.2
3
3
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
11
HUF76113DK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
INCHES
A
A1
1
e
2
6
D
5
b
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
h x 45o
c
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
0.050
1.27
0.024
0.6
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
MILLIMETERS
SYMBOL
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
1.75mm
CL
MS-012AA
12mm
12mm TAPE AND REEL
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
12
50mm
12.4mm